0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003 * Abilis Systems TB10X SOC device tree
0004 *
0005 * Copyright (C) Abilis Systems 2013
0006 *
0007 * Author: Christian Ruppert <christian.ruppert@abilis.com>
0008 */
0009
0010
0011 / {
0012 compatible = "abilis,arc-tb10x";
0013 #address-cells = <1>;
0014 #size-cells = <1>;
0015
0016 cpus {
0017 #address-cells = <1>;
0018 #size-cells = <0>;
0019 cpu@0 {
0020 device_type = "cpu";
0021 compatible = "snps,arc770d";
0022 reg = <0>;
0023 };
0024 };
0025
0026 /* TIMER0 with interrupt for clockevent */
0027 timer0 {
0028 compatible = "snps,arc-timer";
0029 interrupts = <3>;
0030 interrupt-parent = <&intc>;
0031 clocks = <&cpu_clk>;
0032 };
0033
0034 /* TIMER1 for free running clocksource */
0035 timer1 {
0036 compatible = "snps,arc-timer";
0037 clocks = <&cpu_clk>;
0038 };
0039
0040 soc100 {
0041 #address-cells = <1>;
0042 #size-cells = <1>;
0043 device_type = "soc";
0044 ranges = <0xfe000000 0xfe000000 0x02000000
0045 0x000f0000 0x000f0000 0x00010000>;
0046 compatible = "abilis,tb10x", "simple-bus";
0047
0048 pll0: oscillator {
0049 compatible = "fixed-clock";
0050 #clock-cells = <0>;
0051 clock-output-names = "pll0";
0052 };
0053 cpu_clk: clkdiv_cpu {
0054 compatible = "fixed-factor-clock";
0055 #clock-cells = <0>;
0056 clocks = <&pll0>;
0057 clock-output-names = "cpu_clk";
0058 };
0059 ahb_clk: clkdiv_ahb {
0060 compatible = "fixed-factor-clock";
0061 #clock-cells = <0>;
0062 clocks = <&pll0>;
0063 clock-output-names = "ahb_clk";
0064 };
0065
0066 iomux: iomux@ff10601c {
0067 compatible = "abilis,tb10x-iomux";
0068 #gpio-range-cells = <3>;
0069 reg = <0xff10601c 0x4>;
0070 };
0071
0072 intc: interrupt-controller {
0073 compatible = "snps,arc700-intc";
0074 interrupt-controller;
0075 #interrupt-cells = <1>;
0076 };
0077 tb10x_ictl: pic@fe002000 {
0078 compatible = "abilis,tb10x-ictl";
0079 reg = <0xfe002000 0x20>;
0080 interrupt-controller;
0081 #interrupt-cells = <2>;
0082 interrupt-parent = <&intc>;
0083 interrupts = <5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
0084 20 21 22 23 24 25 26 27 28 29 30 31>;
0085 };
0086
0087 uart@ff100000 {
0088 compatible = "snps,dw-apb-uart";
0089 reg = <0xff100000 0x100>;
0090 clock-frequency = <166666666>;
0091 interrupts = <25 8>;
0092 reg-shift = <2>;
0093 reg-io-width = <4>;
0094 interrupt-parent = <&tb10x_ictl>;
0095 };
0096 ethernet@fe100000 {
0097 compatible = "snps,dwmac-3.70a","snps,dwmac";
0098 reg = <0xfe100000 0x1058>;
0099 interrupt-parent = <&tb10x_ictl>;
0100 interrupts = <6 8>;
0101 interrupt-names = "macirq";
0102 clocks = <&ahb_clk>;
0103 clock-names = "stmmaceth";
0104 };
0105 dma@fe000000 {
0106 compatible = "snps,dma-spear1340";
0107 reg = <0xfe000000 0x400>;
0108 interrupt-parent = <&tb10x_ictl>;
0109 interrupts = <14 8>;
0110 dma-channels = <6>;
0111 dma-requests = <0>;
0112 dma-masters = <1>;
0113 #dma-cells = <3>;
0114 chan_allocation_order = <0>;
0115 chan_priority = <1>;
0116 block_size = <0x7ff>;
0117 data-width = <4>;
0118 clocks = <&ahb_clk>;
0119 clock-names = "hclk";
0120 multi-block = <1 1 1 1 1 1>;
0121 };
0122
0123 i2c0: i2c@ff120000 {
0124 #address-cells = <1>;
0125 #size-cells = <0>;
0126 compatible = "snps,designware-i2c";
0127 reg = <0xff120000 0x1000>;
0128 interrupt-parent = <&tb10x_ictl>;
0129 interrupts = <12 8>;
0130 clocks = <&ahb_clk>;
0131 };
0132 i2c1: i2c@ff121000 {
0133 #address-cells = <1>;
0134 #size-cells = <0>;
0135 compatible = "snps,designware-i2c";
0136 reg = <0xff121000 0x1000>;
0137 interrupt-parent = <&tb10x_ictl>;
0138 interrupts = <12 8>;
0139 clocks = <&ahb_clk>;
0140 };
0141 i2c2: i2c@ff122000 {
0142 #address-cells = <1>;
0143 #size-cells = <0>;
0144 compatible = "snps,designware-i2c";
0145 reg = <0xff122000 0x1000>;
0146 interrupt-parent = <&tb10x_ictl>;
0147 interrupts = <12 8>;
0148 clocks = <&ahb_clk>;
0149 };
0150 i2c3: i2c@ff123000 {
0151 #address-cells = <1>;
0152 #size-cells = <0>;
0153 compatible = "snps,designware-i2c";
0154 reg = <0xff123000 0x1000>;
0155 interrupt-parent = <&tb10x_ictl>;
0156 interrupts = <12 8>;
0157 clocks = <&ahb_clk>;
0158 };
0159 i2c4: i2c@ff124000 {
0160 #address-cells = <1>;
0161 #size-cells = <0>;
0162 compatible = "snps,designware-i2c";
0163 reg = <0xff124000 0x1000>;
0164 interrupt-parent = <&tb10x_ictl>;
0165 interrupts = <12 8>;
0166 clocks = <&ahb_clk>;
0167 };
0168
0169 spi0: spi@fe010000 {
0170 #address-cells = <1>;
0171 #size-cells = <0>;
0172 cell-index = <0>;
0173 compatible = "abilis,tb100-spi";
0174 num-cs = <1>;
0175 reg = <0xfe010000 0x20>;
0176 interrupt-parent = <&tb10x_ictl>;
0177 interrupts = <26 8>;
0178 clocks = <&ahb_clk>;
0179 };
0180 spi1: spi@fe011000 {
0181 #address-cells = <1>;
0182 #size-cells = <0>;
0183 cell-index = <1>;
0184 compatible = "abilis,tb100-spi";
0185 num-cs = <2>;
0186 reg = <0xfe011000 0x20>;
0187 interrupt-parent = <&tb10x_ictl>;
0188 interrupts = <10 8>;
0189 clocks = <&ahb_clk>;
0190 };
0191
0192 tb10x_tsm: tb10x-tsm@ff316000 {
0193 compatible = "abilis,tb100-tsm";
0194 reg = <0xff316000 0x400>;
0195 interrupt-parent = <&tb10x_ictl>;
0196 interrupts = <17 8>;
0197 output-clkdiv = <4>;
0198 global-packet-delay = <0x21>;
0199 port-packet-delay = <0>;
0200 };
0201 tb10x_stream_proc: tb10x-stream-proc {
0202 compatible = "abilis,tb100-streamproc";
0203 reg = <0xfff00000 0x200>,
0204 <0x000f0000 0x10000>,
0205 <0xfff00200 0x105>,
0206 <0xff10600c 0x1>,
0207 <0xfe001018 0x1>;
0208 reg-names = "mbox",
0209 "sp_iccm",
0210 "mbox_irq",
0211 "cpuctrl",
0212 "a6it_int_force";
0213 interrupt-parent = <&tb10x_ictl>;
0214 interrupts = <20 2>, <19 2>;
0215 interrupt-names = "cmd_irq", "event_irq";
0216 };
0217 tb10x_mdsc0: tb10x-mdscr@ff300000 {
0218 compatible = "abilis,tb100-mdscr";
0219 reg = <0xff300000 0x7000>;
0220 tb100-mdscr-manage-tsin;
0221 };
0222 tb10x_mscr0: tb10x-mdscr@ff307000 {
0223 compatible = "abilis,tb100-mdscr";
0224 reg = <0xff307000 0x7000>;
0225 };
0226 tb10x_scr0: tb10x-mdscr@ff30e000 {
0227 compatible = "abilis,tb100-mdscr";
0228 reg = <0xff30e000 0x4000>;
0229 tb100-mdscr-manage-tsin;
0230 };
0231 tb10x_scr1: tb10x-mdscr@ff312000 {
0232 compatible = "abilis,tb100-mdscr";
0233 reg = <0xff312000 0x4000>;
0234 tb100-mdscr-manage-tsin;
0235 };
0236 tb10x_wfb: tb10x-wfb@ff319000 {
0237 compatible = "abilis,tb100-wfb";
0238 reg = <0xff319000 0x1000>;
0239 interrupt-parent = <&tb10x_ictl>;
0240 interrupts = <16 8>;
0241 };
0242 };
0243 };
