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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /* ----------------------------------------------------------------------- *
0003  *
0004  *   Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
0005  *
0006  * ----------------------------------------------------------------------- */
0007 
0008 /*
0009  * raid6/x86.h
0010  *
0011  * Definitions common to x86 and x86-64 RAID-6 code only
0012  */
0013 
0014 #ifndef LINUX_RAID_RAID6X86_H
0015 #define LINUX_RAID_RAID6X86_H
0016 
0017 #if (defined(__i386__) || defined(__x86_64__)) && !defined(__arch_um__)
0018 
0019 #ifdef __KERNEL__ /* Real code */
0020 
0021 #include <asm/fpu/api.h>
0022 
0023 #else /* Dummy code for user space testing */
0024 
0025 static inline void kernel_fpu_begin(void)
0026 {
0027 }
0028 
0029 static inline void kernel_fpu_end(void)
0030 {
0031 }
0032 
0033 #define __aligned(x) __attribute__((aligned(x)))
0034 
0035 #define X86_FEATURE_MMX     (0*32+23) /* Multimedia Extensions */
0036 #define X86_FEATURE_FXSR    (0*32+24) /* FXSAVE and FXRSTOR instructions
0037                        * (fast save and restore) */
0038 #define X86_FEATURE_XMM     (0*32+25) /* Streaming SIMD Extensions */
0039 #define X86_FEATURE_XMM2    (0*32+26) /* Streaming SIMD Extensions-2 */
0040 #define X86_FEATURE_XMM3    (4*32+ 0) /* "pni" SSE-3 */
0041 #define X86_FEATURE_SSSE3   (4*32+ 9) /* Supplemental SSE-3 */
0042 #define X86_FEATURE_AVX (4*32+28) /* Advanced Vector Extensions */
0043 #define X86_FEATURE_AVX2        (9*32+ 5) /* AVX2 instructions */
0044 #define X86_FEATURE_AVX512F     (9*32+16) /* AVX-512 Foundation */
0045 #define X86_FEATURE_AVX512DQ    (9*32+17) /* AVX-512 DQ (Double/Quad granular)
0046                        * Instructions
0047                        */
0048 #define X86_FEATURE_AVX512BW    (9*32+30) /* AVX-512 BW (Byte/Word granular)
0049                        * Instructions
0050                        */
0051 #define X86_FEATURE_AVX512VL    (9*32+31) /* AVX-512 VL (128/256 Vector Length)
0052                        * Extensions
0053                        */
0054 #define X86_FEATURE_MMXEXT  (1*32+22) /* AMD MMX extensions */
0055 
0056 /* Should work well enough on modern CPUs for testing */
0057 static inline int boot_cpu_has(int flag)
0058 {
0059     u32 eax, ebx, ecx, edx;
0060 
0061     eax = (flag & 0x100) ? 7 :
0062         (flag & 0x20) ? 0x80000001 : 1;
0063     ecx = 0;
0064 
0065     asm volatile("cpuid"
0066              : "+a" (eax), "=b" (ebx), "=d" (edx), "+c" (ecx));
0067 
0068     return ((flag & 0x100 ? ebx :
0069         (flag & 0x80) ? ecx : edx) >> (flag & 31)) & 1;
0070 }
0071 
0072 #endif /* ndef __KERNEL__ */
0073 
0074 #endif
0075 #endif