lib/raid6/recov_ssse3.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 Intel Corporation
0004  */
0005
0006 #include <linux/raid/pq.h>
0007 #include "x86.h"
0008
0009 static int raid6_has_ssse3(void)
0010 {
0011     return boot_cpu_has(X86_FEATURE_XMM) &&
0012         boot_cpu_has(X86_FEATURE_XMM2) &&
0013         boot_cpu_has(X86_FEATURE_SSSE3);
0014 }
0015
0016 static void raid6_2data_recov_ssse3(int disks, size_t bytes, int faila,
0017         int failb, void **ptrs)
0018 {
0019     u8 *p, *q, *dp, *dq;
0020     const u8 *pbmul;    /* P multiplier table for B data */
0021     const u8 *qmul;     /* Q multiplier table (for both) */
0022     static const u8 __aligned(16) x0f[16] = {
0023          0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
0024          0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f};
0025
0026     p = (u8 *)ptrs[disks-2];
0027     q = (u8 *)ptrs[disks-1];
0028
0029     /* Compute syndrome with zero for the missing data pages
0030        Use the dead data pages as temporary storage for
0031        delta p and delta q */
0032     dp = (u8 *)ptrs[faila];
0033     ptrs[faila] = (void *)raid6_empty_zero_page;
0034     ptrs[disks-2] = dp;
0035     dq = (u8 *)ptrs[failb];
0036     ptrs[failb] = (void *)raid6_empty_zero_page;
0037     ptrs[disks-1] = dq;
0038
0039     raid6_call.gen_syndrome(disks, bytes, ptrs);
0040
0041     /* Restore pointer table */
0042     ptrs[faila]   = dp;
0043     ptrs[failb]   = dq;
0044     ptrs[disks-2] = p;
0045     ptrs[disks-1] = q;
0046
0047     /* Now, pick the proper data tables */
0048     pbmul = raid6_vgfmul[raid6_gfexi[failb-faila]];
0049     qmul  = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila] ^
0050         raid6_gfexp[failb]]];
0051
0052     kernel_fpu_begin();
0053
0054     asm volatile("movdqa %0,%%xmm7" : : "m" (x0f[0]));
0055
0056 #ifdef CONFIG_X86_64
0057     asm volatile("movdqa %0,%%xmm6" : : "m" (qmul[0]));
0058     asm volatile("movdqa %0,%%xmm14" : : "m" (pbmul[0]));
0059     asm volatile("movdqa %0,%%xmm15" : : "m" (pbmul[16]));
0060 #endif
0061
0062     /* Now do it... */
0063     while (bytes) {
0064 #ifdef CONFIG_X86_64
0065         /* xmm6, xmm14, xmm15 */
0066
0067         asm volatile("movdqa %0,%%xmm1" : : "m" (q[0]));
0068         asm volatile("movdqa %0,%%xmm9" : : "m" (q[16]));
0069         asm volatile("movdqa %0,%%xmm0" : : "m" (p[0]));
0070         asm volatile("movdqa %0,%%xmm8" : : "m" (p[16]));
0071         asm volatile("pxor   %0,%%xmm1" : : "m" (dq[0]));
0072         asm volatile("pxor   %0,%%xmm9" : : "m" (dq[16]));
0073         asm volatile("pxor   %0,%%xmm0" : : "m" (dp[0]));
0074         asm volatile("pxor   %0,%%xmm8" : : "m" (dp[16]));
0075
0076         /* xmm0/8 = px */
0077
0078         asm volatile("movdqa %xmm6,%xmm4");
0079         asm volatile("movdqa %0,%%xmm5" : : "m" (qmul[16]));
0080         asm volatile("movdqa %xmm6,%xmm12");
0081         asm volatile("movdqa %xmm5,%xmm13");
0082         asm volatile("movdqa %xmm1,%xmm3");
0083         asm volatile("movdqa %xmm9,%xmm11");
0084         asm volatile("movdqa %xmm0,%xmm2"); /* xmm2/10 = px */
0085         asm volatile("movdqa %xmm8,%xmm10");
0086         asm volatile("psraw  $4,%xmm1");
0087         asm volatile("psraw  $4,%xmm9");
0088         asm volatile("pand   %xmm7,%xmm3");
0089         asm volatile("pand   %xmm7,%xmm11");
0090         asm volatile("pand   %xmm7,%xmm1");
0091         asm volatile("pand   %xmm7,%xmm9");
0092         asm volatile("pshufb %xmm3,%xmm4");
0093         asm volatile("pshufb %xmm11,%xmm12");
0094         asm volatile("pshufb %xmm1,%xmm5");
0095         asm volatile("pshufb %xmm9,%xmm13");
0096         asm volatile("pxor   %xmm4,%xmm5");
0097         asm volatile("pxor   %xmm12,%xmm13");
0098
0099         /* xmm5/13 = qx */
0100
0101         asm volatile("movdqa %xmm14,%xmm4");
0102         asm volatile("movdqa %xmm15,%xmm1");
0103         asm volatile("movdqa %xmm14,%xmm12");
0104         asm volatile("movdqa %xmm15,%xmm9");
0105         asm volatile("movdqa %xmm2,%xmm3");
0106         asm volatile("movdqa %xmm10,%xmm11");
0107         asm volatile("psraw  $4,%xmm2");
0108         asm volatile("psraw  $4,%xmm10");
0109         asm volatile("pand   %xmm7,%xmm3");
0110         asm volatile("pand   %xmm7,%xmm11");
0111         asm volatile("pand   %xmm7,%xmm2");
0112         asm volatile("pand   %xmm7,%xmm10");
0113         asm volatile("pshufb %xmm3,%xmm4");
0114         asm volatile("pshufb %xmm11,%xmm12");
0115         asm volatile("pshufb %xmm2,%xmm1");
0116         asm volatile("pshufb %xmm10,%xmm9");
0117         asm volatile("pxor   %xmm4,%xmm1");
0118         asm volatile("pxor   %xmm12,%xmm9");
0119
0120         /* xmm1/9 = pbmul[px] */
0121         asm volatile("pxor   %xmm5,%xmm1");
0122         asm volatile("pxor   %xmm13,%xmm9");
0123         /* xmm1/9 = db = DQ */
0124         asm volatile("movdqa %%xmm1,%0" : "=m" (dq[0]));
0125         asm volatile("movdqa %%xmm9,%0" : "=m" (dq[16]));
0126
0127         asm volatile("pxor   %xmm1,%xmm0");
0128         asm volatile("pxor   %xmm9,%xmm8");
0129         asm volatile("movdqa %%xmm0,%0" : "=m" (dp[0]));
0130         asm volatile("movdqa %%xmm8,%0" : "=m" (dp[16]));
0131
0132         bytes -= 32;
0133         p += 32;
0134         q += 32;
0135         dp += 32;
0136         dq += 32;
0137 #else
0138         asm volatile("movdqa %0,%%xmm1" : : "m" (*q));
0139         asm volatile("movdqa %0,%%xmm0" : : "m" (*p));
0140         asm volatile("pxor   %0,%%xmm1" : : "m" (*dq));
0141         asm volatile("pxor   %0,%%xmm0" : : "m" (*dp));
0142
0143         /* 1 = dq ^ q
0144          * 0 = dp ^ p
0145          */
0146         asm volatile("movdqa %0,%%xmm4" : : "m" (qmul[0]));
0147         asm volatile("movdqa %0,%%xmm5" : : "m" (qmul[16]));
0148
0149         asm volatile("movdqa %xmm1,%xmm3");
0150         asm volatile("psraw  $4,%xmm1");
0151         asm volatile("pand   %xmm7,%xmm3");
0152         asm volatile("pand   %xmm7,%xmm1");
0153         asm volatile("pshufb %xmm3,%xmm4");
0154         asm volatile("pshufb %xmm1,%xmm5");
0155         asm volatile("pxor   %xmm4,%xmm5");
0156
0157         asm volatile("movdqa %xmm0,%xmm2"); /* xmm2 = px */
0158
0159         /* xmm5 = qx */
0160
0161         asm volatile("movdqa %0,%%xmm4" : : "m" (pbmul[0]));
0162         asm volatile("movdqa %0,%%xmm1" : : "m" (pbmul[16]));
0163         asm volatile("movdqa %xmm2,%xmm3");
0164         asm volatile("psraw  $4,%xmm2");
0165         asm volatile("pand   %xmm7,%xmm3");
0166         asm volatile("pand   %xmm7,%xmm2");
0167         asm volatile("pshufb %xmm3,%xmm4");
0168         asm volatile("pshufb %xmm2,%xmm1");
0169         asm volatile("pxor   %xmm4,%xmm1");
0170
0171         /* xmm1 = pbmul[px] */
0172         asm volatile("pxor   %xmm5,%xmm1");
0173         /* xmm1 = db = DQ */
0174         asm volatile("movdqa %%xmm1,%0" : "=m" (*dq));
0175
0176         asm volatile("pxor   %xmm1,%xmm0");
0177         asm volatile("movdqa %%xmm0,%0" : "=m" (*dp));
0178
0179         bytes -= 16;
0180         p += 16;
0181         q += 16;
0182         dp += 16;
0183         dq += 16;
0184 #endif
0185     }
0186
0187     kernel_fpu_end();
0188 }
0189
0190
0191 static void raid6_datap_recov_ssse3(int disks, size_t bytes, int faila,
0192         void **ptrs)
0193 {
0194     u8 *p, *q, *dq;
0195     const u8 *qmul;     /* Q multiplier table */
0196     static const u8 __aligned(16) x0f[16] = {
0197          0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
0198          0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f};
0199
0200     p = (u8 *)ptrs[disks-2];
0201     q = (u8 *)ptrs[disks-1];
0202
0203     /* Compute syndrome with zero for the missing data page
0204        Use the dead data page as temporary storage for delta q */
0205     dq = (u8 *)ptrs[faila];
0206     ptrs[faila] = (void *)raid6_empty_zero_page;
0207     ptrs[disks-1] = dq;
0208
0209     raid6_call.gen_syndrome(disks, bytes, ptrs);
0210
0211     /* Restore pointer table */
0212     ptrs[faila]   = dq;
0213     ptrs[disks-1] = q;
0214
0215     /* Now, pick the proper data tables */
0216     qmul  = raid6_vgfmul[raid6_gfinv[raid6_gfexp[faila]]];
0217
0218     kernel_fpu_begin();
0219
0220     asm volatile("movdqa %0, %%xmm7" : : "m" (x0f[0]));
0221
0222     while (bytes) {
0223 #ifdef CONFIG_X86_64
0224         asm volatile("movdqa %0, %%xmm3" : : "m" (dq[0]));
0225         asm volatile("movdqa %0, %%xmm4" : : "m" (dq[16]));
0226         asm volatile("pxor %0, %%xmm3" : : "m" (q[0]));
0227         asm volatile("movdqa %0, %%xmm0" : : "m" (qmul[0]));
0228
0229         /* xmm3 = q[0] ^ dq[0] */
0230
0231         asm volatile("pxor %0, %%xmm4" : : "m" (q[16]));
0232         asm volatile("movdqa %0, %%xmm1" : : "m" (qmul[16]));
0233
0234         /* xmm4 = q[16] ^ dq[16] */
0235
0236         asm volatile("movdqa %xmm3, %xmm6");
0237         asm volatile("movdqa %xmm4, %xmm8");
0238
0239         /* xmm4 = xmm8 = q[16] ^ dq[16] */
0240
0241         asm volatile("psraw $4, %xmm3");
0242         asm volatile("pand %xmm7, %xmm6");
0243         asm volatile("pand %xmm7, %xmm3");
0244         asm volatile("pshufb %xmm6, %xmm0");
0245         asm volatile("pshufb %xmm3, %xmm1");
0246         asm volatile("movdqa %0, %%xmm10" : : "m" (qmul[0]));
0247         asm volatile("pxor %xmm0, %xmm1");
0248         asm volatile("movdqa %0, %%xmm11" : : "m" (qmul[16]));
0249
0250         /* xmm1 = qmul[q[0] ^ dq[0]] */
0251
0252         asm volatile("psraw $4, %xmm4");
0253         asm volatile("pand %xmm7, %xmm8");
0254         asm volatile("pand %xmm7, %xmm4");
0255         asm volatile("pshufb %xmm8, %xmm10");
0256         asm volatile("pshufb %xmm4, %xmm11");
0257         asm volatile("movdqa %0, %%xmm2" : : "m" (p[0]));
0258         asm volatile("pxor %xmm10, %xmm11");
0259         asm volatile("movdqa %0, %%xmm12" : : "m" (p[16]));
0260
0261         /* xmm11 = qmul[q[16] ^ dq[16]] */
0262
0263         asm volatile("pxor %xmm1, %xmm2");
0264
0265         /* xmm2 = p[0] ^ qmul[q[0] ^ dq[0]] */
0266
0267         asm volatile("pxor %xmm11, %xmm12");
0268
0269         /* xmm12 = p[16] ^ qmul[q[16] ^ dq[16]] */
0270
0271         asm volatile("movdqa %%xmm1, %0" : "=m" (dq[0]));
0272         asm volatile("movdqa %%xmm11, %0" : "=m" (dq[16]));
0273
0274         asm volatile("movdqa %%xmm2, %0" : "=m" (p[0]));
0275         asm volatile("movdqa %%xmm12, %0" : "=m" (p[16]));
0276
0277         bytes -= 32;
0278         p += 32;
0279         q += 32;
0280         dq += 32;
0281
0282 #else
0283         asm volatile("movdqa %0, %%xmm3" : : "m" (dq[0]));
0284         asm volatile("movdqa %0, %%xmm0" : : "m" (qmul[0]));
0285         asm volatile("pxor %0, %%xmm3" : : "m" (q[0]));
0286         asm volatile("movdqa %0, %%xmm1" : : "m" (qmul[16]));
0287
0288         /* xmm3 = *q ^ *dq */
0289
0290         asm volatile("movdqa %xmm3, %xmm6");
0291         asm volatile("movdqa %0, %%xmm2" : : "m" (p[0]));
0292         asm volatile("psraw $4, %xmm3");
0293         asm volatile("pand %xmm7, %xmm6");
0294         asm volatile("pand %xmm7, %xmm3");
0295         asm volatile("pshufb %xmm6, %xmm0");
0296         asm volatile("pshufb %xmm3, %xmm1");
0297         asm volatile("pxor %xmm0, %xmm1");
0298
0299         /* xmm1 = qmul[*q ^ *dq */
0300
0301         asm volatile("pxor %xmm1, %xmm2");
0302
0303         /* xmm2 = *p ^ qmul[*q ^ *dq] */
0304
0305         asm volatile("movdqa %%xmm1, %0" : "=m" (dq[0]));
0306         asm volatile("movdqa %%xmm2, %0" : "=m" (p[0]));
0307
0308         bytes -= 16;
0309         p += 16;
0310         q += 16;
0311         dq += 16;
0312 #endif
0313     }
0314
0315     kernel_fpu_end();
0316 }
0317
0318 const struct raid6_recov_calls raid6_recov_ssse3 = {
0319     .data2 = raid6_2data_recov_ssse3,
0320     .datap = raid6_datap_recov_ssse3,
0321     .valid = raid6_has_ssse3,
0322 #ifdef CONFIG_X86_64
0323     .name = "ssse3x2",
0324 #else
0325     .name = "ssse3x1",
0326 #endif
0327     .priority = 1,
0328 };