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0001 /* -----------------------------------------------------------------------
0002  *
0003  *   neon.uc - RAID-6 syndrome calculation using ARM NEON instructions
0004  *
0005  *   Copyright (C) 2012 Rob Herring
0006  *   Copyright (C) 2015 Linaro Ltd. <ard.biesheuvel@linaro.org>
0007  *
0008  *   Based on altivec.uc:
0009  *     Copyright 2002-2004 H. Peter Anvin - All Rights Reserved
0010  *
0011  *   This program is free software; you can redistribute it and/or modify
0012  *   it under the terms of the GNU General Public License as published by
0013  *   the Free Software Foundation, Inc., 53 Temple Place Ste 330,
0014  *   Boston MA 02111-1307, USA; either version 2 of the License, or
0015  *   (at your option) any later version; incorporated herein by reference.
0016  *
0017  * ----------------------------------------------------------------------- */
0018 
0019 /*
0020  * neon$#.c
0021  *
0022  * $#-way unrolled NEON intrinsics math RAID-6 instruction set
0023  *
0024  * This file is postprocessed using unroll.awk
0025  */
0026 
0027 #include <arm_neon.h>
0028 
0029 typedef uint8x16_t unative_t;
0030 
0031 #define NSIZE   sizeof(unative_t)
0032 
0033 /*
0034  * The SHLBYTE() operation shifts each byte left by 1, *not*
0035  * rolling over into the next byte
0036  */
0037 static inline unative_t SHLBYTE(unative_t v)
0038 {
0039         return vshlq_n_u8(v, 1);
0040 }
0041 
0042 /*
0043  * The MASK() operation returns 0xFF in any byte for which the high
0044  * bit is 1, 0x00 for any byte for which the high bit is 0.
0045  */
0046 static inline unative_t MASK(unative_t v)
0047 {
0048         return (unative_t)vshrq_n_s8((int8x16_t)v, 7);
0049 }
0050 
0051 static inline unative_t PMUL(unative_t v, unative_t u)
0052 {
0053         return (unative_t)vmulq_p8((poly8x16_t)v, (poly8x16_t)u);
0054 }
0055 
0056 void raid6_neon$#_gen_syndrome_real(int disks, unsigned long bytes, void **ptrs)
0057 {
0058         uint8_t **dptr = (uint8_t **)ptrs;
0059         uint8_t *p, *q;
0060         int d, z, z0;
0061 
0062         register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
0063         const unative_t x1d = vdupq_n_u8(0x1d);
0064 
0065         z0 = disks - 3;         /* Highest data disk */
0066         p = dptr[z0+1];         /* XOR parity */
0067         q = dptr[z0+2];         /* RS syndrome */
0068 
0069         for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
0070                 wq$$ = wp$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]);
0071                 for ( z = z0-1 ; z >= 0 ; z-- ) {
0072                         wd$$ = vld1q_u8(&dptr[z][d+$$*NSIZE]);
0073                         wp$$ = veorq_u8(wp$$, wd$$);
0074                         w2$$ = MASK(wq$$);
0075                         w1$$ = SHLBYTE(wq$$);
0076 
0077                         w2$$ = vandq_u8(w2$$, x1d);
0078                         w1$$ = veorq_u8(w1$$, w2$$);
0079                         wq$$ = veorq_u8(w1$$, wd$$);
0080                 }
0081                 vst1q_u8(&p[d+NSIZE*$$], wp$$);
0082                 vst1q_u8(&q[d+NSIZE*$$], wq$$);
0083         }
0084 }
0085 
0086 void raid6_neon$#_xor_syndrome_real(int disks, int start, int stop,
0087                                     unsigned long bytes, void **ptrs)
0088 {
0089         uint8_t **dptr = (uint8_t **)ptrs;
0090         uint8_t *p, *q;
0091         int d, z, z0;
0092 
0093         register unative_t wd$$, wq$$, wp$$, w1$$, w2$$;
0094         const unative_t x1d = vdupq_n_u8(0x1d);
0095 
0096         z0 = stop;              /* P/Q right side optimization */
0097         p = dptr[disks-2];      /* XOR parity */
0098         q = dptr[disks-1];      /* RS syndrome */
0099 
0100         for ( d = 0 ; d < bytes ; d += NSIZE*$# ) {
0101                 wq$$ = vld1q_u8(&dptr[z0][d+$$*NSIZE]);
0102                 wp$$ = veorq_u8(vld1q_u8(&p[d+$$*NSIZE]), wq$$);
0103 
0104                 /* P/Q data pages */
0105                 for ( z = z0-1 ; z >= start ; z-- ) {
0106                         wd$$ = vld1q_u8(&dptr[z][d+$$*NSIZE]);
0107                         wp$$ = veorq_u8(wp$$, wd$$);
0108                         w2$$ = MASK(wq$$);
0109                         w1$$ = SHLBYTE(wq$$);
0110 
0111                         w2$$ = vandq_u8(w2$$, x1d);
0112                         w1$$ = veorq_u8(w1$$, w2$$);
0113                         wq$$ = veorq_u8(w1$$, wd$$);
0114                 }
0115                 /* P/Q left side optimization */
0116                 for ( z = start-1 ; z >= 3 ; z -= 4 ) {
0117                         w2$$ = vshrq_n_u8(wq$$, 4);
0118                         w1$$ = vshlq_n_u8(wq$$, 4);
0119 
0120                         w2$$ = PMUL(w2$$, x1d);
0121                         wq$$ = veorq_u8(w1$$, w2$$);
0122                 }
0123 
0124                 switch (z) {
0125                 case 2:
0126                         w2$$ = vshrq_n_u8(wq$$, 5);
0127                         w1$$ = vshlq_n_u8(wq$$, 3);
0128 
0129                         w2$$ = PMUL(w2$$, x1d);
0130                         wq$$ = veorq_u8(w1$$, w2$$);
0131                         break;
0132                 case 1:
0133                         w2$$ = vshrq_n_u8(wq$$, 6);
0134                         w1$$ = vshlq_n_u8(wq$$, 2);
0135 
0136                         w2$$ = PMUL(w2$$, x1d);
0137                         wq$$ = veorq_u8(w1$$, w2$$);
0138                         break;
0139                 case 0:
0140                         w2$$ = MASK(wq$$);
0141                         w1$$ = SHLBYTE(wq$$);
0142 
0143                         w2$$ = vandq_u8(w2$$, x1d);
0144                         wq$$ = veorq_u8(w1$$, w2$$);
0145                 }
0146                 w1$$ = vld1q_u8(&q[d+NSIZE*$$]);
0147                 wq$$ = veorq_u8(wq$$, w1$$);
0148 
0149                 vst1q_u8(&p[d+NSIZE*$$], wp$$);
0150                 vst1q_u8(&q[d+NSIZE*$$], wq$$);
0151         }
0152 }