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0001 /* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
0002  * Note: I added some stuff for use with gnupg
0003  *
0004  * Copyright (C) 1991, 1992, 1993, 1994, 1996, 1998,
0005  *  2000, 2001, 2002, 2003 Free Software Foundation, Inc.
0006  *
0007  * This file is free software; you can redistribute it and/or modify
0008  * it under the terms of the GNU Library General Public License as published by
0009  * the Free Software Foundation; either version 2 of the License, or (at your
0010  * option) any later version.
0011  *
0012  * This file is distributed in the hope that it will be useful, but
0013  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
0014  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU Library General Public
0015  * License for more details.
0016  *
0017  * You should have received a copy of the GNU Library General Public License
0018  * along with this file; see the file COPYING.LIB.  If not, write to
0019  * the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
0020  * MA 02111-1307, USA. */
0021 
0022 #include <linux/count_zeros.h>
0023 
0024 /* You have to define the following before including this file:
0025  *
0026  * UWtype -- An unsigned type, default type for operations (typically a "word")
0027  * UHWtype -- An unsigned type, at least half the size of UWtype.
0028  * UDWtype -- An unsigned type, at least twice as large a UWtype
0029  * W_TYPE_SIZE -- size in bits of UWtype
0030  *
0031  * SItype, USItype -- Signed and unsigned 32 bit types.
0032  * DItype, UDItype -- Signed and unsigned 64 bit types.
0033  *
0034  * On a 32 bit machine UWtype should typically be USItype;
0035  * on a 64 bit machine, UWtype should typically be UDItype.
0036 */
0037 
0038 #define __BITS4 (W_TYPE_SIZE / 4)
0039 #define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
0040 #define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
0041 #define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
0042 
0043 /* This is used to make sure no undesirable sharing between different libraries
0044     that use this file takes place.  */
0045 #ifndef __MPN
0046 #define __MPN(x) __##x
0047 #endif
0048 
0049 /* Define auxiliary asm macros.
0050  *
0051  * 1) umul_ppmm(high_prod, low_prod, multiplier, multiplicand) multiplies two
0052  * UWtype integers MULTIPLIER and MULTIPLICAND, and generates a two UWtype
0053  * word product in HIGH_PROD and LOW_PROD.
0054  *
0055  * 2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
0056  * UDWtype product.  This is just a variant of umul_ppmm.
0057 
0058  * 3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
0059  * denominator) divides a UDWtype, composed by the UWtype integers
0060  * HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
0061  * in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
0062  * than DENOMINATOR for correct operation.  If, in addition, the most
0063  * significant bit of DENOMINATOR must be 1, then the pre-processor symbol
0064  * UDIV_NEEDS_NORMALIZATION is defined to 1.
0065  * 4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
0066  * denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
0067  * is rounded towards 0.
0068  *
0069  * 5) count_leading_zeros(count, x) counts the number of zero-bits from the
0070  * msb to the first non-zero bit in the UWtype X.  This is the number of
0071  * steps X needs to be shifted left to set the msb.  Undefined for X == 0,
0072  * unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
0073  *
0074  * 6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
0075  * from the least significant end.
0076  *
0077  * 7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
0078  * high_addend_2, low_addend_2) adds two UWtype integers, composed by
0079  * HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
0080  * respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
0081  * (i.e. carry out) is not stored anywhere, and is lost.
0082  *
0083  * 8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
0084  * high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
0085  * composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
0086  * LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
0087  * and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
0088  * and is lost.
0089  *
0090  * If any of these macros are left undefined for a particular CPU,
0091  * C macros are used.  */
0092 
0093 /* The CPUs come in alphabetical order below.
0094  *
0095  * Please add support for more CPUs here, or improve the current support
0096  * for the CPUs below!  */
0097 
0098 #if defined(__GNUC__) && !defined(NO_ASM)
0099 
0100 /* We sometimes need to clobber "cc" with gcc2, but that would not be
0101     understood by gcc1. Use cpp to avoid major code duplication.  */
0102 #if __GNUC__ < 2
0103 #define __CLOBBER_CC
0104 #define __AND_CLOBBER_CC
0105 #else /* __GNUC__ >= 2 */
0106 #define __CLOBBER_CC : "cc"
0107 #define __AND_CLOBBER_CC , "cc"
0108 #endif /* __GNUC__ < 2 */
0109 
0110 /***************************************
0111     **************  A29K  *****************
0112     ***************************************/
0113 #if (defined(__a29k__) || defined(_AM29K)) && W_TYPE_SIZE == 32
0114 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0115     __asm__ ("add %1,%4,%5\n" \
0116         "addc %0,%2,%3" \
0117     : "=r" ((USItype)(sh)), \
0118         "=&r" ((USItype)(sl)) \
0119     : "%r" ((USItype)(ah)), \
0120         "rI" ((USItype)(bh)), \
0121         "%r" ((USItype)(al)), \
0122         "rI" ((USItype)(bl)))
0123 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0124     __asm__ ("sub %1,%4,%5\n" \
0125         "subc %0,%2,%3" \
0126     : "=r" ((USItype)(sh)), \
0127         "=&r" ((USItype)(sl)) \
0128     : "r" ((USItype)(ah)), \
0129         "rI" ((USItype)(bh)), \
0130         "r" ((USItype)(al)), \
0131         "rI" ((USItype)(bl)))
0132 #define umul_ppmm(xh, xl, m0, m1) \
0133 do { \
0134         USItype __m0 = (m0), __m1 = (m1); \
0135         __asm__ ("multiplu %0,%1,%2" \
0136         : "=r" ((USItype)(xl)) \
0137         : "r" (__m0), \
0138             "r" (__m1)); \
0139         __asm__ ("multmu %0,%1,%2" \
0140         : "=r" ((USItype)(xh)) \
0141         : "r" (__m0), \
0142             "r" (__m1)); \
0143 } while (0)
0144 #define udiv_qrnnd(q, r, n1, n0, d) \
0145     __asm__ ("dividu %0,%3,%4" \
0146     : "=r" ((USItype)(q)), \
0147         "=q" ((USItype)(r)) \
0148     : "1" ((USItype)(n1)), \
0149         "r" ((USItype)(n0)), \
0150         "r" ((USItype)(d)))
0151 #endif /* __a29k__ */
0152 
0153 #if defined(__alpha) && W_TYPE_SIZE == 64
0154 #define umul_ppmm(ph, pl, m0, m1)           \
0155 do {                            \
0156     UDItype __m0 = (m0), __m1 = (m1);       \
0157     (ph) = __builtin_alpha_umulh(__m0, __m1);   \
0158     (pl) = __m0 * __m1;                             \
0159 } while (0)
0160 #define UMUL_TIME 46
0161 #ifndef LONGLONG_STANDALONE
0162 #define udiv_qrnnd(q, r, n1, n0, d) \
0163 do { UDItype __r; \
0164     (q) = __udiv_qrnnd(&__r, (n1), (n0), (d)); \
0165     (r) = __r; \
0166 } while (0)
0167 extern UDItype __udiv_qrnnd(UDItype *, UDItype, UDItype, UDItype);
0168 #define UDIV_TIME 220
0169 #endif /* LONGLONG_STANDALONE */
0170 #endif /* __alpha */
0171 
0172 /***************************************
0173     **************  ARM  ******************
0174     ***************************************/
0175 #if defined(__arm__) && W_TYPE_SIZE == 32
0176 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0177     __asm__ ("adds %1, %4, %5\n" \
0178         "adc  %0, %2, %3" \
0179     : "=r" (sh), \
0180         "=&r" (sl) \
0181     : "%r" ((USItype)(ah)), \
0182         "rI" ((USItype)(bh)), \
0183         "%r" ((USItype)(al)), \
0184         "rI" ((USItype)(bl)))
0185 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0186     __asm__ ("subs %1, %4, %5\n" \
0187         "sbc  %0, %2, %3" \
0188     : "=r" (sh), \
0189         "=&r" (sl) \
0190     : "r" ((USItype)(ah)), \
0191         "rI" ((USItype)(bh)), \
0192         "r" ((USItype)(al)), \
0193         "rI" ((USItype)(bl)))
0194 #if defined __ARM_ARCH_2__ || defined __ARM_ARCH_3__
0195 #define umul_ppmm(xh, xl, a, b) \
0196     __asm__ ("@ Inlined umul_ppmm\n" \
0197         "mov    %|r0, %2, lsr #16       @ AAAA\n" \
0198         "mov    %|r2, %3, lsr #16       @ BBBB\n" \
0199         "bic    %|r1, %2, %|r0, lsl #16     @ aaaa\n" \
0200         "bic    %0, %3, %|r2, lsl #16       @ bbbb\n" \
0201         "mul    %1, %|r1, %|r2          @ aaaa * BBBB\n" \
0202         "mul    %|r2, %|r0, %|r2        @ AAAA * BBBB\n" \
0203         "mul    %|r1, %0, %|r1          @ aaaa * bbbb\n" \
0204         "mul    %0, %|r0, %0            @ AAAA * bbbb\n" \
0205         "adds   %|r0, %1, %0            @ central sum\n" \
0206         "addcs  %|r2, %|r2, #65536\n" \
0207         "adds   %1, %|r1, %|r0, lsl #16\n" \
0208         "adc    %0, %|r2, %|r0, lsr #16" \
0209     : "=&r" (xh), \
0210         "=r" (xl) \
0211     : "r" ((USItype)(a)), \
0212         "r" ((USItype)(b)) \
0213     : "r0", "r1", "r2")
0214 #else
0215 #define umul_ppmm(xh, xl, a, b) \
0216     __asm__ ("@ Inlined umul_ppmm\n" \
0217         "umull %1, %0, %2, %3" \
0218     : "=&r" (xh), \
0219         "=&r" (xl) \
0220     : "r" ((USItype)(a)), \
0221         "r" ((USItype)(b)) \
0222     : "r0", "r1")
0223 #endif
0224 #define UMUL_TIME 20
0225 #define UDIV_TIME 100
0226 #endif /* __arm__ */
0227 
0228 /***************************************
0229     **************  CLIPPER  **************
0230     ***************************************/
0231 #if defined(__clipper__) && W_TYPE_SIZE == 32
0232 #define umul_ppmm(w1, w0, u, v) \
0233     ({union {UDItype __ll; \
0234         struct {USItype __l, __h; } __i; \
0235     } __xx; \
0236     __asm__ ("mulwux %2,%0" \
0237     : "=r" (__xx.__ll) \
0238     : "%0" ((USItype)(u)), \
0239         "r" ((USItype)(v))); \
0240     (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
0241 #define smul_ppmm(w1, w0, u, v) \
0242     ({union {DItype __ll; \
0243         struct {SItype __l, __h; } __i; \
0244     } __xx; \
0245     __asm__ ("mulwx %2,%0" \
0246     : "=r" (__xx.__ll) \
0247     : "%0" ((SItype)(u)), \
0248         "r" ((SItype)(v))); \
0249     (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
0250 #define __umulsidi3(u, v) \
0251     ({UDItype __w; \
0252     __asm__ ("mulwux %2,%0" \
0253     : "=r" (__w) \
0254     : "%0" ((USItype)(u)), \
0255         "r" ((USItype)(v))); \
0256     __w; })
0257 #endif /* __clipper__ */
0258 
0259 /***************************************
0260     **************  GMICRO  ***************
0261     ***************************************/
0262 #if defined(__gmicro__) && W_TYPE_SIZE == 32
0263 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0264     __asm__ ("add.w %5,%1\n" \
0265         "addx %3,%0" \
0266     : "=g" ((USItype)(sh)), \
0267         "=&g" ((USItype)(sl)) \
0268     : "%0" ((USItype)(ah)), \
0269         "g" ((USItype)(bh)), \
0270         "%1" ((USItype)(al)), \
0271         "g" ((USItype)(bl)))
0272 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0273     __asm__ ("sub.w %5,%1\n" \
0274         "subx %3,%0" \
0275     : "=g" ((USItype)(sh)), \
0276         "=&g" ((USItype)(sl)) \
0277     : "0" ((USItype)(ah)), \
0278         "g" ((USItype)(bh)), \
0279         "1" ((USItype)(al)), \
0280         "g" ((USItype)(bl)))
0281 #define umul_ppmm(ph, pl, m0, m1) \
0282     __asm__ ("mulx %3,%0,%1" \
0283     : "=g" ((USItype)(ph)), \
0284         "=r" ((USItype)(pl)) \
0285     : "%0" ((USItype)(m0)), \
0286         "g" ((USItype)(m1)))
0287 #define udiv_qrnnd(q, r, nh, nl, d) \
0288     __asm__ ("divx %4,%0,%1" \
0289     : "=g" ((USItype)(q)), \
0290         "=r" ((USItype)(r)) \
0291     : "1" ((USItype)(nh)), \
0292         "0" ((USItype)(nl)), \
0293         "g" ((USItype)(d)))
0294 #endif
0295 
0296 /***************************************
0297     **************  HPPA  *****************
0298     ***************************************/
0299 #if defined(__hppa) && W_TYPE_SIZE == 32
0300 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0301     __asm__ ("add %4,%5,%1\n" \
0302            "addc %2,%3,%0" \
0303     : "=r" ((USItype)(sh)), \
0304          "=&r" ((USItype)(sl)) \
0305     : "%rM" ((USItype)(ah)), \
0306          "rM" ((USItype)(bh)), \
0307          "%rM" ((USItype)(al)), \
0308          "rM" ((USItype)(bl)))
0309 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0310     __asm__ ("sub %4,%5,%1\n" \
0311        "subb %2,%3,%0" \
0312     : "=r" ((USItype)(sh)), \
0313          "=&r" ((USItype)(sl)) \
0314     : "rM" ((USItype)(ah)), \
0315          "rM" ((USItype)(bh)), \
0316          "rM" ((USItype)(al)), \
0317          "rM" ((USItype)(bl)))
0318 #if 0 && defined(_PA_RISC1_1)
0319 /* xmpyu uses floating point register which is not allowed in Linux kernel. */
0320 #define umul_ppmm(wh, wl, u, v) \
0321 do { \
0322     union {UDItype __ll; \
0323     struct {USItype __h, __l; } __i; \
0324     } __xx; \
0325     __asm__ ("xmpyu %1,%2,%0" \
0326     : "=*f" (__xx.__ll) \
0327     : "*f" ((USItype)(u)), \
0328            "*f" ((USItype)(v))); \
0329     (wh) = __xx.__i.__h; \
0330     (wl) = __xx.__i.__l; \
0331 } while (0)
0332 #define UMUL_TIME 8
0333 #define UDIV_TIME 60
0334 #else
0335 #define UMUL_TIME 40
0336 #define UDIV_TIME 80
0337 #endif
0338 #if 0 /* #ifndef LONGLONG_STANDALONE */
0339 #define udiv_qrnnd(q, r, n1, n0, d) \
0340 do { USItype __r; \
0341     (q) = __udiv_qrnnd(&__r, (n1), (n0), (d)); \
0342     (r) = __r; \
0343 } while (0)
0344 extern USItype __udiv_qrnnd();
0345 #endif /* LONGLONG_STANDALONE */
0346 #endif /* hppa */
0347 
0348 /***************************************
0349     **************  I370  *****************
0350     ***************************************/
0351 #if (defined(__i370__) || defined(__mvs__)) && W_TYPE_SIZE == 32
0352 #define umul_ppmm(xh, xl, m0, m1) \
0353 do { \
0354     union {UDItype __ll; \
0355        struct {USItype __h, __l; } __i; \
0356     } __xx; \
0357     USItype __m0 = (m0), __m1 = (m1); \
0358     __asm__ ("mr %0,%3" \
0359     : "=r" (__xx.__i.__h), \
0360            "=r" (__xx.__i.__l) \
0361     : "%1" (__m0), \
0362            "r" (__m1)); \
0363     (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
0364     (xh) += ((((SItype) __m0 >> 31) & __m1) \
0365          + (((SItype) __m1 >> 31) & __m0)); \
0366 } while (0)
0367 #define smul_ppmm(xh, xl, m0, m1) \
0368 do { \
0369     union {DItype __ll; \
0370        struct {USItype __h, __l; } __i; \
0371     } __xx; \
0372     __asm__ ("mr %0,%3" \
0373     : "=r" (__xx.__i.__h), \
0374            "=r" (__xx.__i.__l) \
0375     : "%1" (m0), \
0376            "r" (m1)); \
0377     (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
0378 } while (0)
0379 #define sdiv_qrnnd(q, r, n1, n0, d) \
0380 do { \
0381     union {DItype __ll; \
0382        struct {USItype __h, __l; } __i; \
0383     } __xx; \
0384     __xx.__i.__h = n1; __xx.__i.__l = n0; \
0385     __asm__ ("dr %0,%2" \
0386     : "=r" (__xx.__ll) \
0387     : "0" (__xx.__ll), "r" (d)); \
0388     (q) = __xx.__i.__l; (r) = __xx.__i.__h; \
0389 } while (0)
0390 #endif
0391 
0392 /***************************************
0393     **************  I386  *****************
0394     ***************************************/
0395 #undef __i386__
0396 #if (defined(__i386__) || defined(__i486__)) && W_TYPE_SIZE == 32
0397 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0398     __asm__ ("addl %5,%1\n" \
0399        "adcl %3,%0" \
0400     : "=r" (sh), \
0401          "=&r" (sl) \
0402     : "%0" ((USItype)(ah)), \
0403          "g" ((USItype)(bh)), \
0404          "%1" ((USItype)(al)), \
0405          "g" ((USItype)(bl)))
0406 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0407     __asm__ ("subl %5,%1\n" \
0408        "sbbl %3,%0" \
0409     : "=r" (sh), \
0410          "=&r" (sl) \
0411     : "0" ((USItype)(ah)), \
0412          "g" ((USItype)(bh)), \
0413          "1" ((USItype)(al)), \
0414          "g" ((USItype)(bl)))
0415 #define umul_ppmm(w1, w0, u, v) \
0416     __asm__ ("mull %3" \
0417     : "=a" (w0), \
0418          "=d" (w1) \
0419     : "%0" ((USItype)(u)), \
0420          "rm" ((USItype)(v)))
0421 #define udiv_qrnnd(q, r, n1, n0, d) \
0422     __asm__ ("divl %4" \
0423     : "=a" (q), \
0424          "=d" (r) \
0425     : "0" ((USItype)(n0)), \
0426          "1" ((USItype)(n1)), \
0427          "rm" ((USItype)(d)))
0428 #ifndef UMUL_TIME
0429 #define UMUL_TIME 40
0430 #endif
0431 #ifndef UDIV_TIME
0432 #define UDIV_TIME 40
0433 #endif
0434 #endif /* 80x86 */
0435 
0436 /***************************************
0437     **************  I860  *****************
0438     ***************************************/
0439 #if defined(__i860__) && W_TYPE_SIZE == 32
0440 #define rshift_rhlc(r, h, l, c) \
0441     __asm__ ("shr %3,r0,r0\n" \
0442     "shrd %1,%2,%0" \
0443        "=r" (r) : "r" (h), "r" (l), "rn" (c))
0444 #endif /* i860 */
0445 
0446 /***************************************
0447     **************  I960  *****************
0448     ***************************************/
0449 #if defined(__i960__) && W_TYPE_SIZE == 32
0450 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0451     __asm__ ("cmpo 1,0\n" \
0452     "addc %5,%4,%1\n" \
0453     "addc %3,%2,%0" \
0454     : "=r" ((USItype)(sh)), \
0455          "=&r" ((USItype)(sl)) \
0456     : "%dI" ((USItype)(ah)), \
0457          "dI" ((USItype)(bh)), \
0458          "%dI" ((USItype)(al)), \
0459          "dI" ((USItype)(bl)))
0460 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0461     __asm__ ("cmpo 0,0\n" \
0462     "subc %5,%4,%1\n" \
0463     "subc %3,%2,%0" \
0464     : "=r" ((USItype)(sh)), \
0465          "=&r" ((USItype)(sl)) \
0466     : "dI" ((USItype)(ah)), \
0467          "dI" ((USItype)(bh)), \
0468          "dI" ((USItype)(al)), \
0469          "dI" ((USItype)(bl)))
0470 #define umul_ppmm(w1, w0, u, v) \
0471     ({union {UDItype __ll; \
0472        struct {USItype __l, __h; } __i; \
0473     } __xx; \
0474     __asm__ ("emul        %2,%1,%0" \
0475     : "=d" (__xx.__ll) \
0476     : "%dI" ((USItype)(u)), \
0477          "dI" ((USItype)(v))); \
0478     (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
0479 #define __umulsidi3(u, v) \
0480     ({UDItype __w; \
0481     __asm__ ("emul      %2,%1,%0" \
0482     : "=d" (__w) \
0483     : "%dI" ((USItype)(u)), \
0484            "dI" ((USItype)(v))); \
0485     __w; })
0486 #define udiv_qrnnd(q, r, nh, nl, d) \
0487 do { \
0488     union {UDItype __ll; \
0489        struct {USItype __l, __h; } __i; \
0490     } __nn; \
0491     __nn.__i.__h = (nh); __nn.__i.__l = (nl); \
0492     __asm__ ("ediv %d,%n,%0" \
0493     : "=d" (__rq.__ll) \
0494     : "dI" (__nn.__ll), \
0495          "dI" ((USItype)(d))); \
0496     (r) = __rq.__i.__l; (q) = __rq.__i.__h; \
0497 } while (0)
0498 #if defined(__i960mx)       /* what is the proper symbol to test??? */
0499 #define rshift_rhlc(r, h, l, c) \
0500 do { \
0501     union {UDItype __ll; \
0502        struct {USItype __l, __h; } __i; \
0503     } __nn; \
0504     __nn.__i.__h = (h); __nn.__i.__l = (l); \
0505     __asm__ ("shre %2,%1,%0" \
0506     : "=d" (r) : "dI" (__nn.__ll), "dI" (c)); \
0507 }
0508 #endif /* i960mx */
0509 #endif /* i960 */
0510 
0511 /***************************************
0512     **************  68000   ****************
0513     ***************************************/
0514 #if (defined(__mc68000__) || defined(__mc68020__) || defined(__NeXT__) || defined(mc68020)) && W_TYPE_SIZE == 32
0515 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0516     __asm__ ("add%.l %5,%1\n" \
0517        "addx%.l %3,%0" \
0518     : "=d" ((USItype)(sh)), \
0519          "=&d" ((USItype)(sl)) \
0520     : "%0" ((USItype)(ah)), \
0521          "d" ((USItype)(bh)), \
0522          "%1" ((USItype)(al)), \
0523          "g" ((USItype)(bl)))
0524 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0525     __asm__ ("sub%.l %5,%1\n" \
0526        "subx%.l %3,%0" \
0527     : "=d" ((USItype)(sh)), \
0528          "=&d" ((USItype)(sl)) \
0529     : "0" ((USItype)(ah)), \
0530          "d" ((USItype)(bh)), \
0531          "1" ((USItype)(al)), \
0532          "g" ((USItype)(bl)))
0533 #if (defined(__mc68020__) || defined(__NeXT__) || defined(mc68020))
0534 #define umul_ppmm(w1, w0, u, v) \
0535     __asm__ ("mulu%.l %3,%1:%0" \
0536     : "=d" ((USItype)(w0)), \
0537          "=d" ((USItype)(w1)) \
0538     : "%0" ((USItype)(u)), \
0539          "dmi" ((USItype)(v)))
0540 #define UMUL_TIME 45
0541 #define udiv_qrnnd(q, r, n1, n0, d) \
0542     __asm__ ("divu%.l %4,%1:%0" \
0543     : "=d" ((USItype)(q)), \
0544          "=d" ((USItype)(r)) \
0545     : "0" ((USItype)(n0)), \
0546          "1" ((USItype)(n1)), \
0547          "dmi" ((USItype)(d)))
0548 #define UDIV_TIME 90
0549 #define sdiv_qrnnd(q, r, n1, n0, d) \
0550     __asm__ ("divs%.l %4,%1:%0" \
0551     : "=d" ((USItype)(q)), \
0552          "=d" ((USItype)(r)) \
0553     : "0" ((USItype)(n0)), \
0554          "1" ((USItype)(n1)), \
0555          "dmi" ((USItype)(d)))
0556 #else /* not mc68020 */
0557 #define umul_ppmm(xh, xl, a, b) \
0558 do { USItype __umul_tmp1, __umul_tmp2; \
0559     __asm__ ("| Inlined umul_ppmm\n" \
0560     "move%.l %5,%3\n" \
0561     "move%.l %2,%0\n" \
0562     "move%.w %3,%1\n" \
0563     "swap   %3\n" \
0564     "swap   %0\n" \
0565     "mulu   %2,%1\n" \
0566     "mulu   %3,%0\n" \
0567     "mulu   %2,%3\n" \
0568     "swap   %2\n" \
0569     "mulu   %5,%2\n" \
0570     "add%.l %3,%2\n" \
0571     "jcc    1f\n" \
0572     "add%.l %#0x10000,%0\n" \
0573     "1: move%.l %2,%3\n" \
0574     "clr%.w %2\n" \
0575     "swap   %2\n" \
0576     "swap   %3\n" \
0577     "clr%.w %3\n" \
0578     "add%.l %3,%1\n" \
0579     "addx%.l %2,%0\n" \
0580     "| End inlined umul_ppmm" \
0581     : "=&d" ((USItype)(xh)), "=&d" ((USItype)(xl)), \
0582         "=d" (__umul_tmp1), "=&d" (__umul_tmp2) \
0583     : "%2" ((USItype)(a)), "d" ((USItype)(b))); \
0584 } while (0)
0585 #define UMUL_TIME 100
0586 #define UDIV_TIME 400
0587 #endif /* not mc68020 */
0588 #endif /* mc68000 */
0589 
0590 /***************************************
0591     **************  88000   ****************
0592     ***************************************/
0593 #if defined(__m88000__) && W_TYPE_SIZE == 32
0594 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0595     __asm__ ("addu.co %1,%r4,%r5\n" \
0596        "addu.ci %0,%r2,%r3" \
0597     : "=r" ((USItype)(sh)), \
0598          "=&r" ((USItype)(sl)) \
0599     : "%rJ" ((USItype)(ah)), \
0600          "rJ" ((USItype)(bh)), \
0601          "%rJ" ((USItype)(al)), \
0602          "rJ" ((USItype)(bl)))
0603 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0604     __asm__ ("subu.co %1,%r4,%r5\n" \
0605        "subu.ci %0,%r2,%r3" \
0606     : "=r" ((USItype)(sh)), \
0607          "=&r" ((USItype)(sl)) \
0608     : "rJ" ((USItype)(ah)), \
0609          "rJ" ((USItype)(bh)), \
0610          "rJ" ((USItype)(al)), \
0611          "rJ" ((USItype)(bl)))
0612 #if defined(__m88110__)
0613 #define umul_ppmm(wh, wl, u, v) \
0614 do { \
0615     union {UDItype __ll; \
0616        struct {USItype __h, __l; } __i; \
0617     } __x; \
0618     __asm__ ("mulu.d %0,%1,%2" : "=r" (__x.__ll) : "r" (u), "r" (v)); \
0619     (wh) = __x.__i.__h; \
0620     (wl) = __x.__i.__l; \
0621 } while (0)
0622 #define udiv_qrnnd(q, r, n1, n0, d) \
0623     ({union {UDItype __ll; \
0624        struct {USItype __h, __l; } __i; \
0625     } __x, __q; \
0626     __x.__i.__h = (n1); __x.__i.__l = (n0); \
0627     __asm__ ("divu.d %0,%1,%2" \
0628     : "=r" (__q.__ll) : "r" (__x.__ll), "r" (d)); \
0629     (r) = (n0) - __q.__l * (d); (q) = __q.__l; })
0630 #define UMUL_TIME 5
0631 #define UDIV_TIME 25
0632 #else
0633 #define UMUL_TIME 17
0634 #define UDIV_TIME 150
0635 #endif /* __m88110__ */
0636 #endif /* __m88000__ */
0637 
0638 /***************************************
0639     **************  MIPS  *****************
0640     ***************************************/
0641 #if defined(__mips__) && W_TYPE_SIZE == 32
0642 #define umul_ppmm(w1, w0, u, v)         \
0643 do {                        \
0644     UDItype __ll = (UDItype)(u) * (v);  \
0645     w1 = __ll >> 32;            \
0646     w0 = __ll;              \
0647 } while (0)
0648 #define UMUL_TIME 10
0649 #define UDIV_TIME 100
0650 #endif /* __mips__ */
0651 
0652 /***************************************
0653     **************  MIPS/64  **************
0654     ***************************************/
0655 #if (defined(__mips) && __mips >= 3) && W_TYPE_SIZE == 64
0656 #if defined(__mips_isa_rev) && __mips_isa_rev >= 6 && defined(CONFIG_CC_IS_GCC)
0657 /*
0658  * GCC ends up emitting a __multi3 intrinsic call for MIPS64r6 with the plain C
0659  * code below, so we special case MIPS64r6 until the compiler can do better.
0660  */
0661 #define umul_ppmm(w1, w0, u, v)                     \
0662 do {                                    \
0663     __asm__ ("dmulu %0,%1,%2"                   \
0664          : "=d" ((UDItype)(w0))                 \
0665          : "d" ((UDItype)(u)),                  \
0666            "d" ((UDItype)(v)));                 \
0667     __asm__ ("dmuhu %0,%1,%2"                   \
0668          : "=d" ((UDItype)(w1))                 \
0669          : "d" ((UDItype)(u)),                  \
0670            "d" ((UDItype)(v)));                 \
0671 } while (0)
0672 #else
0673 #define umul_ppmm(w1, w0, u, v) \
0674 do {                                    \
0675     typedef unsigned int __ll_UTItype __attribute__((mode(TI)));    \
0676     __ll_UTItype __ll = (__ll_UTItype)(u) * (v);            \
0677     w1 = __ll >> 64;                        \
0678     w0 = __ll;                          \
0679 } while (0)
0680 #endif
0681 #define UMUL_TIME 20
0682 #define UDIV_TIME 140
0683 #endif /* __mips__ */
0684 
0685 /***************************************
0686     **************  32000   ****************
0687     ***************************************/
0688 #if defined(__ns32000__) && W_TYPE_SIZE == 32
0689 #define umul_ppmm(w1, w0, u, v) \
0690     ({union {UDItype __ll; \
0691        struct {USItype __l, __h; } __i; \
0692     } __xx; \
0693     __asm__ ("meid %2,%0" \
0694     : "=g" (__xx.__ll) \
0695     : "%0" ((USItype)(u)), \
0696          "g" ((USItype)(v))); \
0697     (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
0698 #define __umulsidi3(u, v) \
0699     ({UDItype __w; \
0700     __asm__ ("meid %2,%0" \
0701     : "=g" (__w) \
0702     : "%0" ((USItype)(u)), \
0703            "g" ((USItype)(v))); \
0704     __w; })
0705 #define udiv_qrnnd(q, r, n1, n0, d) \
0706     ({union {UDItype __ll; \
0707        struct {USItype __l, __h; } __i; \
0708     } __xx; \
0709     __xx.__i.__h = (n1); __xx.__i.__l = (n0); \
0710     __asm__ ("deid %2,%0" \
0711     : "=g" (__xx.__ll) \
0712     : "0" (__xx.__ll), \
0713          "g" ((USItype)(d))); \
0714     (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
0715 #endif /* __ns32000__ */
0716 
0717 /***************************************
0718     **************  PPC  ******************
0719     ***************************************/
0720 #if (defined(_ARCH_PPC) || defined(_IBMR2)) && W_TYPE_SIZE == 32
0721 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0722 do { \
0723     if (__builtin_constant_p(bh) && (bh) == 0) \
0724         __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
0725         : "=r" (sh), \
0726         "=&r" (sl) \
0727         : "%r" ((USItype)(ah)), \
0728         "%r" ((USItype)(al)), \
0729         "rI" ((USItype)(bl))); \
0730     else if (__builtin_constant_p(bh) && (bh) == ~(USItype) 0) \
0731         __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
0732         : "=r" (sh), \
0733         "=&r" (sl) \
0734         : "%r" ((USItype)(ah)), \
0735         "%r" ((USItype)(al)), \
0736         "rI" ((USItype)(bl))); \
0737     else \
0738         __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
0739         : "=r" (sh), \
0740         "=&r" (sl) \
0741         : "%r" ((USItype)(ah)), \
0742         "r" ((USItype)(bh)), \
0743         "%r" ((USItype)(al)), \
0744         "rI" ((USItype)(bl))); \
0745 } while (0)
0746 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0747 do { \
0748     if (__builtin_constant_p(ah) && (ah) == 0) \
0749         __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
0750         : "=r" (sh), \
0751         "=&r" (sl) \
0752         : "r" ((USItype)(bh)), \
0753         "rI" ((USItype)(al)), \
0754         "r" ((USItype)(bl))); \
0755     else if (__builtin_constant_p(ah) && (ah) == ~(USItype) 0) \
0756         __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
0757         : "=r" (sh), \
0758         "=&r" (sl) \
0759         : "r" ((USItype)(bh)), \
0760         "rI" ((USItype)(al)), \
0761         "r" ((USItype)(bl))); \
0762     else if (__builtin_constant_p(bh) && (bh) == 0) \
0763         __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
0764         : "=r" (sh), \
0765         "=&r" (sl) \
0766         : "r" ((USItype)(ah)), \
0767         "rI" ((USItype)(al)), \
0768         "r" ((USItype)(bl))); \
0769     else if (__builtin_constant_p(bh) && (bh) == ~(USItype) 0) \
0770         __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
0771         : "=r" (sh), \
0772         "=&r" (sl) \
0773         : "r" ((USItype)(ah)), \
0774         "rI" ((USItype)(al)), \
0775         "r" ((USItype)(bl))); \
0776     else \
0777         __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
0778         : "=r" (sh), \
0779         "=&r" (sl) \
0780         : "r" ((USItype)(ah)), \
0781         "r" ((USItype)(bh)), \
0782         "rI" ((USItype)(al)), \
0783         "r" ((USItype)(bl))); \
0784 } while (0)
0785 #if defined(_ARCH_PPC)
0786 #define umul_ppmm(ph, pl, m0, m1) \
0787 do { \
0788     USItype __m0 = (m0), __m1 = (m1); \
0789     __asm__ ("mulhwu %0,%1,%2" \
0790     : "=r" (ph) \
0791     : "%r" (__m0), \
0792     "r" (__m1)); \
0793     (pl) = __m0 * __m1; \
0794 } while (0)
0795 #define UMUL_TIME 15
0796 #define smul_ppmm(ph, pl, m0, m1) \
0797 do { \
0798     SItype __m0 = (m0), __m1 = (m1); \
0799     __asm__ ("mulhw %0,%1,%2" \
0800     : "=r" ((SItype) ph) \
0801     : "%r" (__m0), \
0802     "r" (__m1)); \
0803     (pl) = __m0 * __m1; \
0804 } while (0)
0805 #define SMUL_TIME 14
0806 #define UDIV_TIME 120
0807 #else
0808 #define umul_ppmm(xh, xl, m0, m1) \
0809 do { \
0810     USItype __m0 = (m0), __m1 = (m1); \
0811     __asm__ ("mul %0,%2,%3" \
0812     : "=r" ((USItype)(xh)), \
0813     "=q" ((USItype)(xl)) \
0814     : "r" (__m0), \
0815     "r" (__m1)); \
0816     (xh) += ((((SItype) __m0 >> 31) & __m1) \
0817     + (((SItype) __m1 >> 31) & __m0)); \
0818 } while (0)
0819 #define UMUL_TIME 8
0820 #define smul_ppmm(xh, xl, m0, m1) \
0821     __asm__ ("mul %0,%2,%3" \
0822     : "=r" ((SItype)(xh)), \
0823     "=q" ((SItype)(xl)) \
0824     : "r" (m0), \
0825     "r" (m1))
0826 #define SMUL_TIME 4
0827 #define sdiv_qrnnd(q, r, nh, nl, d) \
0828     __asm__ ("div %0,%2,%4" \
0829     : "=r" ((SItype)(q)), "=q" ((SItype)(r)) \
0830     : "r" ((SItype)(nh)), "1" ((SItype)(nl)), "r" ((SItype)(d)))
0831 #define UDIV_TIME 100
0832 #endif
0833 #endif /* Power architecture variants.  */
0834 
0835 /***************************************
0836     **************  PYR  ******************
0837     ***************************************/
0838 #if defined(__pyr__) && W_TYPE_SIZE == 32
0839 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0840     __asm__ ("addw        %5,%1\n" \
0841     "addwc  %3,%0" \
0842     : "=r" ((USItype)(sh)), \
0843     "=&r" ((USItype)(sl)) \
0844     : "%0" ((USItype)(ah)), \
0845     "g" ((USItype)(bh)), \
0846     "%1" ((USItype)(al)), \
0847     "g" ((USItype)(bl)))
0848 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0849     __asm__ ("subw        %5,%1\n" \
0850     "subwb  %3,%0" \
0851     : "=r" ((USItype)(sh)), \
0852     "=&r" ((USItype)(sl)) \
0853     : "0" ((USItype)(ah)), \
0854     "g" ((USItype)(bh)), \
0855     "1" ((USItype)(al)), \
0856     "g" ((USItype)(bl)))
0857     /* This insn works on Pyramids with AP, XP, or MI CPUs, but not with SP.  */
0858 #define umul_ppmm(w1, w0, u, v) \
0859     ({union {UDItype __ll; \
0860     struct {USItype __h, __l; } __i; \
0861     } __xx; \
0862     __asm__ ("movw %1,%R0\n" \
0863     "uemul %2,%0" \
0864     : "=&r" (__xx.__ll) \
0865     : "g" ((USItype) (u)), \
0866     "g" ((USItype)(v))); \
0867     (w1) = __xx.__i.__h; (w0) = __xx.__i.__l; })
0868 #endif /* __pyr__ */
0869 
0870 /***************************************
0871     **************  RT/ROMP  **************
0872     ***************************************/
0873 #if defined(__ibm032__) /* RT/ROMP */   && W_TYPE_SIZE == 32
0874 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0875     __asm__ ("a %1,%5\n" \
0876     "ae %0,%3" \
0877     : "=r" ((USItype)(sh)), \
0878     "=&r" ((USItype)(sl)) \
0879     : "%0" ((USItype)(ah)), \
0880     "r" ((USItype)(bh)), \
0881     "%1" ((USItype)(al)), \
0882     "r" ((USItype)(bl)))
0883 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0884     __asm__ ("s %1,%5\n" \
0885     "se %0,%3" \
0886     : "=r" ((USItype)(sh)), \
0887     "=&r" ((USItype)(sl)) \
0888     : "0" ((USItype)(ah)), \
0889     "r" ((USItype)(bh)), \
0890     "1" ((USItype)(al)), \
0891     "r" ((USItype)(bl)))
0892 #define umul_ppmm(ph, pl, m0, m1) \
0893 do { \
0894     USItype __m0 = (m0), __m1 = (m1); \
0895     __asm__ ( \
0896     "s       r2,r2\n" \
0897     "mts    r10,%2\n" \
0898     "m  r2,%3\n" \
0899     "m  r2,%3\n" \
0900     "m  r2,%3\n" \
0901     "m  r2,%3\n" \
0902     "m  r2,%3\n" \
0903     "m  r2,%3\n" \
0904     "m  r2,%3\n" \
0905     "m  r2,%3\n" \
0906     "m  r2,%3\n" \
0907     "m  r2,%3\n" \
0908     "m  r2,%3\n" \
0909     "m  r2,%3\n" \
0910     "m  r2,%3\n" \
0911     "m  r2,%3\n" \
0912     "m  r2,%3\n" \
0913     "m  r2,%3\n" \
0914     "cas    %0,r2,r0\n" \
0915     "mfs    r10,%1" \
0916     : "=r" ((USItype)(ph)), \
0917     "=r" ((USItype)(pl)) \
0918     : "%r" (__m0), \
0919     "r" (__m1) \
0920     : "r2"); \
0921     (ph) += ((((SItype) __m0 >> 31) & __m1) \
0922     + (((SItype) __m1 >> 31) & __m0)); \
0923 } while (0)
0924 #define UMUL_TIME 20
0925 #define UDIV_TIME 200
0926 #endif /* RT/ROMP */
0927 
0928 /***************************************
0929     **************  SH2  ******************
0930     ***************************************/
0931 #if (defined(__sh2__) || defined(__sh3__) || defined(__SH4__)) \
0932     && W_TYPE_SIZE == 32
0933 #define umul_ppmm(w1, w0, u, v) \
0934     __asm__ ( \
0935     "dmulu.l %2,%3\n" \
0936     "sts    macl,%1\n" \
0937     "sts    mach,%0" \
0938     : "=r" ((USItype)(w1)), \
0939     "=r" ((USItype)(w0)) \
0940     : "r" ((USItype)(u)), \
0941     "r" ((USItype)(v)) \
0942     : "macl", "mach")
0943 #define UMUL_TIME 5
0944 #endif
0945 
0946 /***************************************
0947     **************  SPARC   ****************
0948     ***************************************/
0949 #if defined(__sparc__) && W_TYPE_SIZE == 32
0950 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
0951     __asm__ ("addcc %r4,%5,%1\n" \
0952     "addx %r2,%3,%0" \
0953     : "=r" ((USItype)(sh)), \
0954     "=&r" ((USItype)(sl)) \
0955     : "%rJ" ((USItype)(ah)), \
0956     "rI" ((USItype)(bh)), \
0957     "%rJ" ((USItype)(al)), \
0958     "rI" ((USItype)(bl)) \
0959     __CLOBBER_CC)
0960 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
0961     __asm__ ("subcc %r4,%5,%1\n" \
0962     "subx %r2,%3,%0" \
0963     : "=r" ((USItype)(sh)), \
0964     "=&r" ((USItype)(sl)) \
0965     : "rJ" ((USItype)(ah)), \
0966     "rI" ((USItype)(bh)), \
0967     "rJ" ((USItype)(al)), \
0968     "rI" ((USItype)(bl)) \
0969     __CLOBBER_CC)
0970 #if defined(__sparc_v8__)
0971 /* Don't match immediate range because, 1) it is not often useful,
0972     2) the 'I' flag thinks of the range as a 13 bit signed interval,
0973     while we want to match a 13 bit interval, sign extended to 32 bits,
0974     but INTERPRETED AS UNSIGNED.  */
0975 #define umul_ppmm(w1, w0, u, v) \
0976     __asm__ ("umul %2,%3,%1;rd %%y,%0" \
0977     : "=r" ((USItype)(w1)), \
0978     "=r" ((USItype)(w0)) \
0979     : "r" ((USItype)(u)), \
0980     "r" ((USItype)(v)))
0981 #define UMUL_TIME 5
0982 #ifndef SUPERSPARC      /* SuperSPARC's udiv only handles 53 bit dividends */
0983 #define udiv_qrnnd(q, r, n1, n0, d) \
0984 do { \
0985     USItype __q; \
0986     __asm__ ("mov %1,%%y;nop;nop;nop;udiv %2,%3,%0" \
0987     : "=r" ((USItype)(__q)) \
0988     : "r" ((USItype)(n1)), \
0989     "r" ((USItype)(n0)), \
0990     "r" ((USItype)(d))); \
0991     (r) = (n0) - __q * (d); \
0992     (q) = __q; \
0993 } while (0)
0994 #define UDIV_TIME 25
0995 #endif /* SUPERSPARC */
0996 #else /* ! __sparc_v8__ */
0997 #if defined(__sparclite__)
0998 /* This has hardware multiply but not divide.  It also has two additional
0999     instructions scan (ffs from high bit) and divscc.  */
1000 #define umul_ppmm(w1, w0, u, v) \
1001     __asm__ ("umul %2,%3,%1;rd %%y,%0" \
1002     : "=r" ((USItype)(w1)), \
1003     "=r" ((USItype)(w0)) \
1004     : "r" ((USItype)(u)), \
1005     "r" ((USItype)(v)))
1006 #define UMUL_TIME 5
1007 #define udiv_qrnnd(q, r, n1, n0, d) \
1008     __asm__ ("! Inlined udiv_qrnnd\n" \
1009     "wr %%g0,%2,%%y ! Not a delayed write for sparclite\n" \
1010     "tst    %%g0\n" \
1011     "divscc %3,%4,%%g1\n" \
1012     "divscc %%g1,%4,%%g1\n" \
1013     "divscc %%g1,%4,%%g1\n" \
1014     "divscc %%g1,%4,%%g1\n" \
1015     "divscc %%g1,%4,%%g1\n" \
1016     "divscc %%g1,%4,%%g1\n" \
1017     "divscc %%g1,%4,%%g1\n" \
1018     "divscc %%g1,%4,%%g1\n" \
1019     "divscc %%g1,%4,%%g1\n" \
1020     "divscc %%g1,%4,%%g1\n" \
1021     "divscc %%g1,%4,%%g1\n" \
1022     "divscc %%g1,%4,%%g1\n" \
1023     "divscc %%g1,%4,%%g1\n" \
1024     "divscc %%g1,%4,%%g1\n" \
1025     "divscc %%g1,%4,%%g1\n" \
1026     "divscc %%g1,%4,%%g1\n" \
1027     "divscc %%g1,%4,%%g1\n" \
1028     "divscc %%g1,%4,%%g1\n" \
1029     "divscc %%g1,%4,%%g1\n" \
1030     "divscc %%g1,%4,%%g1\n" \
1031     "divscc %%g1,%4,%%g1\n" \
1032     "divscc %%g1,%4,%%g1\n" \
1033     "divscc %%g1,%4,%%g1\n" \
1034     "divscc %%g1,%4,%%g1\n" \
1035     "divscc %%g1,%4,%%g1\n" \
1036     "divscc %%g1,%4,%%g1\n" \
1037     "divscc %%g1,%4,%%g1\n" \
1038     "divscc %%g1,%4,%%g1\n" \
1039     "divscc %%g1,%4,%%g1\n" \
1040     "divscc %%g1,%4,%%g1\n" \
1041     "divscc %%g1,%4,%%g1\n" \
1042     "divscc %%g1,%4,%0\n" \
1043     "rd %%y,%1\n" \
1044     "bl,a 1f\n" \
1045     "add    %1,%4,%1\n" \
1046     "1: ! End of inline udiv_qrnnd" \
1047     : "=r" ((USItype)(q)), \
1048     "=r" ((USItype)(r)) \
1049     : "r" ((USItype)(n1)), \
1050     "r" ((USItype)(n0)), \
1051     "rI" ((USItype)(d)) \
1052     : "%g1" __AND_CLOBBER_CC)
1053 #define UDIV_TIME 37
1054 #endif /* __sparclite__ */
1055 #endif /* __sparc_v8__ */
1056     /* Default to sparc v7 versions of umul_ppmm and udiv_qrnnd.  */
1057 #ifndef umul_ppmm
1058 #define umul_ppmm(w1, w0, u, v) \
1059     __asm__ ("! Inlined umul_ppmm\n" \
1060     "wr %%g0,%2,%%y ! SPARC has 0-3 delay insn after a wr\n" \
1061     "sra    %3,31,%%g2  ! Don't move this insn\n" \
1062     "and    %2,%%g2,%%g2    ! Don't move this insn\n" \
1063     "andcc  %%g0,0,%%g1 ! Don't move this insn\n" \
1064     "mulscc %%g1,%3,%%g1\n" \
1065     "mulscc %%g1,%3,%%g1\n" \
1066     "mulscc %%g1,%3,%%g1\n" \
1067     "mulscc %%g1,%3,%%g1\n" \
1068     "mulscc %%g1,%3,%%g1\n" \
1069     "mulscc %%g1,%3,%%g1\n" \
1070     "mulscc %%g1,%3,%%g1\n" \
1071     "mulscc %%g1,%3,%%g1\n" \
1072     "mulscc %%g1,%3,%%g1\n" \
1073     "mulscc %%g1,%3,%%g1\n" \
1074     "mulscc %%g1,%3,%%g1\n" \
1075     "mulscc %%g1,%3,%%g1\n" \
1076     "mulscc %%g1,%3,%%g1\n" \
1077     "mulscc %%g1,%3,%%g1\n" \
1078     "mulscc %%g1,%3,%%g1\n" \
1079     "mulscc %%g1,%3,%%g1\n" \
1080     "mulscc %%g1,%3,%%g1\n" \
1081     "mulscc %%g1,%3,%%g1\n" \
1082     "mulscc %%g1,%3,%%g1\n" \
1083     "mulscc %%g1,%3,%%g1\n" \
1084     "mulscc %%g1,%3,%%g1\n" \
1085     "mulscc %%g1,%3,%%g1\n" \
1086     "mulscc %%g1,%3,%%g1\n" \
1087     "mulscc %%g1,%3,%%g1\n" \
1088     "mulscc %%g1,%3,%%g1\n" \
1089     "mulscc %%g1,%3,%%g1\n" \
1090     "mulscc %%g1,%3,%%g1\n" \
1091     "mulscc %%g1,%3,%%g1\n" \
1092     "mulscc %%g1,%3,%%g1\n" \
1093     "mulscc %%g1,%3,%%g1\n" \
1094     "mulscc %%g1,%3,%%g1\n" \
1095     "mulscc %%g1,%3,%%g1\n" \
1096     "mulscc %%g1,0,%%g1\n" \
1097     "add    %%g1,%%g2,%0\n" \
1098     "rd %%y,%1" \
1099     : "=r" ((USItype)(w1)), \
1100     "=r" ((USItype)(w0)) \
1101     : "%rI" ((USItype)(u)), \
1102     "r" ((USItype)(v)) \
1103     : "%g1", "%g2" __AND_CLOBBER_CC)
1104 #define UMUL_TIME 39        /* 39 instructions */
1105 /* It's quite necessary to add this much assembler for the sparc.
1106    The default udiv_qrnnd (in C) is more than 10 times slower!  */
1107 #define udiv_qrnnd(q, r, n1, n0, d) \
1108   __asm__ ("! Inlined udiv_qrnnd\n\t"                   \
1109        "mov 32,%%g1\n\t"                        \
1110        "subcc   %1,%2,%%g0\n\t"                 \
1111        "1:  bcs 5f\n\t"                     \
1112        "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t"    \
1113        "sub %1,%2,%1    ! this kills msb of n\n\t"      \
1114        "addx    %1,%1,%1    ! so this can't give carry\n\t" \
1115        "subcc   %%g1,1,%%g1\n\t"                \
1116        "2:  bne 1b\n\t"                     \
1117        "subcc   %1,%2,%%g0\n\t"                 \
1118        "bcs 3f\n\t"                         \
1119        "addxcc %0,%0,%0 ! shift n1n0 and a q-bit in lsb\n\t"    \
1120        "b       3f\n\t"                     \
1121        "sub %1,%2,%1    ! this kills msb of n\n\t"      \
1122        "4:  sub %1,%2,%1\n\t"                   \
1123        "5:  addxcc  %1,%1,%1\n\t"                   \
1124        "bcc 2b\n\t"                         \
1125        "subcc   %%g1,1,%%g1\n\t"                \
1126        "! Got carry from n.  Subtract next step to cancel this carry.\n\t" \
1127        "bne 4b\n\t"                         \
1128        "addcc   %0,%0,%0    ! shift n1n0 and a 0-bit in lsb\n\t" \
1129        "sub %1,%2,%1\n\t"                       \
1130        "3:  xnor    %0,0,%0\n\t"                    \
1131        "! End of inline udiv_qrnnd\n"               \
1132        : "=&r" ((USItype)(q)),                  \
1133          "=&r" ((USItype)(r))                   \
1134        : "r" ((USItype)(d)),                    \
1135          "1" ((USItype)(n1)),                   \
1136          "0" ((USItype)(n0)) : "%g1", "cc")
1137 #define UDIV_TIME (3+7*32)      /* 7 instructions/iteration. 32 iterations.  */
1138 #endif
1139 #endif /* __sparc__ */
1140 
1141 /***************************************
1142     **************  VAX  ******************
1143     ***************************************/
1144 #if defined(__vax__) && W_TYPE_SIZE == 32
1145 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1146     __asm__ ("addl2 %5,%1\n" \
1147     "adwc %3,%0" \
1148     : "=g" ((USItype)(sh)), \
1149     "=&g" ((USItype)(sl)) \
1150     : "%0" ((USItype)(ah)), \
1151     "g" ((USItype)(bh)), \
1152     "%1" ((USItype)(al)), \
1153     "g" ((USItype)(bl)))
1154 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1155     __asm__ ("subl2 %5,%1\n" \
1156     "sbwc %3,%0" \
1157     : "=g" ((USItype)(sh)), \
1158     "=&g" ((USItype)(sl)) \
1159     : "0" ((USItype)(ah)), \
1160     "g" ((USItype)(bh)), \
1161     "1" ((USItype)(al)), \
1162     "g" ((USItype)(bl)))
1163 #define umul_ppmm(xh, xl, m0, m1) \
1164 do { \
1165     union {UDItype __ll; \
1166     struct {USItype __l, __h; } __i; \
1167     } __xx; \
1168     USItype __m0 = (m0), __m1 = (m1); \
1169     __asm__ ("emul %1,%2,$0,%0" \
1170     : "=g" (__xx.__ll) \
1171     : "g" (__m0), \
1172     "g" (__m1)); \
1173     (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1174     (xh) += ((((SItype) __m0 >> 31) & __m1) \
1175     + (((SItype) __m1 >> 31) & __m0)); \
1176 } while (0)
1177 #define sdiv_qrnnd(q, r, n1, n0, d) \
1178 do { \
1179     union {DItype __ll; \
1180     struct {SItype __l, __h; } __i; \
1181     } __xx; \
1182     __xx.__i.__h = n1; __xx.__i.__l = n0; \
1183     __asm__ ("ediv %3,%2,%0,%1" \
1184     : "=g" (q), "=g" (r) \
1185     : "g" (__xx.__ll), "g" (d)); \
1186 } while (0)
1187 #endif /* __vax__ */
1188 
1189 /***************************************
1190     **************  Z8000   ****************
1191     ***************************************/
1192 #if defined(__z8000__) && W_TYPE_SIZE == 16
1193 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1194     __asm__ ("add %H1,%H5\n\tadc  %H0,%H3" \
1195     : "=r" ((unsigned int)(sh)), \
1196     "=&r" ((unsigned int)(sl)) \
1197     : "%0" ((unsigned int)(ah)), \
1198     "r" ((unsigned int)(bh)), \
1199     "%1" ((unsigned int)(al)), \
1200     "rQR" ((unsigned int)(bl)))
1201 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1202     __asm__ ("sub %H1,%H5\n\tsbc  %H0,%H3" \
1203     : "=r" ((unsigned int)(sh)), \
1204     "=&r" ((unsigned int)(sl)) \
1205     : "0" ((unsigned int)(ah)), \
1206     "r" ((unsigned int)(bh)), \
1207     "1" ((unsigned int)(al)), \
1208     "rQR" ((unsigned int)(bl)))
1209 #define umul_ppmm(xh, xl, m0, m1) \
1210 do { \
1211     union {long int __ll; \
1212     struct {unsigned int __h, __l; } __i; \
1213     } __xx; \
1214     unsigned int __m0 = (m0), __m1 = (m1); \
1215     __asm__ ("mult      %S0,%H3" \
1216     : "=r" (__xx.__i.__h), \
1217     "=r" (__xx.__i.__l) \
1218     : "%1" (__m0), \
1219     "rQR" (__m1)); \
1220     (xh) = __xx.__i.__h; (xl) = __xx.__i.__l; \
1221     (xh) += ((((signed int) __m0 >> 15) & __m1) \
1222     + (((signed int) __m1 >> 15) & __m0)); \
1223 } while (0)
1224 #endif /* __z8000__ */
1225 
1226 #endif /* __GNUC__ */
1227 
1228 /***************************************
1229     ***********  Generic Versions   ********
1230     ***************************************/
1231 #if !defined(umul_ppmm) && defined(__umulsidi3)
1232 #define umul_ppmm(ph, pl, m0, m1) \
1233 { \
1234     UDWtype __ll = __umulsidi3(m0, m1); \
1235     ph = (UWtype) (__ll >> W_TYPE_SIZE); \
1236     pl = (UWtype) __ll; \
1237 }
1238 #endif
1239 
1240 #if !defined(__umulsidi3)
1241 #define __umulsidi3(u, v) \
1242     ({UWtype __hi, __lo; \
1243     umul_ppmm(__hi, __lo, u, v); \
1244     ((UDWtype) __hi << W_TYPE_SIZE) | __lo; })
1245 #endif
1246 
1247     /* If this machine has no inline assembler, use C macros.  */
1248 
1249 #if !defined(add_ssaaaa)
1250 #define add_ssaaaa(sh, sl, ah, al, bh, bl) \
1251 do { \
1252     UWtype __x; \
1253     __x = (al) + (bl); \
1254     (sh) = (ah) + (bh) + (__x < (al)); \
1255     (sl) = __x; \
1256 } while (0)
1257 #endif
1258 
1259 #if !defined(sub_ddmmss)
1260 #define sub_ddmmss(sh, sl, ah, al, bh, bl) \
1261 do { \
1262     UWtype __x; \
1263     __x = (al) - (bl); \
1264     (sh) = (ah) - (bh) - (__x > (al)); \
1265     (sl) = __x; \
1266 } while (0)
1267 #endif
1268 
1269 #if !defined(umul_ppmm)
1270 #define umul_ppmm(w1, w0, u, v) \
1271 do { \
1272     UWtype __x0, __x1, __x2, __x3; \
1273     UHWtype __ul, __vl, __uh, __vh; \
1274     UWtype __u = (u), __v = (v); \
1275     \
1276     __ul = __ll_lowpart(__u); \
1277     __uh = __ll_highpart(__u); \
1278     __vl = __ll_lowpart(__v); \
1279     __vh = __ll_highpart(__v); \
1280     \
1281     __x0 = (UWtype) __ul * __vl; \
1282     __x1 = (UWtype) __ul * __vh; \
1283     __x2 = (UWtype) __uh * __vl; \
1284     __x3 = (UWtype) __uh * __vh; \
1285     \
1286     __x1 += __ll_highpart(__x0);/* this can't give carry */ \
1287     __x1 += __x2;       /* but this indeed can */ \
1288     if (__x1 < __x2)        /* did we get it? */ \
1289     __x3 += __ll_B;     /* yes, add it in the proper pos. */ \
1290     \
1291     (w1) = __x3 + __ll_highpart(__x1); \
1292     (w0) = (__ll_lowpart(__x1) << W_TYPE_SIZE/2) + __ll_lowpart(__x0); \
1293 } while (0)
1294 #endif
1295 
1296 #if !defined(umul_ppmm)
1297 #define smul_ppmm(w1, w0, u, v) \
1298 do { \
1299     UWtype __w1; \
1300     UWtype __m0 = (u), __m1 = (v); \
1301     umul_ppmm(__w1, w0, __m0, __m1); \
1302     (w1) = __w1 - (-(__m0 >> (W_TYPE_SIZE - 1)) & __m1) \
1303     - (-(__m1 >> (W_TYPE_SIZE - 1)) & __m0); \
1304 } while (0)
1305 #endif
1306 
1307     /* Define this unconditionally, so it can be used for debugging.  */
1308 #define __udiv_qrnnd_c(q, r, n1, n0, d) \
1309 do { \
1310     UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
1311     __d1 = __ll_highpart(d); \
1312     __d0 = __ll_lowpart(d); \
1313     \
1314     __r1 = (n1) % __d1; \
1315     __q1 = (n1) / __d1; \
1316     __m = (UWtype) __q1 * __d0; \
1317     __r1 = __r1 * __ll_B | __ll_highpart(n0); \
1318     if (__r1 < __m) { \
1319         __q1--, __r1 += (d); \
1320         if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */ \
1321         if (__r1 < __m) \
1322             __q1--, __r1 += (d); \
1323     } \
1324     __r1 -= __m; \
1325     \
1326     __r0 = __r1 % __d1; \
1327     __q0 = __r1 / __d1; \
1328     __m = (UWtype) __q0 * __d0; \
1329     __r0 = __r0 * __ll_B | __ll_lowpart(n0); \
1330     if (__r0 < __m) { \
1331         __q0--, __r0 += (d); \
1332         if (__r0 >= (d)) \
1333             if (__r0 < __m) \
1334                 __q0--, __r0 += (d); \
1335     } \
1336     __r0 -= __m; \
1337     \
1338     (q) = (UWtype) __q1 * __ll_B | __q0; \
1339     (r) = __r0; \
1340 } while (0)
1341 
1342 /* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
1343     __udiv_w_sdiv (defined in libgcc or elsewhere).  */
1344 #if !defined(udiv_qrnnd) && defined(sdiv_qrnnd)
1345 #define udiv_qrnnd(q, r, nh, nl, d) \
1346 do { \
1347     UWtype __r; \
1348     (q) = __MPN(udiv_w_sdiv) (&__r, nh, nl, d); \
1349     (r) = __r; \
1350 } while (0)
1351 #endif
1352 
1353     /* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
1354 #if !defined(udiv_qrnnd)
1355 #define UDIV_NEEDS_NORMALIZATION 1
1356 #define udiv_qrnnd __udiv_qrnnd_c
1357 #endif
1358 
1359 #ifndef UDIV_NEEDS_NORMALIZATION
1360 #define UDIV_NEEDS_NORMALIZATION 0
1361 #endif
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