kernel/sched/membarrier.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2010-2017 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
0004  *
0005  * membarrier system call
0006  */
0007
0008 /*
0009  * For documentation purposes, here are some membarrier ordering
0010  * scenarios to keep in mind:
0011  *
0012  * A) Userspace thread execution after IPI vs membarrier's memory
0013  *    barrier before sending the IPI
0014  *
0015  * Userspace variables:
0016  *
0017  * int x = 0, y = 0;
0018  *
0019  * The memory barrier at the start of membarrier() on CPU0 is necessary in
0020  * order to enforce the guarantee that any writes occurring on CPU0 before
0021  * the membarrier() is executed will be visible to any code executing on
0022  * CPU1 after the IPI-induced memory barrier:
0023  *
0024  *         CPU0                              CPU1
0025  *
0026  *         x = 1
0027  *         membarrier():
0028  *           a: smp_mb()
0029  *           b: send IPI                       IPI-induced mb
0030  *           c: smp_mb()
0031  *         r2 = y
0032  *                                           y = 1
0033  *                                           barrier()
0034  *                                           r1 = x
0035  *
0036  *                     BUG_ON(r1 == 0 && r2 == 0)
0037  *
0038  * The write to y and load from x by CPU1 are unordered by the hardware,
0039  * so it's possible to have "r1 = x" reordered before "y = 1" at any
0040  * point after (b).  If the memory barrier at (a) is omitted, then "x = 1"
0041  * can be reordered after (a) (although not after (c)), so we get r1 == 0
0042  * and r2 == 0.  This violates the guarantee that membarrier() is
0043  * supposed by provide.
0044  *
0045  * The timing of the memory barrier at (a) has to ensure that it executes
0046  * before the IPI-induced memory barrier on CPU1.
0047  *
0048  * B) Userspace thread execution before IPI vs membarrier's memory
0049  *    barrier after completing the IPI
0050  *
0051  * Userspace variables:
0052  *
0053  * int x = 0, y = 0;
0054  *
0055  * The memory barrier at the end of membarrier() on CPU0 is necessary in
0056  * order to enforce the guarantee that any writes occurring on CPU1 before
0057  * the membarrier() is executed will be visible to any code executing on
0058  * CPU0 after the membarrier():
0059  *
0060  *         CPU0                              CPU1
0061  *
0062  *                                           x = 1
0063  *                                           barrier()
0064  *                                           y = 1
0065  *         r2 = y
0066  *         membarrier():
0067  *           a: smp_mb()
0068  *           b: send IPI                       IPI-induced mb
0069  *           c: smp_mb()
0070  *         r1 = x
0071  *         BUG_ON(r1 == 0 && r2 == 1)
0072  *
0073  * The writes to x and y are unordered by the hardware, so it's possible to
0074  * have "r2 = 1" even though the write to x doesn't execute until (b).  If
0075  * the memory barrier at (c) is omitted then "r1 = x" can be reordered
0076  * before (b) (although not before (a)), so we get "r1 = 0".  This violates
0077  * the guarantee that membarrier() is supposed to provide.
0078  *
0079  * The timing of the memory barrier at (c) has to ensure that it executes
0080  * after the IPI-induced memory barrier on CPU1.
0081  *
0082  * C) Scheduling userspace thread -> kthread -> userspace thread vs membarrier
0083  *
0084  *           CPU0                            CPU1
0085  *
0086  *           membarrier():
0087  *           a: smp_mb()
0088  *                                           d: switch to kthread (includes mb)
0089  *           b: read rq->curr->mm == NULL
0090  *                                           e: switch to user (includes mb)
0091  *           c: smp_mb()
0092  *
0093  * Using the scenario from (A), we can show that (a) needs to be paired
0094  * with (e). Using the scenario from (B), we can show that (c) needs to
0095  * be paired with (d).
0096  *
0097  * D) exit_mm vs membarrier
0098  *
0099  * Two thread groups are created, A and B.  Thread group B is created by
0100  * issuing clone from group A with flag CLONE_VM set, but not CLONE_THREAD.
0101  * Let's assume we have a single thread within each thread group (Thread A
0102  * and Thread B).  Thread A runs on CPU0, Thread B runs on CPU1.
0103  *
0104  *           CPU0                            CPU1
0105  *
0106  *           membarrier():
0107  *             a: smp_mb()
0108  *                                           exit_mm():
0109  *                                             d: smp_mb()
0110  *                                             e: current->mm = NULL
0111  *             b: read rq->curr->mm == NULL
0112  *             c: smp_mb()
0113  *
0114  * Using scenario (B), we can show that (c) needs to be paired with (d).
0115  *
0116  * E) kthread_{use,unuse}_mm vs membarrier
0117  *
0118  *           CPU0                            CPU1
0119  *
0120  *           membarrier():
0121  *           a: smp_mb()
0122  *                                           kthread_unuse_mm()
0123  *                                             d: smp_mb()
0124  *                                             e: current->mm = NULL
0125  *           b: read rq->curr->mm == NULL
0126  *                                           kthread_use_mm()
0127  *                                             f: current->mm = mm
0128  *                                             g: smp_mb()
0129  *           c: smp_mb()
0130  *
0131  * Using the scenario from (A), we can show that (a) needs to be paired
0132  * with (g). Using the scenario from (B), we can show that (c) needs to
0133  * be paired with (d).
0134  */
0135
0136 /*
0137  * Bitmask made from a "or" of all commands within enum membarrier_cmd,
0138  * except MEMBARRIER_CMD_QUERY.
0139  */
0140 #ifdef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
0141 #define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK          \
0142     (MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE         \
0143     | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE)
0144 #else
0145 #define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK  0
0146 #endif
0147
0148 #ifdef CONFIG_RSEQ
0149 #define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK       \
0150     (MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ          \
0151     | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ)
0152 #else
0153 #define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK   0
0154 #endif
0155
0156 #define MEMBARRIER_CMD_BITMASK                      \
0157     (MEMBARRIER_CMD_GLOBAL | MEMBARRIER_CMD_GLOBAL_EXPEDITED    \
0158     | MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED          \
0159     | MEMBARRIER_CMD_PRIVATE_EXPEDITED              \
0160     | MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED         \
0161     | MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK        \
0162     | MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK)
0163
0164 static void ipi_mb(void *info)
0165 {
0166     smp_mb();   /* IPIs should be serializing but paranoid. */
0167 }
0168
0169 static void ipi_sync_core(void *info)
0170 {
0171     /*
0172      * The smp_mb() in membarrier after all the IPIs is supposed to
0173      * ensure that memory on remote CPUs that occur before the IPI
0174      * become visible to membarrier()'s caller -- see scenario B in
0175      * the big comment at the top of this file.
0176      *
0177      * A sync_core() would provide this guarantee, but
0178      * sync_core_before_usermode() might end up being deferred until
0179      * after membarrier()'s smp_mb().
0180      */
0181     smp_mb();   /* IPIs should be serializing but paranoid. */
0182
0183     sync_core_before_usermode();
0184 }
0185
0186 static void ipi_rseq(void *info)
0187 {
0188     /*
0189      * Ensure that all stores done by the calling thread are visible
0190      * to the current task before the current task resumes.  We could
0191      * probably optimize this away on most architectures, but by the
0192      * time we've already sent an IPI, the cost of the extra smp_mb()
0193      * is negligible.
0194      */
0195     smp_mb();
0196     rseq_preempt(current);
0197 }
0198
0199 static void ipi_sync_rq_state(void *info)
0200 {
0201     struct mm_struct *mm = (struct mm_struct *) info;
0202
0203     if (current->mm != mm)
0204         return;
0205     this_cpu_write(runqueues.membarrier_state,
0206                atomic_read(&mm->membarrier_state));
0207     /*
0208      * Issue a memory barrier after setting
0209      * MEMBARRIER_STATE_GLOBAL_EXPEDITED in the current runqueue to
0210      * guarantee that no memory access following registration is reordered
0211      * before registration.
0212      */
0213     smp_mb();
0214 }
0215
0216 void membarrier_exec_mmap(struct mm_struct *mm)
0217 {
0218     /*
0219      * Issue a memory barrier before clearing membarrier_state to
0220      * guarantee that no memory access prior to exec is reordered after
0221      * clearing this state.
0222      */
0223     smp_mb();
0224     atomic_set(&mm->membarrier_state, 0);
0225     /*
0226      * Keep the runqueue membarrier_state in sync with this mm
0227      * membarrier_state.
0228      */
0229     this_cpu_write(runqueues.membarrier_state, 0);
0230 }
0231
0232 void membarrier_update_current_mm(struct mm_struct *next_mm)
0233 {
0234     struct rq *rq = this_rq();
0235     int membarrier_state = 0;
0236
0237     if (next_mm)
0238         membarrier_state = atomic_read(&next_mm->membarrier_state);
0239     if (READ_ONCE(rq->membarrier_state) == membarrier_state)
0240         return;
0241     WRITE_ONCE(rq->membarrier_state, membarrier_state);
0242 }
0243
0244 static int membarrier_global_expedited(void)
0245 {
0246     int cpu;
0247     cpumask_var_t tmpmask;
0248
0249     if (num_online_cpus() == 1)
0250         return 0;
0251
0252     /*
0253      * Matches memory barriers around rq->curr modification in
0254      * scheduler.
0255      */
0256     smp_mb();   /* system call entry is not a mb. */
0257
0258     if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
0259         return -ENOMEM;
0260
0261     cpus_read_lock();
0262     rcu_read_lock();
0263     for_each_online_cpu(cpu) {
0264         struct task_struct *p;
0265
0266         /*
0267          * Skipping the current CPU is OK even through we can be
0268          * migrated at any point. The current CPU, at the point
0269          * where we read raw_smp_processor_id(), is ensured to
0270          * be in program order with respect to the caller
0271          * thread. Therefore, we can skip this CPU from the
0272          * iteration.
0273          */
0274         if (cpu == raw_smp_processor_id())
0275             continue;
0276
0277         if (!(READ_ONCE(cpu_rq(cpu)->membarrier_state) &
0278             MEMBARRIER_STATE_GLOBAL_EXPEDITED))
0279             continue;
0280
0281         /*
0282          * Skip the CPU if it runs a kernel thread which is not using
0283          * a task mm.
0284          */
0285         p = rcu_dereference(cpu_rq(cpu)->curr);
0286         if (!p->mm)
0287             continue;
0288
0289         __cpumask_set_cpu(cpu, tmpmask);
0290     }
0291     rcu_read_unlock();
0292
0293     preempt_disable();
0294     smp_call_function_many(tmpmask, ipi_mb, NULL, 1);
0295     preempt_enable();
0296
0297     free_cpumask_var(tmpmask);
0298     cpus_read_unlock();
0299
0300     /*
0301      * Memory barrier on the caller thread _after_ we finished
0302      * waiting for the last IPI. Matches memory barriers around
0303      * rq->curr modification in scheduler.
0304      */
0305     smp_mb();   /* exit from system call is not a mb */
0306     return 0;
0307 }
0308
0309 static int membarrier_private_expedited(int flags, int cpu_id)
0310 {
0311     cpumask_var_t tmpmask;
0312     struct mm_struct *mm = current->mm;
0313     smp_call_func_t ipi_func = ipi_mb;
0314
0315     if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
0316         if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
0317             return -EINVAL;
0318         if (!(atomic_read(&mm->membarrier_state) &
0319               MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
0320             return -EPERM;
0321         ipi_func = ipi_sync_core;
0322     } else if (flags == MEMBARRIER_FLAG_RSEQ) {
0323         if (!IS_ENABLED(CONFIG_RSEQ))
0324             return -EINVAL;
0325         if (!(atomic_read(&mm->membarrier_state) &
0326               MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY))
0327             return -EPERM;
0328         ipi_func = ipi_rseq;
0329     } else {
0330         WARN_ON_ONCE(flags);
0331         if (!(atomic_read(&mm->membarrier_state) &
0332               MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY))
0333             return -EPERM;
0334     }
0335
0336     if (flags != MEMBARRIER_FLAG_SYNC_CORE &&
0337         (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1))
0338         return 0;
0339
0340     /*
0341      * Matches memory barriers around rq->curr modification in
0342      * scheduler.
0343      */
0344     smp_mb();   /* system call entry is not a mb. */
0345
0346     if (cpu_id < 0 && !zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
0347         return -ENOMEM;
0348
0349     cpus_read_lock();
0350
0351     if (cpu_id >= 0) {
0352         struct task_struct *p;
0353
0354         if (cpu_id >= nr_cpu_ids || !cpu_online(cpu_id))
0355             goto out;
0356         rcu_read_lock();
0357         p = rcu_dereference(cpu_rq(cpu_id)->curr);
0358         if (!p || p->mm != mm) {
0359             rcu_read_unlock();
0360             goto out;
0361         }
0362         rcu_read_unlock();
0363     } else {
0364         int cpu;
0365
0366         rcu_read_lock();
0367         for_each_online_cpu(cpu) {
0368             struct task_struct *p;
0369
0370             p = rcu_dereference(cpu_rq(cpu)->curr);
0371             if (p && p->mm == mm)
0372                 __cpumask_set_cpu(cpu, tmpmask);
0373         }
0374         rcu_read_unlock();
0375     }
0376
0377     if (cpu_id >= 0) {
0378         /*
0379          * smp_call_function_single() will call ipi_func() if cpu_id
0380          * is the calling CPU.
0381          */
0382         smp_call_function_single(cpu_id, ipi_func, NULL, 1);
0383     } else {
0384         /*
0385          * For regular membarrier, we can save a few cycles by
0386          * skipping the current cpu -- we're about to do smp_mb()
0387          * below, and if we migrate to a different cpu, this cpu
0388          * and the new cpu will execute a full barrier in the
0389          * scheduler.
0390          *
0391          * For SYNC_CORE, we do need a barrier on the current cpu --
0392          * otherwise, if we are migrated and replaced by a different
0393          * task in the same mm just before, during, or after
0394          * membarrier, we will end up with some thread in the mm
0395          * running without a core sync.
0396          *
0397          * For RSEQ, don't rseq_preempt() the caller.  User code
0398          * is not supposed to issue syscalls at all from inside an
0399          * rseq critical section.
0400          */
0401         if (flags != MEMBARRIER_FLAG_SYNC_CORE) {
0402             preempt_disable();
0403             smp_call_function_many(tmpmask, ipi_func, NULL, true);
0404             preempt_enable();
0405         } else {
0406             on_each_cpu_mask(tmpmask, ipi_func, NULL, true);
0407         }
0408     }
0409
0410 out:
0411     if (cpu_id < 0)
0412         free_cpumask_var(tmpmask);
0413     cpus_read_unlock();
0414
0415     /*
0416      * Memory barrier on the caller thread _after_ we finished
0417      * waiting for the last IPI. Matches memory barriers around
0418      * rq->curr modification in scheduler.
0419      */
0420     smp_mb();   /* exit from system call is not a mb */
0421
0422     return 0;
0423 }
0424
0425 static int sync_runqueues_membarrier_state(struct mm_struct *mm)
0426 {
0427     int membarrier_state = atomic_read(&mm->membarrier_state);
0428     cpumask_var_t tmpmask;
0429     int cpu;
0430
0431     if (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1) {
0432         this_cpu_write(runqueues.membarrier_state, membarrier_state);
0433
0434         /*
0435          * For single mm user, we can simply issue a memory barrier
0436          * after setting MEMBARRIER_STATE_GLOBAL_EXPEDITED in the
0437          * mm and in the current runqueue to guarantee that no memory
0438          * access following registration is reordered before
0439          * registration.
0440          */
0441         smp_mb();
0442         return 0;
0443     }
0444
0445     if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
0446         return -ENOMEM;
0447
0448     /*
0449      * For mm with multiple users, we need to ensure all future
0450      * scheduler executions will observe @mm's new membarrier
0451      * state.
0452      */
0453     synchronize_rcu();
0454
0455     /*
0456      * For each cpu runqueue, if the task's mm match @mm, ensure that all
0457      * @mm's membarrier state set bits are also set in the runqueue's
0458      * membarrier state. This ensures that a runqueue scheduling
0459      * between threads which are users of @mm has its membarrier state
0460      * updated.
0461      */
0462     cpus_read_lock();
0463     rcu_read_lock();
0464     for_each_online_cpu(cpu) {
0465         struct rq *rq = cpu_rq(cpu);
0466         struct task_struct *p;
0467
0468         p = rcu_dereference(rq->curr);
0469         if (p && p->mm == mm)
0470             __cpumask_set_cpu(cpu, tmpmask);
0471     }
0472     rcu_read_unlock();
0473
0474     on_each_cpu_mask(tmpmask, ipi_sync_rq_state, mm, true);
0475
0476     free_cpumask_var(tmpmask);
0477     cpus_read_unlock();
0478
0479     return 0;
0480 }
0481
0482 static int membarrier_register_global_expedited(void)
0483 {
0484     struct task_struct *p = current;
0485     struct mm_struct *mm = p->mm;
0486     int ret;
0487
0488     if (atomic_read(&mm->membarrier_state) &
0489         MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY)
0490         return 0;
0491     atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED, &mm->membarrier_state);
0492     ret = sync_runqueues_membarrier_state(mm);
0493     if (ret)
0494         return ret;
0495     atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY,
0496           &mm->membarrier_state);
0497
0498     return 0;
0499 }
0500
0501 static int membarrier_register_private_expedited(int flags)
0502 {
0503     struct task_struct *p = current;
0504     struct mm_struct *mm = p->mm;
0505     int ready_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY,
0506         set_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED,
0507         ret;
0508
0509     if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
0510         if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
0511             return -EINVAL;
0512         ready_state =
0513             MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY;
0514     } else if (flags == MEMBARRIER_FLAG_RSEQ) {
0515         if (!IS_ENABLED(CONFIG_RSEQ))
0516             return -EINVAL;
0517         ready_state =
0518             MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY;
0519     } else {
0520         WARN_ON_ONCE(flags);
0521     }
0522
0523     /*
0524      * We need to consider threads belonging to different thread
0525      * groups, which use the same mm. (CLONE_VM but not
0526      * CLONE_THREAD).
0527      */
0528     if ((atomic_read(&mm->membarrier_state) & ready_state) == ready_state)
0529         return 0;
0530     if (flags & MEMBARRIER_FLAG_SYNC_CORE)
0531         set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE;
0532     if (flags & MEMBARRIER_FLAG_RSEQ)
0533         set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ;
0534     atomic_or(set_state, &mm->membarrier_state);
0535     ret = sync_runqueues_membarrier_state(mm);
0536     if (ret)
0537         return ret;
0538     atomic_or(ready_state, &mm->membarrier_state);
0539
0540     return 0;
0541 }
0542
0543 /**
0544  * sys_membarrier - issue memory barriers on a set of threads
0545  * @cmd:    Takes command values defined in enum membarrier_cmd.
0546  * @flags:  Currently needs to be 0 for all commands other than
0547  *          MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ: in the latter
0548  *          case it can be MEMBARRIER_CMD_FLAG_CPU, indicating that @cpu_id
0549  *          contains the CPU on which to interrupt (= restart)
0550  *          the RSEQ critical section.
0551  * @cpu_id: if @flags == MEMBARRIER_CMD_FLAG_CPU, indicates the cpu on which
0552  *          RSEQ CS should be interrupted (@cmd must be
0553  *          MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ).
0554  *
0555  * If this system call is not implemented, -ENOSYS is returned. If the
0556  * command specified does not exist, not available on the running
0557  * kernel, or if the command argument is invalid, this system call
0558  * returns -EINVAL. For a given command, with flags argument set to 0,
0559  * if this system call returns -ENOSYS or -EINVAL, it is guaranteed to
0560  * always return the same value until reboot. In addition, it can return
0561  * -ENOMEM if there is not enough memory available to perform the system
0562  * call.
0563  *
0564  * All memory accesses performed in program order from each targeted thread
0565  * is guaranteed to be ordered with respect to sys_membarrier(). If we use
0566  * the semantic "barrier()" to represent a compiler barrier forcing memory
0567  * accesses to be performed in program order across the barrier, and
0568  * smp_mb() to represent explicit memory barriers forcing full memory
0569  * ordering across the barrier, we have the following ordering table for
0570  * each pair of barrier(), sys_membarrier() and smp_mb():
0571  *
0572  * The pair ordering is detailed as (O: ordered, X: not ordered):
0573  *
0574  *                        barrier()   smp_mb() sys_membarrier()
0575  *        barrier()          X           X            O
0576  *        smp_mb()           X           O            O
0577  *        sys_membarrier()   O           O            O
0578  */
0579 SYSCALL_DEFINE3(membarrier, int, cmd, unsigned int, flags, int, cpu_id)
0580 {
0581     switch (cmd) {
0582     case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
0583         if (unlikely(flags && flags != MEMBARRIER_CMD_FLAG_CPU))
0584             return -EINVAL;
0585         break;
0586     default:
0587         if (unlikely(flags))
0588             return -EINVAL;
0589     }
0590
0591     if (!(flags & MEMBARRIER_CMD_FLAG_CPU))
0592         cpu_id = -1;
0593
0594     switch (cmd) {
0595     case MEMBARRIER_CMD_QUERY:
0596     {
0597         int cmd_mask = MEMBARRIER_CMD_BITMASK;
0598
0599         if (tick_nohz_full_enabled())
0600             cmd_mask &= ~MEMBARRIER_CMD_GLOBAL;
0601         return cmd_mask;
0602     }
0603     case MEMBARRIER_CMD_GLOBAL:
0604         /* MEMBARRIER_CMD_GLOBAL is not compatible with nohz_full. */
0605         if (tick_nohz_full_enabled())
0606             return -EINVAL;
0607         if (num_online_cpus() > 1)
0608             synchronize_rcu();
0609         return 0;
0610     case MEMBARRIER_CMD_GLOBAL_EXPEDITED:
0611         return membarrier_global_expedited();
0612     case MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED:
0613         return membarrier_register_global_expedited();
0614     case MEMBARRIER_CMD_PRIVATE_EXPEDITED:
0615         return membarrier_private_expedited(0, cpu_id);
0616     case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED:
0617         return membarrier_register_private_expedited(0);
0618     case MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE:
0619         return membarrier_private_expedited(MEMBARRIER_FLAG_SYNC_CORE, cpu_id);
0620     case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE:
0621         return membarrier_register_private_expedited(MEMBARRIER_FLAG_SYNC_CORE);
0622     case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
0623         return membarrier_private_expedited(MEMBARRIER_FLAG_RSEQ, cpu_id);
0624     case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ:
0625         return membarrier_register_private_expedited(MEMBARRIER_FLAG_RSEQ);
0626     default:
0627         return -EINVAL;
0628     }
0629 }