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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Library implementing the most common irq chip callback functions
0004  *
0005  * Copyright (C) 2011, Thomas Gleixner
0006  */
0007 #include <linux/io.h>
0008 #include <linux/irq.h>
0009 #include <linux/slab.h>
0010 #include <linux/export.h>
0011 #include <linux/irqdomain.h>
0012 #include <linux/interrupt.h>
0013 #include <linux/kernel_stat.h>
0014 #include <linux/syscore_ops.h>
0015 
0016 #include "internals.h"
0017 
0018 static LIST_HEAD(gc_list);
0019 static DEFINE_RAW_SPINLOCK(gc_lock);
0020 
0021 /**
0022  * irq_gc_noop - NOOP function
0023  * @d: irq_data
0024  */
0025 void irq_gc_noop(struct irq_data *d)
0026 {
0027 }
0028 EXPORT_SYMBOL_GPL(irq_gc_noop);
0029 
0030 /**
0031  * irq_gc_mask_disable_reg - Mask chip via disable register
0032  * @d: irq_data
0033  *
0034  * Chip has separate enable/disable registers instead of a single mask
0035  * register.
0036  */
0037 void irq_gc_mask_disable_reg(struct irq_data *d)
0038 {
0039     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0040     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0041     u32 mask = d->mask;
0042 
0043     irq_gc_lock(gc);
0044     irq_reg_writel(gc, mask, ct->regs.disable);
0045     *ct->mask_cache &= ~mask;
0046     irq_gc_unlock(gc);
0047 }
0048 EXPORT_SYMBOL_GPL(irq_gc_mask_disable_reg);
0049 
0050 /**
0051  * irq_gc_mask_set_bit - Mask chip via setting bit in mask register
0052  * @d: irq_data
0053  *
0054  * Chip has a single mask register. Values of this register are cached
0055  * and protected by gc->lock
0056  */
0057 void irq_gc_mask_set_bit(struct irq_data *d)
0058 {
0059     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0060     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0061     u32 mask = d->mask;
0062 
0063     irq_gc_lock(gc);
0064     *ct->mask_cache |= mask;
0065     irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
0066     irq_gc_unlock(gc);
0067 }
0068 EXPORT_SYMBOL_GPL(irq_gc_mask_set_bit);
0069 
0070 /**
0071  * irq_gc_mask_clr_bit - Mask chip via clearing bit in mask register
0072  * @d: irq_data
0073  *
0074  * Chip has a single mask register. Values of this register are cached
0075  * and protected by gc->lock
0076  */
0077 void irq_gc_mask_clr_bit(struct irq_data *d)
0078 {
0079     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0080     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0081     u32 mask = d->mask;
0082 
0083     irq_gc_lock(gc);
0084     *ct->mask_cache &= ~mask;
0085     irq_reg_writel(gc, *ct->mask_cache, ct->regs.mask);
0086     irq_gc_unlock(gc);
0087 }
0088 EXPORT_SYMBOL_GPL(irq_gc_mask_clr_bit);
0089 
0090 /**
0091  * irq_gc_unmask_enable_reg - Unmask chip via enable register
0092  * @d: irq_data
0093  *
0094  * Chip has separate enable/disable registers instead of a single mask
0095  * register.
0096  */
0097 void irq_gc_unmask_enable_reg(struct irq_data *d)
0098 {
0099     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0100     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0101     u32 mask = d->mask;
0102 
0103     irq_gc_lock(gc);
0104     irq_reg_writel(gc, mask, ct->regs.enable);
0105     *ct->mask_cache |= mask;
0106     irq_gc_unlock(gc);
0107 }
0108 EXPORT_SYMBOL_GPL(irq_gc_unmask_enable_reg);
0109 
0110 /**
0111  * irq_gc_ack_set_bit - Ack pending interrupt via setting bit
0112  * @d: irq_data
0113  */
0114 void irq_gc_ack_set_bit(struct irq_data *d)
0115 {
0116     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0117     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0118     u32 mask = d->mask;
0119 
0120     irq_gc_lock(gc);
0121     irq_reg_writel(gc, mask, ct->regs.ack);
0122     irq_gc_unlock(gc);
0123 }
0124 EXPORT_SYMBOL_GPL(irq_gc_ack_set_bit);
0125 
0126 /**
0127  * irq_gc_ack_clr_bit - Ack pending interrupt via clearing bit
0128  * @d: irq_data
0129  */
0130 void irq_gc_ack_clr_bit(struct irq_data *d)
0131 {
0132     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0133     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0134     u32 mask = ~d->mask;
0135 
0136     irq_gc_lock(gc);
0137     irq_reg_writel(gc, mask, ct->regs.ack);
0138     irq_gc_unlock(gc);
0139 }
0140 
0141 /**
0142  * irq_gc_mask_disable_and_ack_set - Mask and ack pending interrupt
0143  * @d: irq_data
0144  *
0145  * This generic implementation of the irq_mask_ack method is for chips
0146  * with separate enable/disable registers instead of a single mask
0147  * register and where a pending interrupt is acknowledged by setting a
0148  * bit.
0149  *
0150  * Note: This is the only permutation currently used.  Similar generic
0151  * functions should be added here if other permutations are required.
0152  */
0153 void irq_gc_mask_disable_and_ack_set(struct irq_data *d)
0154 {
0155     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0156     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0157     u32 mask = d->mask;
0158 
0159     irq_gc_lock(gc);
0160     irq_reg_writel(gc, mask, ct->regs.disable);
0161     *ct->mask_cache &= ~mask;
0162     irq_reg_writel(gc, mask, ct->regs.ack);
0163     irq_gc_unlock(gc);
0164 }
0165 
0166 /**
0167  * irq_gc_eoi - EOI interrupt
0168  * @d: irq_data
0169  */
0170 void irq_gc_eoi(struct irq_data *d)
0171 {
0172     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0173     struct irq_chip_type *ct = irq_data_get_chip_type(d);
0174     u32 mask = d->mask;
0175 
0176     irq_gc_lock(gc);
0177     irq_reg_writel(gc, mask, ct->regs.eoi);
0178     irq_gc_unlock(gc);
0179 }
0180 
0181 /**
0182  * irq_gc_set_wake - Set/clr wake bit for an interrupt
0183  * @d:  irq_data
0184  * @on: Indicates whether the wake bit should be set or cleared
0185  *
0186  * For chips where the wake from suspend functionality is not
0187  * configured in a separate register and the wakeup active state is
0188  * just stored in a bitmask.
0189  */
0190 int irq_gc_set_wake(struct irq_data *d, unsigned int on)
0191 {
0192     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0193     u32 mask = d->mask;
0194 
0195     if (!(mask & gc->wake_enabled))
0196         return -EINVAL;
0197 
0198     irq_gc_lock(gc);
0199     if (on)
0200         gc->wake_active |= mask;
0201     else
0202         gc->wake_active &= ~mask;
0203     irq_gc_unlock(gc);
0204     return 0;
0205 }
0206 EXPORT_SYMBOL_GPL(irq_gc_set_wake);
0207 
0208 static u32 irq_readl_be(void __iomem *addr)
0209 {
0210     return ioread32be(addr);
0211 }
0212 
0213 static void irq_writel_be(u32 val, void __iomem *addr)
0214 {
0215     iowrite32be(val, addr);
0216 }
0217 
0218 void irq_init_generic_chip(struct irq_chip_generic *gc, const char *name,
0219                int num_ct, unsigned int irq_base,
0220                void __iomem *reg_base, irq_flow_handler_t handler)
0221 {
0222     raw_spin_lock_init(&gc->lock);
0223     gc->num_ct = num_ct;
0224     gc->irq_base = irq_base;
0225     gc->reg_base = reg_base;
0226     gc->chip_types->chip.name = name;
0227     gc->chip_types->handler = handler;
0228 }
0229 
0230 /**
0231  * irq_alloc_generic_chip - Allocate a generic chip and initialize it
0232  * @name:   Name of the irq chip
0233  * @num_ct: Number of irq_chip_type instances associated with this
0234  * @irq_base:   Interrupt base nr for this chip
0235  * @reg_base:   Register base address (virtual)
0236  * @handler:    Default flow handler associated with this chip
0237  *
0238  * Returns an initialized irq_chip_generic structure. The chip defaults
0239  * to the primary (index 0) irq_chip_type and @handler
0240  */
0241 struct irq_chip_generic *
0242 irq_alloc_generic_chip(const char *name, int num_ct, unsigned int irq_base,
0243                void __iomem *reg_base, irq_flow_handler_t handler)
0244 {
0245     struct irq_chip_generic *gc;
0246 
0247     gc = kzalloc(struct_size(gc, chip_types, num_ct), GFP_KERNEL);
0248     if (gc) {
0249         irq_init_generic_chip(gc, name, num_ct, irq_base, reg_base,
0250                       handler);
0251     }
0252     return gc;
0253 }
0254 EXPORT_SYMBOL_GPL(irq_alloc_generic_chip);
0255 
0256 static void
0257 irq_gc_init_mask_cache(struct irq_chip_generic *gc, enum irq_gc_flags flags)
0258 {
0259     struct irq_chip_type *ct = gc->chip_types;
0260     u32 *mskptr = &gc->mask_cache, mskreg = ct->regs.mask;
0261     int i;
0262 
0263     for (i = 0; i < gc->num_ct; i++) {
0264         if (flags & IRQ_GC_MASK_CACHE_PER_TYPE) {
0265             mskptr = &ct[i].mask_cache_priv;
0266             mskreg = ct[i].regs.mask;
0267         }
0268         ct[i].mask_cache = mskptr;
0269         if (flags & IRQ_GC_INIT_MASK_CACHE)
0270             *mskptr = irq_reg_readl(gc, mskreg);
0271     }
0272 }
0273 
0274 /**
0275  * __irq_alloc_domain_generic_chips - Allocate generic chips for an irq domain
0276  * @d:          irq domain for which to allocate chips
0277  * @irqs_per_chip:  Number of interrupts each chip handles (max 32)
0278  * @num_ct:     Number of irq_chip_type instances associated with this
0279  * @name:       Name of the irq chip
0280  * @handler:        Default flow handler associated with these chips
0281  * @clr:        IRQ_* bits to clear in the mapping function
0282  * @set:        IRQ_* bits to set in the mapping function
0283  * @gcflags:        Generic chip specific setup flags
0284  */
0285 int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
0286                      int num_ct, const char *name,
0287                      irq_flow_handler_t handler,
0288                      unsigned int clr, unsigned int set,
0289                      enum irq_gc_flags gcflags)
0290 {
0291     struct irq_domain_chip_generic *dgc;
0292     struct irq_chip_generic *gc;
0293     unsigned long flags;
0294     int numchips, i;
0295     size_t dgc_sz;
0296     size_t gc_sz;
0297     size_t sz;
0298     void *tmp;
0299 
0300     if (d->gc)
0301         return -EBUSY;
0302 
0303     numchips = DIV_ROUND_UP(d->revmap_size, irqs_per_chip);
0304     if (!numchips)
0305         return -EINVAL;
0306 
0307     /* Allocate a pointer, generic chip and chiptypes for each chip */
0308     gc_sz = struct_size(gc, chip_types, num_ct);
0309     dgc_sz = struct_size(dgc, gc, numchips);
0310     sz = dgc_sz + numchips * gc_sz;
0311 
0312     tmp = dgc = kzalloc(sz, GFP_KERNEL);
0313     if (!dgc)
0314         return -ENOMEM;
0315     dgc->irqs_per_chip = irqs_per_chip;
0316     dgc->num_chips = numchips;
0317     dgc->irq_flags_to_set = set;
0318     dgc->irq_flags_to_clear = clr;
0319     dgc->gc_flags = gcflags;
0320     d->gc = dgc;
0321 
0322     /* Calc pointer to the first generic chip */
0323     tmp += dgc_sz;
0324     for (i = 0; i < numchips; i++) {
0325         /* Store the pointer to the generic chip */
0326         dgc->gc[i] = gc = tmp;
0327         irq_init_generic_chip(gc, name, num_ct, i * irqs_per_chip,
0328                       NULL, handler);
0329 
0330         gc->domain = d;
0331         if (gcflags & IRQ_GC_BE_IO) {
0332             gc->reg_readl = &irq_readl_be;
0333             gc->reg_writel = &irq_writel_be;
0334         }
0335 
0336         raw_spin_lock_irqsave(&gc_lock, flags);
0337         list_add_tail(&gc->list, &gc_list);
0338         raw_spin_unlock_irqrestore(&gc_lock, flags);
0339         /* Calc pointer to the next generic chip */
0340         tmp += gc_sz;
0341     }
0342     return 0;
0343 }
0344 EXPORT_SYMBOL_GPL(__irq_alloc_domain_generic_chips);
0345 
0346 static struct irq_chip_generic *
0347 __irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
0348 {
0349     struct irq_domain_chip_generic *dgc = d->gc;
0350     int idx;
0351 
0352     if (!dgc)
0353         return ERR_PTR(-ENODEV);
0354     idx = hw_irq / dgc->irqs_per_chip;
0355     if (idx >= dgc->num_chips)
0356         return ERR_PTR(-EINVAL);
0357     return dgc->gc[idx];
0358 }
0359 
0360 /**
0361  * irq_get_domain_generic_chip - Get a pointer to the generic chip of a hw_irq
0362  * @d:          irq domain pointer
0363  * @hw_irq:     Hardware interrupt number
0364  */
0365 struct irq_chip_generic *
0366 irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq)
0367 {
0368     struct irq_chip_generic *gc = __irq_get_domain_generic_chip(d, hw_irq);
0369 
0370     return !IS_ERR(gc) ? gc : NULL;
0371 }
0372 EXPORT_SYMBOL_GPL(irq_get_domain_generic_chip);
0373 
0374 /*
0375  * Separate lockdep classes for interrupt chip which can nest irq_desc
0376  * lock and request mutex.
0377  */
0378 static struct lock_class_key irq_nested_lock_class;
0379 static struct lock_class_key irq_nested_request_class;
0380 
0381 /*
0382  * irq_map_generic_chip - Map a generic chip for an irq domain
0383  */
0384 int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
0385              irq_hw_number_t hw_irq)
0386 {
0387     struct irq_data *data = irq_domain_get_irq_data(d, virq);
0388     struct irq_domain_chip_generic *dgc = d->gc;
0389     struct irq_chip_generic *gc;
0390     struct irq_chip_type *ct;
0391     struct irq_chip *chip;
0392     unsigned long flags;
0393     int idx;
0394 
0395     gc = __irq_get_domain_generic_chip(d, hw_irq);
0396     if (IS_ERR(gc))
0397         return PTR_ERR(gc);
0398 
0399     idx = hw_irq % dgc->irqs_per_chip;
0400 
0401     if (test_bit(idx, &gc->unused))
0402         return -ENOTSUPP;
0403 
0404     if (test_bit(idx, &gc->installed))
0405         return -EBUSY;
0406 
0407     ct = gc->chip_types;
0408     chip = &ct->chip;
0409 
0410     /* We only init the cache for the first mapping of a generic chip */
0411     if (!gc->installed) {
0412         raw_spin_lock_irqsave(&gc->lock, flags);
0413         irq_gc_init_mask_cache(gc, dgc->gc_flags);
0414         raw_spin_unlock_irqrestore(&gc->lock, flags);
0415     }
0416 
0417     /* Mark the interrupt as installed */
0418     set_bit(idx, &gc->installed);
0419 
0420     if (dgc->gc_flags & IRQ_GC_INIT_NESTED_LOCK)
0421         irq_set_lockdep_class(virq, &irq_nested_lock_class,
0422                       &irq_nested_request_class);
0423 
0424     if (chip->irq_calc_mask)
0425         chip->irq_calc_mask(data);
0426     else
0427         data->mask = 1 << idx;
0428 
0429     irq_domain_set_info(d, virq, hw_irq, chip, gc, ct->handler, NULL, NULL);
0430     irq_modify_status(virq, dgc->irq_flags_to_clear, dgc->irq_flags_to_set);
0431     return 0;
0432 }
0433 
0434 void irq_unmap_generic_chip(struct irq_domain *d, unsigned int virq)
0435 {
0436     struct irq_data *data = irq_domain_get_irq_data(d, virq);
0437     struct irq_domain_chip_generic *dgc = d->gc;
0438     unsigned int hw_irq = data->hwirq;
0439     struct irq_chip_generic *gc;
0440     int irq_idx;
0441 
0442     gc = irq_get_domain_generic_chip(d, hw_irq);
0443     if (!gc)
0444         return;
0445 
0446     irq_idx = hw_irq % dgc->irqs_per_chip;
0447 
0448     clear_bit(irq_idx, &gc->installed);
0449     irq_domain_set_info(d, virq, hw_irq, &no_irq_chip, NULL, NULL, NULL,
0450                 NULL);
0451 
0452 }
0453 
0454 const struct irq_domain_ops irq_generic_chip_ops = {
0455     .map    = irq_map_generic_chip,
0456     .unmap  = irq_unmap_generic_chip,
0457     .xlate  = irq_domain_xlate_onetwocell,
0458 };
0459 EXPORT_SYMBOL_GPL(irq_generic_chip_ops);
0460 
0461 /**
0462  * irq_setup_generic_chip - Setup a range of interrupts with a generic chip
0463  * @gc:     Generic irq chip holding all data
0464  * @msk:    Bitmask holding the irqs to initialize relative to gc->irq_base
0465  * @flags:  Flags for initialization
0466  * @clr:    IRQ_* bits to clear
0467  * @set:    IRQ_* bits to set
0468  *
0469  * Set up max. 32 interrupts starting from gc->irq_base. Note, this
0470  * initializes all interrupts to the primary irq_chip_type and its
0471  * associated handler.
0472  */
0473 void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
0474                 enum irq_gc_flags flags, unsigned int clr,
0475                 unsigned int set)
0476 {
0477     struct irq_chip_type *ct = gc->chip_types;
0478     struct irq_chip *chip = &ct->chip;
0479     unsigned int i;
0480 
0481     raw_spin_lock(&gc_lock);
0482     list_add_tail(&gc->list, &gc_list);
0483     raw_spin_unlock(&gc_lock);
0484 
0485     irq_gc_init_mask_cache(gc, flags);
0486 
0487     for (i = gc->irq_base; msk; msk >>= 1, i++) {
0488         if (!(msk & 0x01))
0489             continue;
0490 
0491         if (flags & IRQ_GC_INIT_NESTED_LOCK)
0492             irq_set_lockdep_class(i, &irq_nested_lock_class,
0493                           &irq_nested_request_class);
0494 
0495         if (!(flags & IRQ_GC_NO_MASK)) {
0496             struct irq_data *d = irq_get_irq_data(i);
0497 
0498             if (chip->irq_calc_mask)
0499                 chip->irq_calc_mask(d);
0500             else
0501                 d->mask = 1 << (i - gc->irq_base);
0502         }
0503         irq_set_chip_and_handler(i, chip, ct->handler);
0504         irq_set_chip_data(i, gc);
0505         irq_modify_status(i, clr, set);
0506     }
0507     gc->irq_cnt = i - gc->irq_base;
0508 }
0509 EXPORT_SYMBOL_GPL(irq_setup_generic_chip);
0510 
0511 /**
0512  * irq_setup_alt_chip - Switch to alternative chip
0513  * @d:      irq_data for this interrupt
0514  * @type:   Flow type to be initialized
0515  *
0516  * Only to be called from chip->irq_set_type() callbacks.
0517  */
0518 int irq_setup_alt_chip(struct irq_data *d, unsigned int type)
0519 {
0520     struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
0521     struct irq_chip_type *ct = gc->chip_types;
0522     unsigned int i;
0523 
0524     for (i = 0; i < gc->num_ct; i++, ct++) {
0525         if (ct->type & type) {
0526             d->chip = &ct->chip;
0527             irq_data_to_desc(d)->handle_irq = ct->handler;
0528             return 0;
0529         }
0530     }
0531     return -EINVAL;
0532 }
0533 EXPORT_SYMBOL_GPL(irq_setup_alt_chip);
0534 
0535 /**
0536  * irq_remove_generic_chip - Remove a chip
0537  * @gc:     Generic irq chip holding all data
0538  * @msk:    Bitmask holding the irqs to initialize relative to gc->irq_base
0539  * @clr:    IRQ_* bits to clear
0540  * @set:    IRQ_* bits to set
0541  *
0542  * Remove up to 32 interrupts starting from gc->irq_base.
0543  */
0544 void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
0545                  unsigned int clr, unsigned int set)
0546 {
0547     unsigned int i = gc->irq_base;
0548 
0549     raw_spin_lock(&gc_lock);
0550     list_del(&gc->list);
0551     raw_spin_unlock(&gc_lock);
0552 
0553     for (; msk; msk >>= 1, i++) {
0554         if (!(msk & 0x01))
0555             continue;
0556 
0557         /* Remove handler first. That will mask the irq line */
0558         irq_set_handler(i, NULL);
0559         irq_set_chip(i, &no_irq_chip);
0560         irq_set_chip_data(i, NULL);
0561         irq_modify_status(i, clr, set);
0562     }
0563 }
0564 EXPORT_SYMBOL_GPL(irq_remove_generic_chip);
0565 
0566 static struct irq_data *irq_gc_get_irq_data(struct irq_chip_generic *gc)
0567 {
0568     unsigned int virq;
0569 
0570     if (!gc->domain)
0571         return irq_get_irq_data(gc->irq_base);
0572 
0573     /*
0574      * We don't know which of the irqs has been actually
0575      * installed. Use the first one.
0576      */
0577     if (!gc->installed)
0578         return NULL;
0579 
0580     virq = irq_find_mapping(gc->domain, gc->irq_base + __ffs(gc->installed));
0581     return virq ? irq_get_irq_data(virq) : NULL;
0582 }
0583 
0584 #ifdef CONFIG_PM
0585 static int irq_gc_suspend(void)
0586 {
0587     struct irq_chip_generic *gc;
0588 
0589     list_for_each_entry(gc, &gc_list, list) {
0590         struct irq_chip_type *ct = gc->chip_types;
0591 
0592         if (ct->chip.irq_suspend) {
0593             struct irq_data *data = irq_gc_get_irq_data(gc);
0594 
0595             if (data)
0596                 ct->chip.irq_suspend(data);
0597         }
0598 
0599         if (gc->suspend)
0600             gc->suspend(gc);
0601     }
0602     return 0;
0603 }
0604 
0605 static void irq_gc_resume(void)
0606 {
0607     struct irq_chip_generic *gc;
0608 
0609     list_for_each_entry(gc, &gc_list, list) {
0610         struct irq_chip_type *ct = gc->chip_types;
0611 
0612         if (gc->resume)
0613             gc->resume(gc);
0614 
0615         if (ct->chip.irq_resume) {
0616             struct irq_data *data = irq_gc_get_irq_data(gc);
0617 
0618             if (data)
0619                 ct->chip.irq_resume(data);
0620         }
0621     }
0622 }
0623 #else
0624 #define irq_gc_suspend NULL
0625 #define irq_gc_resume NULL
0626 #endif
0627 
0628 static void irq_gc_shutdown(void)
0629 {
0630     struct irq_chip_generic *gc;
0631 
0632     list_for_each_entry(gc, &gc_list, list) {
0633         struct irq_chip_type *ct = gc->chip_types;
0634 
0635         if (ct->chip.irq_pm_shutdown) {
0636             struct irq_data *data = irq_gc_get_irq_data(gc);
0637 
0638             if (data)
0639                 ct->chip.irq_pm_shutdown(data);
0640         }
0641     }
0642 }
0643 
0644 static struct syscore_ops irq_gc_syscore_ops = {
0645     .suspend = irq_gc_suspend,
0646     .resume = irq_gc_resume,
0647     .shutdown = irq_gc_shutdown,
0648 };
0649 
0650 static int __init irq_gc_init_ops(void)
0651 {
0652     register_syscore_ops(&irq_gc_syscore_ops);
0653     return 0;
0654 }
0655 device_initcall(irq_gc_init_ops);
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