kernel/dma/direct.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2018-2020 Christoph Hellwig.
0004  *
0005  * DMA operations that map physical memory directly without using an IOMMU.
0006  */
0007 #include <linux/memblock.h> /* for max_pfn */
0008 #include <linux/export.h>
0009 #include <linux/mm.h>
0010 #include <linux/dma-map-ops.h>
0011 #include <linux/scatterlist.h>
0012 #include <linux/pfn.h>
0013 #include <linux/vmalloc.h>
0014 #include <linux/set_memory.h>
0015 #include <linux/slab.h>
0016 #include "direct.h"
0017
0018 /*
0019  * Most architectures use ZONE_DMA for the first 16 Megabytes, but some use
0020  * it for entirely different regions. In that case the arch code needs to
0021  * override the variable below for dma-direct to work properly.
0022  */
0023 unsigned int zone_dma_bits __ro_after_init = 24;
0024
0025 static inline dma_addr_t phys_to_dma_direct(struct device *dev,
0026         phys_addr_t phys)
0027 {
0028     if (force_dma_unencrypted(dev))
0029         return phys_to_dma_unencrypted(dev, phys);
0030     return phys_to_dma(dev, phys);
0031 }
0032
0033 static inline struct page *dma_direct_to_page(struct device *dev,
0034         dma_addr_t dma_addr)
0035 {
0036     return pfn_to_page(PHYS_PFN(dma_to_phys(dev, dma_addr)));
0037 }
0038
0039 u64 dma_direct_get_required_mask(struct device *dev)
0040 {
0041     phys_addr_t phys = (phys_addr_t)(max_pfn - 1) << PAGE_SHIFT;
0042     u64 max_dma = phys_to_dma_direct(dev, phys);
0043
0044     return (1ULL << (fls64(max_dma) - 1)) * 2 - 1;
0045 }
0046
0047 static gfp_t dma_direct_optimal_gfp_mask(struct device *dev, u64 dma_mask,
0048                   u64 *phys_limit)
0049 {
0050     u64 dma_limit = min_not_zero(dma_mask, dev->bus_dma_limit);
0051
0052     /*
0053      * Optimistically try the zone that the physical address mask falls
0054      * into first.  If that returns memory that isn't actually addressable
0055      * we will fallback to the next lower zone and try again.
0056      *
0057      * Note that GFP_DMA32 and GFP_DMA are no ops without the corresponding
0058      * zones.
0059      */
0060     *phys_limit = dma_to_phys(dev, dma_limit);
0061     if (*phys_limit <= DMA_BIT_MASK(zone_dma_bits))
0062         return GFP_DMA;
0063     if (*phys_limit <= DMA_BIT_MASK(32))
0064         return GFP_DMA32;
0065     return 0;
0066 }
0067
0068 static bool dma_coherent_ok(struct device *dev, phys_addr_t phys, size_t size)
0069 {
0070     dma_addr_t dma_addr = phys_to_dma_direct(dev, phys);
0071
0072     if (dma_addr == DMA_MAPPING_ERROR)
0073         return false;
0074     return dma_addr + size - 1 <=
0075         min_not_zero(dev->coherent_dma_mask, dev->bus_dma_limit);
0076 }
0077
0078 static int dma_set_decrypted(struct device *dev, void *vaddr, size_t size)
0079 {
0080     if (!force_dma_unencrypted(dev))
0081         return 0;
0082     return set_memory_decrypted((unsigned long)vaddr, PFN_UP(size));
0083 }
0084
0085 static int dma_set_encrypted(struct device *dev, void *vaddr, size_t size)
0086 {
0087     int ret;
0088
0089     if (!force_dma_unencrypted(dev))
0090         return 0;
0091     ret = set_memory_encrypted((unsigned long)vaddr, PFN_UP(size));
0092     if (ret)
0093         pr_warn_ratelimited("leaking DMA memory that can't be re-encrypted\n");
0094     return ret;
0095 }
0096
0097 static void __dma_direct_free_pages(struct device *dev, struct page *page,
0098                     size_t size)
0099 {
0100     if (swiotlb_free(dev, page, size))
0101         return;
0102     dma_free_contiguous(dev, page, size);
0103 }
0104
0105 static struct page *dma_direct_alloc_swiotlb(struct device *dev, size_t size)
0106 {
0107     struct page *page = swiotlb_alloc(dev, size);
0108
0109     if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
0110         swiotlb_free(dev, page, size);
0111         return NULL;
0112     }
0113
0114     return page;
0115 }
0116
0117 static struct page *__dma_direct_alloc_pages(struct device *dev, size_t size,
0118         gfp_t gfp, bool allow_highmem)
0119 {
0120     int node = dev_to_node(dev);
0121     struct page *page = NULL;
0122     u64 phys_limit;
0123
0124     WARN_ON_ONCE(!PAGE_ALIGNED(size));
0125
0126     if (is_swiotlb_for_alloc(dev))
0127         return dma_direct_alloc_swiotlb(dev, size);
0128
0129     gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
0130                        &phys_limit);
0131     page = dma_alloc_contiguous(dev, size, gfp);
0132     if (page) {
0133         if (!dma_coherent_ok(dev, page_to_phys(page), size) ||
0134             (!allow_highmem && PageHighMem(page))) {
0135             dma_free_contiguous(dev, page, size);
0136             page = NULL;
0137         }
0138     }
0139 again:
0140     if (!page)
0141         page = alloc_pages_node(node, gfp, get_order(size));
0142     if (page && !dma_coherent_ok(dev, page_to_phys(page), size)) {
0143         dma_free_contiguous(dev, page, size);
0144         page = NULL;
0145
0146         if (IS_ENABLED(CONFIG_ZONE_DMA32) &&
0147             phys_limit < DMA_BIT_MASK(64) &&
0148             !(gfp & (GFP_DMA32 | GFP_DMA))) {
0149             gfp |= GFP_DMA32;
0150             goto again;
0151         }
0152
0153         if (IS_ENABLED(CONFIG_ZONE_DMA) && !(gfp & GFP_DMA)) {
0154             gfp = (gfp & ~GFP_DMA32) | GFP_DMA;
0155             goto again;
0156         }
0157     }
0158
0159     return page;
0160 }
0161
0162 /*
0163  * Check if a potentially blocking operations needs to dip into the atomic
0164  * pools for the given device/gfp.
0165  */
0166 static bool dma_direct_use_pool(struct device *dev, gfp_t gfp)
0167 {
0168     return !gfpflags_allow_blocking(gfp) && !is_swiotlb_for_alloc(dev);
0169 }
0170
0171 static void *dma_direct_alloc_from_pool(struct device *dev, size_t size,
0172         dma_addr_t *dma_handle, gfp_t gfp)
0173 {
0174     struct page *page;
0175     u64 phys_mask;
0176     void *ret;
0177
0178     if (WARN_ON_ONCE(!IS_ENABLED(CONFIG_DMA_COHERENT_POOL)))
0179         return NULL;
0180
0181     gfp |= dma_direct_optimal_gfp_mask(dev, dev->coherent_dma_mask,
0182                        &phys_mask);
0183     page = dma_alloc_from_pool(dev, size, &ret, gfp, dma_coherent_ok);
0184     if (!page)
0185         return NULL;
0186     *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
0187     return ret;
0188 }
0189
0190 static void *dma_direct_alloc_no_mapping(struct device *dev, size_t size,
0191         dma_addr_t *dma_handle, gfp_t gfp)
0192 {
0193     struct page *page;
0194
0195     page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
0196     if (!page)
0197         return NULL;
0198
0199     /* remove any dirty cache lines on the kernel alias */
0200     if (!PageHighMem(page))
0201         arch_dma_prep_coherent(page, size);
0202
0203     /* return the page pointer as the opaque cookie */
0204     *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
0205     return page;
0206 }
0207
0208 void *dma_direct_alloc(struct device *dev, size_t size,
0209         dma_addr_t *dma_handle, gfp_t gfp, unsigned long attrs)
0210 {
0211     bool remap = false, set_uncached = false;
0212     struct page *page;
0213     void *ret;
0214
0215     size = PAGE_ALIGN(size);
0216     if (attrs & DMA_ATTR_NO_WARN)
0217         gfp |= __GFP_NOWARN;
0218
0219     if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
0220         !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev))
0221         return dma_direct_alloc_no_mapping(dev, size, dma_handle, gfp);
0222
0223     if (!dev_is_dma_coherent(dev)) {
0224         /*
0225          * Fallback to the arch handler if it exists.  This should
0226          * eventually go away.
0227          */
0228         if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
0229             !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
0230             !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
0231             !is_swiotlb_for_alloc(dev))
0232             return arch_dma_alloc(dev, size, dma_handle, gfp,
0233                           attrs);
0234
0235         /*
0236          * If there is a global pool, always allocate from it for
0237          * non-coherent devices.
0238          */
0239         if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL))
0240             return dma_alloc_from_global_coherent(dev, size,
0241                     dma_handle);
0242
0243         /*
0244          * Otherwise remap if the architecture is asking for it.  But
0245          * given that remapping memory is a blocking operation we'll
0246          * instead have to dip into the atomic pools.
0247          */
0248         remap = IS_ENABLED(CONFIG_DMA_DIRECT_REMAP);
0249         if (remap) {
0250             if (dma_direct_use_pool(dev, gfp))
0251                 return dma_direct_alloc_from_pool(dev, size,
0252                         dma_handle, gfp);
0253         } else {
0254             if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED))
0255                 return NULL;
0256             set_uncached = true;
0257         }
0258     }
0259
0260     /*
0261      * Decrypting memory may block, so allocate the memory from the atomic
0262      * pools if we can't block.
0263      */
0264     if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
0265         return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
0266
0267     /* we always manually zero the memory once we are done */
0268     page = __dma_direct_alloc_pages(dev, size, gfp & ~__GFP_ZERO, true);
0269     if (!page)
0270         return NULL;
0271
0272     /*
0273      * dma_alloc_contiguous can return highmem pages depending on a
0274      * combination the cma= arguments and per-arch setup.  These need to be
0275      * remapped to return a kernel virtual address.
0276      */
0277     if (PageHighMem(page)) {
0278         remap = true;
0279         set_uncached = false;
0280     }
0281
0282     if (remap) {
0283         pgprot_t prot = dma_pgprot(dev, PAGE_KERNEL, attrs);
0284
0285         if (force_dma_unencrypted(dev))
0286             prot = pgprot_decrypted(prot);
0287
0288         /* remove any dirty cache lines on the kernel alias */
0289         arch_dma_prep_coherent(page, size);
0290
0291         /* create a coherent mapping */
0292         ret = dma_common_contiguous_remap(page, size, prot,
0293                 __builtin_return_address(0));
0294         if (!ret)
0295             goto out_free_pages;
0296     } else {
0297         ret = page_address(page);
0298         if (dma_set_decrypted(dev, ret, size))
0299             goto out_free_pages;
0300     }
0301
0302     memset(ret, 0, size);
0303
0304     if (set_uncached) {
0305         arch_dma_prep_coherent(page, size);
0306         ret = arch_dma_set_uncached(ret, size);
0307         if (IS_ERR(ret))
0308             goto out_encrypt_pages;
0309     }
0310
0311     *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
0312     return ret;
0313
0314 out_encrypt_pages:
0315     if (dma_set_encrypted(dev, page_address(page), size))
0316         return NULL;
0317 out_free_pages:
0318     __dma_direct_free_pages(dev, page, size);
0319     return NULL;
0320 }
0321
0322 void dma_direct_free(struct device *dev, size_t size,
0323         void *cpu_addr, dma_addr_t dma_addr, unsigned long attrs)
0324 {
0325     unsigned int page_order = get_order(size);
0326
0327     if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) &&
0328         !force_dma_unencrypted(dev) && !is_swiotlb_for_alloc(dev)) {
0329         /* cpu_addr is a struct page cookie, not a kernel address */
0330         dma_free_contiguous(dev, cpu_addr, size);
0331         return;
0332     }
0333
0334     if (!IS_ENABLED(CONFIG_ARCH_HAS_DMA_SET_UNCACHED) &&
0335         !IS_ENABLED(CONFIG_DMA_DIRECT_REMAP) &&
0336         !IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
0337         !dev_is_dma_coherent(dev) &&
0338         !is_swiotlb_for_alloc(dev)) {
0339         arch_dma_free(dev, size, cpu_addr, dma_addr, attrs);
0340         return;
0341     }
0342
0343     if (IS_ENABLED(CONFIG_DMA_GLOBAL_POOL) &&
0344         !dev_is_dma_coherent(dev)) {
0345         if (!dma_release_from_global_coherent(page_order, cpu_addr))
0346             WARN_ON_ONCE(1);
0347         return;
0348     }
0349
0350     /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
0351     if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
0352         dma_free_from_pool(dev, cpu_addr, PAGE_ALIGN(size)))
0353         return;
0354
0355     if (is_vmalloc_addr(cpu_addr)) {
0356         vunmap(cpu_addr);
0357     } else {
0358         if (IS_ENABLED(CONFIG_ARCH_HAS_DMA_CLEAR_UNCACHED))
0359             arch_dma_clear_uncached(cpu_addr, size);
0360         if (dma_set_encrypted(dev, cpu_addr, size))
0361             return;
0362     }
0363
0364     __dma_direct_free_pages(dev, dma_direct_to_page(dev, dma_addr), size);
0365 }
0366
0367 struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
0368         dma_addr_t *dma_handle, enum dma_data_direction dir, gfp_t gfp)
0369 {
0370     struct page *page;
0371     void *ret;
0372
0373     if (force_dma_unencrypted(dev) && dma_direct_use_pool(dev, gfp))
0374         return dma_direct_alloc_from_pool(dev, size, dma_handle, gfp);
0375
0376     page = __dma_direct_alloc_pages(dev, size, gfp, false);
0377     if (!page)
0378         return NULL;
0379
0380     ret = page_address(page);
0381     if (dma_set_decrypted(dev, ret, size))
0382         goto out_free_pages;
0383     memset(ret, 0, size);
0384     *dma_handle = phys_to_dma_direct(dev, page_to_phys(page));
0385     return page;
0386 out_free_pages:
0387     __dma_direct_free_pages(dev, page, size);
0388     return NULL;
0389 }
0390
0391 void dma_direct_free_pages(struct device *dev, size_t size,
0392         struct page *page, dma_addr_t dma_addr,
0393         enum dma_data_direction dir)
0394 {
0395     void *vaddr = page_address(page);
0396
0397     /* If cpu_addr is not from an atomic pool, dma_free_from_pool() fails */
0398     if (IS_ENABLED(CONFIG_DMA_COHERENT_POOL) &&
0399         dma_free_from_pool(dev, vaddr, size))
0400         return;
0401
0402     if (dma_set_encrypted(dev, vaddr, size))
0403         return;
0404     __dma_direct_free_pages(dev, page, size);
0405 }
0406
0407 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_DEVICE) || \
0408     defined(CONFIG_SWIOTLB)
0409 void dma_direct_sync_sg_for_device(struct device *dev,
0410         struct scatterlist *sgl, int nents, enum dma_data_direction dir)
0411 {
0412     struct scatterlist *sg;
0413     int i;
0414
0415     for_each_sg(sgl, sg, nents, i) {
0416         phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
0417
0418         if (unlikely(is_swiotlb_buffer(dev, paddr)))
0419             swiotlb_sync_single_for_device(dev, paddr, sg->length,
0420                                dir);
0421
0422         if (!dev_is_dma_coherent(dev))
0423             arch_sync_dma_for_device(paddr, sg->length,
0424                     dir);
0425     }
0426 }
0427 #endif
0428
0429 #if defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU) || \
0430     defined(CONFIG_ARCH_HAS_SYNC_DMA_FOR_CPU_ALL) || \
0431     defined(CONFIG_SWIOTLB)
0432 void dma_direct_sync_sg_for_cpu(struct device *dev,
0433         struct scatterlist *sgl, int nents, enum dma_data_direction dir)
0434 {
0435     struct scatterlist *sg;
0436     int i;
0437
0438     for_each_sg(sgl, sg, nents, i) {
0439         phys_addr_t paddr = dma_to_phys(dev, sg_dma_address(sg));
0440
0441         if (!dev_is_dma_coherent(dev))
0442             arch_sync_dma_for_cpu(paddr, sg->length, dir);
0443
0444         if (unlikely(is_swiotlb_buffer(dev, paddr)))
0445             swiotlb_sync_single_for_cpu(dev, paddr, sg->length,
0446                             dir);
0447
0448         if (dir == DMA_FROM_DEVICE)
0449             arch_dma_mark_clean(paddr, sg->length);
0450     }
0451
0452     if (!dev_is_dma_coherent(dev))
0453         arch_sync_dma_for_cpu_all();
0454 }
0455
0456 /*
0457  * Unmaps segments, except for ones marked as pci_p2pdma which do not
0458  * require any further action as they contain a bus address.
0459  */
0460 void dma_direct_unmap_sg(struct device *dev, struct scatterlist *sgl,
0461         int nents, enum dma_data_direction dir, unsigned long attrs)
0462 {
0463     struct scatterlist *sg;
0464     int i;
0465
0466     for_each_sg(sgl,  sg, nents, i) {
0467         if (sg_is_dma_bus_address(sg))
0468             sg_dma_unmark_bus_address(sg);
0469         else
0470             dma_direct_unmap_page(dev, sg->dma_address,
0471                           sg_dma_len(sg), dir, attrs);
0472     }
0473 }
0474 #endif
0475
0476 int dma_direct_map_sg(struct device *dev, struct scatterlist *sgl, int nents,
0477         enum dma_data_direction dir, unsigned long attrs)
0478 {
0479     struct pci_p2pdma_map_state p2pdma_state = {};
0480     enum pci_p2pdma_map_type map;
0481     struct scatterlist *sg;
0482     int i, ret;
0483
0484     for_each_sg(sgl, sg, nents, i) {
0485         if (is_pci_p2pdma_page(sg_page(sg))) {
0486             map = pci_p2pdma_map_segment(&p2pdma_state, dev, sg);
0487             switch (map) {
0488             case PCI_P2PDMA_MAP_BUS_ADDR:
0489                 continue;
0490             case PCI_P2PDMA_MAP_THRU_HOST_BRIDGE:
0491                 /*
0492                  * Any P2P mapping that traverses the PCI
0493                  * host bridge must be mapped with CPU physical
0494                  * address and not PCI bus addresses. This is
0495                  * done with dma_direct_map_page() below.
0496                  */
0497                 break;
0498             default:
0499                 ret = -EREMOTEIO;
0500                 goto out_unmap;
0501             }
0502         }
0503
0504         sg->dma_address = dma_direct_map_page(dev, sg_page(sg),
0505                 sg->offset, sg->length, dir, attrs);
0506         if (sg->dma_address == DMA_MAPPING_ERROR) {
0507             ret = -EIO;
0508             goto out_unmap;
0509         }
0510         sg_dma_len(sg) = sg->length;
0511     }
0512
0513     return nents;
0514
0515 out_unmap:
0516     dma_direct_unmap_sg(dev, sgl, i, dir, attrs | DMA_ATTR_SKIP_CPU_SYNC);
0517     return ret;
0518 }
0519
0520 dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
0521         size_t size, enum dma_data_direction dir, unsigned long attrs)
0522 {
0523     dma_addr_t dma_addr = paddr;
0524
0525     if (unlikely(!dma_capable(dev, dma_addr, size, false))) {
0526         dev_err_once(dev,
0527                  "DMA addr %pad+%zu overflow (mask %llx, bus limit %llx).\n",
0528                  &dma_addr, size, *dev->dma_mask, dev->bus_dma_limit);
0529         WARN_ON_ONCE(1);
0530         return DMA_MAPPING_ERROR;
0531     }
0532
0533     return dma_addr;
0534 }
0535
0536 int dma_direct_get_sgtable(struct device *dev, struct sg_table *sgt,
0537         void *cpu_addr, dma_addr_t dma_addr, size_t size,
0538         unsigned long attrs)
0539 {
0540     struct page *page = dma_direct_to_page(dev, dma_addr);
0541     int ret;
0542
0543     ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
0544     if (!ret)
0545         sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
0546     return ret;
0547 }
0548
0549 bool dma_direct_can_mmap(struct device *dev)
0550 {
0551     return dev_is_dma_coherent(dev) ||
0552         IS_ENABLED(CONFIG_DMA_NONCOHERENT_MMAP);
0553 }
0554
0555 int dma_direct_mmap(struct device *dev, struct vm_area_struct *vma,
0556         void *cpu_addr, dma_addr_t dma_addr, size_t size,
0557         unsigned long attrs)
0558 {
0559     unsigned long user_count = vma_pages(vma);
0560     unsigned long count = PAGE_ALIGN(size) >> PAGE_SHIFT;
0561     unsigned long pfn = PHYS_PFN(dma_to_phys(dev, dma_addr));
0562     int ret = -ENXIO;
0563
0564     vma->vm_page_prot = dma_pgprot(dev, vma->vm_page_prot, attrs);
0565     if (force_dma_unencrypted(dev))
0566         vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot);
0567
0568     if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret))
0569         return ret;
0570     if (dma_mmap_from_global_coherent(vma, cpu_addr, size, &ret))
0571         return ret;
0572
0573     if (vma->vm_pgoff >= count || user_count > count - vma->vm_pgoff)
0574         return -ENXIO;
0575     return remap_pfn_range(vma, vma->vm_start, pfn + vma->vm_pgoff,
0576             user_count << PAGE_SHIFT, vma->vm_page_prot);
0577 }
0578
0579 int dma_direct_supported(struct device *dev, u64 mask)
0580 {
0581     u64 min_mask = (max_pfn - 1) << PAGE_SHIFT;
0582
0583     /*
0584      * Because 32-bit DMA masks are so common we expect every architecture
0585      * to be able to satisfy them - either by not supporting more physical
0586      * memory, or by providing a ZONE_DMA32.  If neither is the case, the
0587      * architecture needs to use an IOMMU instead of the direct mapping.
0588      */
0589     if (mask >= DMA_BIT_MASK(32))
0590         return 1;
0591
0592     /*
0593      * This check needs to be against the actual bit mask value, so use
0594      * phys_to_dma_unencrypted() here so that the SME encryption mask isn't
0595      * part of the check.
0596      */
0597     if (IS_ENABLED(CONFIG_ZONE_DMA))
0598         min_mask = min_t(u64, min_mask, DMA_BIT_MASK(zone_dma_bits));
0599     return mask >= phys_to_dma_unencrypted(dev, min_mask);
0600 }
0601
0602 size_t dma_direct_max_mapping_size(struct device *dev)
0603 {
0604     /* If SWIOTLB is active, use its maximum mapping size */
0605     if (is_swiotlb_active(dev) &&
0606         (dma_addressing_limited(dev) || is_swiotlb_force_bounce(dev)))
0607         return swiotlb_max_mapping_size(dev);
0608     return SIZE_MAX;
0609 }
0610
0611 bool dma_direct_need_sync(struct device *dev, dma_addr_t dma_addr)
0612 {
0613     return !dev_is_dma_coherent(dev) ||
0614            is_swiotlb_buffer(dev, dma_to_phys(dev, dma_addr));
0615 }
0616
0617 /**
0618  * dma_direct_set_offset - Assign scalar offset for a single DMA range.
0619  * @dev:    device pointer; needed to "own" the alloced memory.
0620  * @cpu_start:  beginning of memory region covered by this offset.
0621  * @dma_start:  beginning of DMA/PCI region covered by this offset.
0622  * @size:   size of the region.
0623  *
0624  * This is for the simple case of a uniform offset which cannot
0625  * be discovered by "dma-ranges".
0626  *
0627  * It returns -ENOMEM if out of memory, -EINVAL if a map
0628  * already exists, 0 otherwise.
0629  *
0630  * Note: any call to this from a driver is a bug.  The mapping needs
0631  * to be described by the device tree or other firmware interfaces.
0632  */
0633 int dma_direct_set_offset(struct device *dev, phys_addr_t cpu_start,
0634              dma_addr_t dma_start, u64 size)
0635 {
0636     struct bus_dma_region *map;
0637     u64 offset = (u64)cpu_start - (u64)dma_start;
0638
0639     if (dev->dma_range_map) {
0640         dev_err(dev, "attempt to add DMA range to existing map\n");
0641         return -EINVAL;
0642     }
0643
0644     if (!offset)
0645         return 0;
0646
0647     map = kcalloc(2, sizeof(*map), GFP_KERNEL);
0648     if (!map)
0649         return -ENOMEM;
0650     map[0].cpu_start = cpu_start;
0651     map[0].dma_start = dma_start;
0652     map[0].offset = offset;
0653     map[0].size = size;
0654     dev->dma_range_map = map;
0655     return 0;
0656 }