interface/hvm/hvm_vcpu.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright (c) 2015, Roger Pau Monne <roger.pau@citrix.com>
0004  */
0005
0006 #ifndef __XEN_PUBLIC_HVM_HVM_VCPU_H__
0007 #define __XEN_PUBLIC_HVM_HVM_VCPU_H__
0008
0009 #include "../xen.h"
0010
0011 struct vcpu_hvm_x86_32 {
0012     uint32_t eax;
0013     uint32_t ecx;
0014     uint32_t edx;
0015     uint32_t ebx;
0016     uint32_t esp;
0017     uint32_t ebp;
0018     uint32_t esi;
0019     uint32_t edi;
0020     uint32_t eip;
0021     uint32_t eflags;
0022
0023     uint32_t cr0;
0024     uint32_t cr3;
0025     uint32_t cr4;
0026
0027     uint32_t pad1;
0028
0029     /*
0030      * EFER should only be used to set the NXE bit (if required)
0031      * when starting a vCPU in 32bit mode with paging enabled or
0032      * to set the LME/LMA bits in order to start the vCPU in
0033      * compatibility mode.
0034      */
0035     uint64_t efer;
0036
0037     uint32_t cs_base;
0038     uint32_t ds_base;
0039     uint32_t ss_base;
0040     uint32_t es_base;
0041     uint32_t tr_base;
0042     uint32_t cs_limit;
0043     uint32_t ds_limit;
0044     uint32_t ss_limit;
0045     uint32_t es_limit;
0046     uint32_t tr_limit;
0047     uint16_t cs_ar;
0048     uint16_t ds_ar;
0049     uint16_t ss_ar;
0050     uint16_t es_ar;
0051     uint16_t tr_ar;
0052
0053     uint16_t pad2[3];
0054 };
0055
0056 /*
0057  * The layout of the _ar fields of the segment registers is the
0058  * following:
0059  *
0060  * Bits   [0,3]: type (bits 40-43).
0061  * Bit        4: s    (descriptor type, bit 44).
0062  * Bit    [5,6]: dpl  (descriptor privilege level, bits 45-46).
0063  * Bit        7: p    (segment-present, bit 47).
0064  * Bit        8: avl  (available for system software, bit 52).
0065  * Bit        9: l    (64-bit code segment, bit 53).
0066  * Bit       10: db   (meaning depends on the segment, bit 54).
0067  * Bit       11: g    (granularity, bit 55)
0068  * Bits [12,15]: unused, must be blank.
0069  *
0070  * A more complete description of the meaning of this fields can be
0071  * obtained from the Intel SDM, Volume 3, section 3.4.5.
0072  */
0073
0074 struct vcpu_hvm_x86_64 {
0075     uint64_t rax;
0076     uint64_t rcx;
0077     uint64_t rdx;
0078     uint64_t rbx;
0079     uint64_t rsp;
0080     uint64_t rbp;
0081     uint64_t rsi;
0082     uint64_t rdi;
0083     uint64_t rip;
0084     uint64_t rflags;
0085
0086     uint64_t cr0;
0087     uint64_t cr3;
0088     uint64_t cr4;
0089     uint64_t efer;
0090
0091     /*
0092      * Using VCPU_HVM_MODE_64B implies that the vCPU is launched
0093      * directly in long mode, so the cached parts of the segment
0094      * registers get set to match that environment.
0095      *
0096      * If the user wants to launch the vCPU in compatibility mode
0097      * the 32-bit structure should be used instead.
0098      */
0099 };
0100
0101 struct vcpu_hvm_context {
0102 #define VCPU_HVM_MODE_32B 0  /* 32bit fields of the structure will be used. */
0103 #define VCPU_HVM_MODE_64B 1  /* 64bit fields of the structure will be used. */
0104     uint32_t mode;
0105
0106     uint32_t pad;
0107
0108     /* CPU registers. */
0109     union {
0110         struct vcpu_hvm_x86_32 x86_32;
0111         struct vcpu_hvm_x86_64 x86_64;
0112     } cpu_regs;
0113 };
0114 typedef struct vcpu_hvm_context vcpu_hvm_context_t;
0115
0116 #endif /* __XEN_PUBLIC_HVM_HVM_VCPU_H__ */