include/video/vga.h

0001 /*
0002  * linux/include/video/vga.h -- standard VGA chipset interaction
0003  *
0004  * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
0005  *
0006  * Copyright history from vga16fb.c:
0007  *  Copyright 1999 Ben Pfaff and Petr Vandrovec
0008  *  Based on VGA info at http://www.osdever.net/FreeVGA/home.htm
0009  *  Based on VESA framebuffer (c) 1998 Gerd Knorr
0010  *
0011  * This file is subject to the terms and conditions of the GNU General
0012  * Public License.  See the file COPYING in the main directory of this
0013  * archive for more details.
0014  *
0015  */
0016
0017 #ifndef __linux_video_vga_h__
0018 #define __linux_video_vga_h__
0019
0020 #include <linux/types.h>
0021 #include <linux/io.h>
0022 #include <asm/vga.h>
0023 #include <asm/byteorder.h>
0024
0025
0026 /* Some of the code below is taken from SVGAlib.  The original,
0027    unmodified copyright notice for that code is below. */
0028 /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen                    */
0029 /*                                                                 */
0030 /* This library is free software; you can redistribute it and/or   */
0031 /* modify it without any restrictions. This library is distributed */
0032 /* in the hope that it will be useful, but without any warranty.   */
0033
0034 /* Multi-chipset support Copyright 1993 Harm Hanemaayer */
0035 /* partially copyrighted (C) 1993 by Hartmut Schirmer */
0036
0037 /* VGA data register ports */
0038 #define VGA_CRT_DC      0x3D5   /* CRT Controller Data Register - color emulation */
0039 #define VGA_CRT_DM      0x3B5   /* CRT Controller Data Register - mono emulation */
0040 #define VGA_ATT_R       0x3C1   /* Attribute Controller Data Read Register */
0041 #define VGA_ATT_W       0x3C0   /* Attribute Controller Data Write Register */
0042 #define VGA_GFX_D       0x3CF   /* Graphics Controller Data Register */
0043 #define VGA_SEQ_D       0x3C5   /* Sequencer Data Register */
0044 #define VGA_MIS_R       0x3CC   /* Misc Output Read Register */
0045 #define VGA_MIS_W       0x3C2   /* Misc Output Write Register */
0046 #define VGA_FTC_R   0x3CA   /* Feature Control Read Register */
0047 #define VGA_IS1_RC      0x3DA   /* Input Status Register 1 - color emulation */
0048 #define VGA_IS1_RM      0x3BA   /* Input Status Register 1 - mono emulation */
0049 #define VGA_PEL_D       0x3C9   /* PEL Data Register */
0050 #define VGA_PEL_MSK     0x3C6   /* PEL mask register */
0051
0052 /* EGA-specific registers */
0053 #define EGA_GFX_E0  0x3CC   /* Graphics enable processor 0 */
0054 #define EGA_GFX_E1  0x3CA   /* Graphics enable processor 1 */
0055
0056 /* VGA index register ports */
0057 #define VGA_CRT_IC      0x3D4   /* CRT Controller Index - color emulation */
0058 #define VGA_CRT_IM      0x3B4   /* CRT Controller Index - mono emulation */
0059 #define VGA_ATT_IW      0x3C0   /* Attribute Controller Index & Data Write Register */
0060 #define VGA_GFX_I       0x3CE   /* Graphics Controller Index */
0061 #define VGA_SEQ_I       0x3C4   /* Sequencer Index */
0062 #define VGA_PEL_IW      0x3C8   /* PEL Write Index */
0063 #define VGA_PEL_IR      0x3C7   /* PEL Read Index */
0064
0065 /* standard VGA indexes max counts */
0066 #define VGA_CRT_C       0x19    /* Number of CRT Controller Registers */
0067 #define VGA_ATT_C       0x15    /* Number of Attribute Controller Registers */
0068 #define VGA_GFX_C       0x09    /* Number of Graphics Controller Registers */
0069 #define VGA_SEQ_C       0x05    /* Number of Sequencer Registers */
0070 #define VGA_MIS_C       0x01    /* Number of Misc Output Register */
0071
0072 /* VGA misc register bit masks */
0073 #define VGA_MIS_COLOR       0x01
0074 #define VGA_MIS_ENB_MEM_ACCESS  0x02
0075 #define VGA_MIS_DCLK_28322_720  0x04
0076 #define VGA_MIS_ENB_PLL_LOAD    (0x04 | 0x08)
0077 #define VGA_MIS_SEL_HIGH_PAGE   0x20
0078
0079 /* VGA CRT controller register indices */
0080 #define VGA_CRTC_H_TOTAL    0
0081 #define VGA_CRTC_H_DISP     1
0082 #define VGA_CRTC_H_BLANK_START  2
0083 #define VGA_CRTC_H_BLANK_END    3
0084 #define VGA_CRTC_H_SYNC_START   4
0085 #define VGA_CRTC_H_SYNC_END 5
0086 #define VGA_CRTC_V_TOTAL    6
0087 #define VGA_CRTC_OVERFLOW   7
0088 #define VGA_CRTC_PRESET_ROW 8
0089 #define VGA_CRTC_MAX_SCAN   9
0090 #define VGA_CRTC_CURSOR_START   0x0A
0091 #define VGA_CRTC_CURSOR_END 0x0B
0092 #define VGA_CRTC_START_HI   0x0C
0093 #define VGA_CRTC_START_LO   0x0D
0094 #define VGA_CRTC_CURSOR_HI  0x0E
0095 #define VGA_CRTC_CURSOR_LO  0x0F
0096 #define VGA_CRTC_V_SYNC_START   0x10
0097 #define VGA_CRTC_V_SYNC_END 0x11
0098 #define VGA_CRTC_V_DISP_END 0x12
0099 #define VGA_CRTC_OFFSET     0x13
0100 #define VGA_CRTC_UNDERLINE  0x14
0101 #define VGA_CRTC_V_BLANK_START  0x15
0102 #define VGA_CRTC_V_BLANK_END    0x16
0103 #define VGA_CRTC_MODE       0x17
0104 #define VGA_CRTC_LINE_COMPARE   0x18
0105 #define VGA_CRTC_REGS       VGA_CRT_C
0106
0107 /* VGA CRT controller bit masks */
0108 #define VGA_CR11_LOCK_CR0_CR7   0x80 /* lock writes to CR0 - CR7 */
0109 #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
0110
0111 /* VGA attribute controller register indices */
0112 #define VGA_ATC_PALETTE0    0x00
0113 #define VGA_ATC_PALETTE1    0x01
0114 #define VGA_ATC_PALETTE2    0x02
0115 #define VGA_ATC_PALETTE3    0x03
0116 #define VGA_ATC_PALETTE4    0x04
0117 #define VGA_ATC_PALETTE5    0x05
0118 #define VGA_ATC_PALETTE6    0x06
0119 #define VGA_ATC_PALETTE7    0x07
0120 #define VGA_ATC_PALETTE8    0x08
0121 #define VGA_ATC_PALETTE9    0x09
0122 #define VGA_ATC_PALETTEA    0x0A
0123 #define VGA_ATC_PALETTEB    0x0B
0124 #define VGA_ATC_PALETTEC    0x0C
0125 #define VGA_ATC_PALETTED    0x0D
0126 #define VGA_ATC_PALETTEE    0x0E
0127 #define VGA_ATC_PALETTEF    0x0F
0128 #define VGA_ATC_MODE        0x10
0129 #define VGA_ATC_OVERSCAN    0x11
0130 #define VGA_ATC_PLANE_ENABLE    0x12
0131 #define VGA_ATC_PEL     0x13
0132 #define VGA_ATC_COLOR_PAGE  0x14
0133
0134 #define VGA_AR_ENABLE_DISPLAY   0x20
0135
0136 /* VGA sequencer register indices */
0137 #define VGA_SEQ_RESET       0x00
0138 #define VGA_SEQ_CLOCK_MODE  0x01
0139 #define VGA_SEQ_PLANE_WRITE 0x02
0140 #define VGA_SEQ_CHARACTER_MAP   0x03
0141 #define VGA_SEQ_MEMORY_MODE 0x04
0142
0143 /* VGA sequencer register bit masks */
0144 #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
0145 #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */
0146 #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */
0147 #define VGA_SR04_EXT_MEM    0x02 /* bit 1: allows complete mem access to 256K */
0148 #define VGA_SR04_SEQ_MODE   0x04 /* bit 2: directs system to use a sequential addressing mode */
0149 #define VGA_SR04_CHN_4M     0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
0150
0151 /* VGA graphics controller register indices */
0152 #define VGA_GFX_SR_VALUE    0x00
0153 #define VGA_GFX_SR_ENABLE   0x01
0154 #define VGA_GFX_COMPARE_VALUE   0x02
0155 #define VGA_GFX_DATA_ROTATE 0x03
0156 #define VGA_GFX_PLANE_READ  0x04
0157 #define VGA_GFX_MODE        0x05
0158 #define VGA_GFX_MISC        0x06
0159 #define VGA_GFX_COMPARE_MASK    0x07
0160 #define VGA_GFX_BIT_MASK    0x08
0161
0162 /* VGA graphics controller bit masks */
0163 #define VGA_GR06_GRAPHICS_MODE  0x01
0164
0165 /* macro for composing an 8-bit VGA register index and value
0166  * into a single 16-bit quantity */
0167 #define VGA_OUT16VAL(v, r)       (((v) << 8) | (r))
0168
0169 /* decide whether we should enable the faster 16-bit VGA register writes */
0170 #ifdef __LITTLE_ENDIAN
0171 #define VGA_OUTW_WRITE
0172 #endif
0173
0174 /* VGA State Save and Restore */
0175 #define VGA_SAVE_FONT0 1  /* save/restore plane 2 fonts   */
0176 #define VGA_SAVE_FONT1 2  /* save/restore plane 3 fonts   */
0177 #define VGA_SAVE_TEXT  4  /* save/restore plane 0/1 fonts */
0178 #define VGA_SAVE_FONTS 7  /* save/restore all fonts   */
0179 #define VGA_SAVE_MODE  8  /* save/restore video mode      */
0180 #define VGA_SAVE_CMAP  16 /* save/restore color map/DAC   */
0181
0182 struct vgastate {
0183     void __iomem *vgabase;  /* mmio base, if supported         */
0184     unsigned long membase;  /* VGA window base, 0 for default - 0xA000 */
0185     __u32 memsize;      /* VGA window size, 0 for default 64K      */
0186     __u32 flags;        /* what state[s] to save (see VGA_SAVE_*)  */
0187     __u32 depth;        /* current fb depth, not important     */
0188     __u32 num_attr;     /* number of att registers, 0 for default  */
0189     __u32 num_crtc;     /* number of crt registers, 0 for default  */
0190     __u32 num_gfx;      /* number of gfx registers, 0 for default  */
0191     __u32 num_seq;      /* number of seq registers, 0 for default  */
0192     void *vidstate;
0193 };
0194
0195 extern int save_vga(struct vgastate *state);
0196 extern int restore_vga(struct vgastate *state);
0197
0198 /*
0199  * generic VGA port read/write
0200  */
0201
0202 static inline unsigned char vga_io_r (unsigned short port)
0203 {
0204     return inb_p(port);
0205 }
0206
0207 static inline void vga_io_w (unsigned short port, unsigned char val)
0208 {
0209     outb_p(val, port);
0210 }
0211
0212 static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
0213                   unsigned char val)
0214 {
0215     outw(VGA_OUT16VAL (val, reg), port);
0216 }
0217
0218 static inline unsigned char vga_mm_r (void __iomem *regbase, unsigned short port)
0219 {
0220     return readb (regbase + port);
0221 }
0222
0223 static inline void vga_mm_w (void __iomem *regbase, unsigned short port, unsigned char val)
0224 {
0225     writeb (val, regbase + port);
0226 }
0227
0228 static inline void vga_mm_w_fast (void __iomem *regbase, unsigned short port,
0229                   unsigned char reg, unsigned char val)
0230 {
0231     writew (VGA_OUT16VAL (val, reg), regbase + port);
0232 }
0233
0234 static inline unsigned char vga_r (void __iomem *regbase, unsigned short port)
0235 {
0236     if (regbase)
0237         return vga_mm_r (regbase, port);
0238     else
0239         return vga_io_r (port);
0240 }
0241
0242 static inline void vga_w (void __iomem *regbase, unsigned short port, unsigned char val)
0243 {
0244     if (regbase)
0245         vga_mm_w (regbase, port, val);
0246     else
0247         vga_io_w (port, val);
0248 }
0249
0250
0251 static inline void vga_w_fast (void __iomem *regbase, unsigned short port,
0252                    unsigned char reg, unsigned char val)
0253 {
0254     if (regbase)
0255         vga_mm_w_fast (regbase, port, reg, val);
0256     else
0257         vga_io_w_fast (port, reg, val);
0258 }
0259
0260
0261 /*
0262  * VGA CRTC register read/write
0263  */
0264
0265 static inline unsigned char vga_rcrt (void __iomem *regbase, unsigned char reg)
0266 {
0267         vga_w (regbase, VGA_CRT_IC, reg);
0268         return vga_r (regbase, VGA_CRT_DC);
0269 }
0270
0271 static inline void vga_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
0272 {
0273 #ifdef VGA_OUTW_WRITE
0274     vga_w_fast (regbase, VGA_CRT_IC, reg, val);
0275 #else
0276         vga_w (regbase, VGA_CRT_IC, reg);
0277         vga_w (regbase, VGA_CRT_DC, val);
0278 #endif /* VGA_OUTW_WRITE */
0279 }
0280
0281 static inline unsigned char vga_io_rcrt (unsigned char reg)
0282 {
0283         vga_io_w (VGA_CRT_IC, reg);
0284         return vga_io_r (VGA_CRT_DC);
0285 }
0286
0287 static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
0288 {
0289 #ifdef VGA_OUTW_WRITE
0290     vga_io_w_fast (VGA_CRT_IC, reg, val);
0291 #else
0292         vga_io_w (VGA_CRT_IC, reg);
0293         vga_io_w (VGA_CRT_DC, val);
0294 #endif /* VGA_OUTW_WRITE */
0295 }
0296
0297 static inline unsigned char vga_mm_rcrt (void __iomem *regbase, unsigned char reg)
0298 {
0299         vga_mm_w (regbase, VGA_CRT_IC, reg);
0300         return vga_mm_r (regbase, VGA_CRT_DC);
0301 }
0302
0303 static inline void vga_mm_wcrt (void __iomem *regbase, unsigned char reg, unsigned char val)
0304 {
0305 #ifdef VGA_OUTW_WRITE
0306     vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
0307 #else
0308         vga_mm_w (regbase, VGA_CRT_IC, reg);
0309         vga_mm_w (regbase, VGA_CRT_DC, val);
0310 #endif /* VGA_OUTW_WRITE */
0311 }
0312
0313
0314 /*
0315  * VGA sequencer register read/write
0316  */
0317
0318 static inline unsigned char vga_rseq (void __iomem *regbase, unsigned char reg)
0319 {
0320         vga_w (regbase, VGA_SEQ_I, reg);
0321         return vga_r (regbase, VGA_SEQ_D);
0322 }
0323
0324 static inline void vga_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
0325 {
0326 #ifdef VGA_OUTW_WRITE
0327     vga_w_fast (regbase, VGA_SEQ_I, reg, val);
0328 #else
0329         vga_w (regbase, VGA_SEQ_I, reg);
0330         vga_w (regbase, VGA_SEQ_D, val);
0331 #endif /* VGA_OUTW_WRITE */
0332 }
0333
0334 static inline unsigned char vga_io_rseq (unsigned char reg)
0335 {
0336         vga_io_w (VGA_SEQ_I, reg);
0337         return vga_io_r (VGA_SEQ_D);
0338 }
0339
0340 static inline void vga_io_wseq (unsigned char reg, unsigned char val)
0341 {
0342 #ifdef VGA_OUTW_WRITE
0343     vga_io_w_fast (VGA_SEQ_I, reg, val);
0344 #else
0345         vga_io_w (VGA_SEQ_I, reg);
0346         vga_io_w (VGA_SEQ_D, val);
0347 #endif /* VGA_OUTW_WRITE */
0348 }
0349
0350 static inline unsigned char vga_mm_rseq (void __iomem *regbase, unsigned char reg)
0351 {
0352         vga_mm_w (regbase, VGA_SEQ_I, reg);
0353         return vga_mm_r (regbase, VGA_SEQ_D);
0354 }
0355
0356 static inline void vga_mm_wseq (void __iomem *regbase, unsigned char reg, unsigned char val)
0357 {
0358 #ifdef VGA_OUTW_WRITE
0359     vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
0360 #else
0361         vga_mm_w (regbase, VGA_SEQ_I, reg);
0362         vga_mm_w (regbase, VGA_SEQ_D, val);
0363 #endif /* VGA_OUTW_WRITE */
0364 }
0365
0366 /*
0367  * VGA graphics controller register read/write
0368  */
0369
0370 static inline unsigned char vga_rgfx (void __iomem *regbase, unsigned char reg)
0371 {
0372         vga_w (regbase, VGA_GFX_I, reg);
0373         return vga_r (regbase, VGA_GFX_D);
0374 }
0375
0376 static inline void vga_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
0377 {
0378 #ifdef VGA_OUTW_WRITE
0379     vga_w_fast (regbase, VGA_GFX_I, reg, val);
0380 #else
0381         vga_w (regbase, VGA_GFX_I, reg);
0382         vga_w (regbase, VGA_GFX_D, val);
0383 #endif /* VGA_OUTW_WRITE */
0384 }
0385
0386 static inline unsigned char vga_io_rgfx (unsigned char reg)
0387 {
0388         vga_io_w (VGA_GFX_I, reg);
0389         return vga_io_r (VGA_GFX_D);
0390 }
0391
0392 static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
0393 {
0394 #ifdef VGA_OUTW_WRITE
0395     vga_io_w_fast (VGA_GFX_I, reg, val);
0396 #else
0397         vga_io_w (VGA_GFX_I, reg);
0398         vga_io_w (VGA_GFX_D, val);
0399 #endif /* VGA_OUTW_WRITE */
0400 }
0401
0402 static inline unsigned char vga_mm_rgfx (void __iomem *regbase, unsigned char reg)
0403 {
0404         vga_mm_w (regbase, VGA_GFX_I, reg);
0405         return vga_mm_r (regbase, VGA_GFX_D);
0406 }
0407
0408 static inline void vga_mm_wgfx (void __iomem *regbase, unsigned char reg, unsigned char val)
0409 {
0410 #ifdef VGA_OUTW_WRITE
0411     vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
0412 #else
0413         vga_mm_w (regbase, VGA_GFX_I, reg);
0414         vga_mm_w (regbase, VGA_GFX_D, val);
0415 #endif /* VGA_OUTW_WRITE */
0416 }
0417
0418
0419 /*
0420  * VGA attribute controller register read/write
0421  */
0422
0423 static inline unsigned char vga_rattr (void __iomem *regbase, unsigned char reg)
0424 {
0425         vga_w (regbase, VGA_ATT_IW, reg);
0426         return vga_r (regbase, VGA_ATT_R);
0427 }
0428
0429 static inline void vga_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
0430 {
0431         vga_w (regbase, VGA_ATT_IW, reg);
0432         vga_w (regbase, VGA_ATT_W, val);
0433 }
0434
0435 static inline unsigned char vga_io_rattr (unsigned char reg)
0436 {
0437         vga_io_w (VGA_ATT_IW, reg);
0438         return vga_io_r (VGA_ATT_R);
0439 }
0440
0441 static inline void vga_io_wattr (unsigned char reg, unsigned char val)
0442 {
0443         vga_io_w (VGA_ATT_IW, reg);
0444         vga_io_w (VGA_ATT_W, val);
0445 }
0446
0447 static inline unsigned char vga_mm_rattr (void __iomem *regbase, unsigned char reg)
0448 {
0449         vga_mm_w (regbase, VGA_ATT_IW, reg);
0450         return vga_mm_r (regbase, VGA_ATT_R);
0451 }
0452
0453 static inline void vga_mm_wattr (void __iomem *regbase, unsigned char reg, unsigned char val)
0454 {
0455         vga_mm_w (regbase, VGA_ATT_IW, reg);
0456         vga_mm_w (regbase, VGA_ATT_W, val);
0457 }
0458
0459 #endif /* __linux_video_vga_h__ */