include/video/sh_mobile_lcdc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __ASM_SH_MOBILE_LCDC_H__
0003 #define __ASM_SH_MOBILE_LCDC_H__
0004
0005 #include <linux/fb.h>
0006
0007 /* Register definitions */
0008 #define _LDDCKR         0x410
0009 #define LDDCKR_ICKSEL_BUS   (0 << 16)
0010 #define LDDCKR_ICKSEL_MIPI  (1 << 16)
0011 #define LDDCKR_ICKSEL_HDMI  (2 << 16)
0012 #define LDDCKR_ICKSEL_EXT   (3 << 16)
0013 #define LDDCKR_ICKSEL_MASK  (7 << 16)
0014 #define LDDCKR_MOSEL        (1 << 6)
0015 #define _LDDCKSTPR      0x414
0016 #define _LDINTR         0x468
0017 #define LDINTR_FE       (1 << 10)
0018 #define LDINTR_VSE      (1 << 9)
0019 #define LDINTR_VEE      (1 << 8)
0020 #define LDINTR_FS       (1 << 2)
0021 #define LDINTR_VSS      (1 << 1)
0022 #define LDINTR_VES      (1 << 0)
0023 #define LDINTR_STATUS_MASK  (0xff << 0)
0024 #define _LDSR           0x46c
0025 #define LDSR_MSS        (1 << 10)
0026 #define LDSR_MRS        (1 << 8)
0027 #define LDSR_AS         (1 << 1)
0028 #define _LDCNT1R        0x470
0029 #define LDCNT1R_DE      (1 << 0)
0030 #define _LDCNT2R        0x474
0031 #define LDCNT2R_BR      (1 << 8)
0032 #define LDCNT2R_MD      (1 << 3)
0033 #define LDCNT2R_SE      (1 << 2)
0034 #define LDCNT2R_ME      (1 << 1)
0035 #define LDCNT2R_DO      (1 << 0)
0036 #define _LDRCNTR        0x478
0037 #define LDRCNTR_SRS     (1 << 17)
0038 #define LDRCNTR_SRC     (1 << 16)
0039 #define LDRCNTR_MRS     (1 << 1)
0040 #define LDRCNTR_MRC     (1 << 0)
0041 #define _LDDDSR         0x47c
0042 #define LDDDSR_LS       (1 << 2)
0043 #define LDDDSR_WS       (1 << 1)
0044 #define LDDDSR_BS       (1 << 0)
0045
0046 #define LDMT1R_VPOL     (1 << 28)
0047 #define LDMT1R_HPOL     (1 << 27)
0048 #define LDMT1R_DWPOL        (1 << 26)
0049 #define LDMT1R_DIPOL        (1 << 25)
0050 #define LDMT1R_DAPOL        (1 << 24)
0051 #define LDMT1R_HSCNT        (1 << 17)
0052 #define LDMT1R_DWCNT        (1 << 16)
0053 #define LDMT1R_IFM      (1 << 12)
0054 #define LDMT1R_MIFTYP_RGB8  (0x0 << 0)
0055 #define LDMT1R_MIFTYP_RGB9  (0x4 << 0)
0056 #define LDMT1R_MIFTYP_RGB12A    (0x5 << 0)
0057 #define LDMT1R_MIFTYP_RGB12B    (0x6 << 0)
0058 #define LDMT1R_MIFTYP_RGB16 (0x7 << 0)
0059 #define LDMT1R_MIFTYP_RGB18 (0xa << 0)
0060 #define LDMT1R_MIFTYP_RGB24 (0xb << 0)
0061 #define LDMT1R_MIFTYP_YCBCR (0xf << 0)
0062 #define LDMT1R_MIFTYP_SYS8A (0x0 << 0)
0063 #define LDMT1R_MIFTYP_SYS8B (0x1 << 0)
0064 #define LDMT1R_MIFTYP_SYS8C (0x2 << 0)
0065 #define LDMT1R_MIFTYP_SYS8D (0x3 << 0)
0066 #define LDMT1R_MIFTYP_SYS9  (0x4 << 0)
0067 #define LDMT1R_MIFTYP_SYS12 (0x5 << 0)
0068 #define LDMT1R_MIFTYP_SYS16A    (0x7 << 0)
0069 #define LDMT1R_MIFTYP_SYS16B    (0x8 << 0)
0070 #define LDMT1R_MIFTYP_SYS16C    (0x9 << 0)
0071 #define LDMT1R_MIFTYP_SYS18 (0xa << 0)
0072 #define LDMT1R_MIFTYP_SYS24 (0xb << 0)
0073 #define LDMT1R_MIFTYP_MASK  (0xf << 0)
0074
0075 #define LDDFR_CF1       (1 << 18)
0076 #define LDDFR_CF0       (1 << 17)
0077 #define LDDFR_CC        (1 << 16)
0078 #define LDDFR_YF_420        (0 << 8)
0079 #define LDDFR_YF_422        (1 << 8)
0080 #define LDDFR_YF_444        (2 << 8)
0081 #define LDDFR_YF_MASK       (3 << 8)
0082 #define LDDFR_PKF_ARGB32    (0x00 << 0)
0083 #define LDDFR_PKF_RGB16     (0x03 << 0)
0084 #define LDDFR_PKF_RGB24     (0x0b << 0)
0085 #define LDDFR_PKF_MASK      (0x1f << 0)
0086
0087 #define LDSM1R_OS       (1 << 0)
0088
0089 #define LDSM2R_OSTRG        (1 << 0)
0090
0091 #define LDPMR_LPS       (3 << 0)
0092
0093 #define _LDDWD0R        0x800
0094 #define LDDWDxR_WDACT       (1 << 28)
0095 #define LDDWDxR_RSW     (1 << 24)
0096 #define _LDDRDR         0x840
0097 #define LDDRDR_RSR      (1 << 24)
0098 #define LDDRDR_DRD_MASK     (0x3ffff << 0)
0099 #define _LDDWAR         0x900
0100 #define LDDWAR_WA       (1 << 0)
0101 #define _LDDRAR         0x904
0102 #define LDDRAR_RA       (1 << 0)
0103
0104 enum {
0105     RGB8    = LDMT1R_MIFTYP_RGB8,   /* 24bpp, 8:8:8 */
0106     RGB9    = LDMT1R_MIFTYP_RGB9,   /* 18bpp, 9:9 */
0107     RGB12A  = LDMT1R_MIFTYP_RGB12A, /* 24bpp, 12:12 */
0108     RGB12B  = LDMT1R_MIFTYP_RGB12B, /* 12bpp */
0109     RGB16   = LDMT1R_MIFTYP_RGB16,  /* 16bpp */
0110     RGB18   = LDMT1R_MIFTYP_RGB18,  /* 18bpp */
0111     RGB24   = LDMT1R_MIFTYP_RGB24,  /* 24bpp */
0112     YUV422  = LDMT1R_MIFTYP_YCBCR,  /* 16bpp */
0113     SYS8A   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8A, /* 24bpp, 8:8:8 */
0114     SYS8B   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8B, /* 18bpp, 8:8:2 */
0115     SYS8C   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8C, /* 18bpp, 2:8:8 */
0116     SYS8D   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS8D, /* 16bpp, 8:8 */
0117     SYS9    = LDMT1R_IFM | LDMT1R_MIFTYP_SYS9,  /* 18bpp, 9:9 */
0118     SYS12   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS12, /* 24bpp, 12:12 */
0119     SYS16A  = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16A,    /* 16bpp */
0120     SYS16B  = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16B,    /* 18bpp, 16:2 */
0121     SYS16C  = LDMT1R_IFM | LDMT1R_MIFTYP_SYS16C,    /* 18bpp, 2:16 */
0122     SYS18   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS18, /* 18bpp */
0123     SYS24   = LDMT1R_IFM | LDMT1R_MIFTYP_SYS24, /* 24bpp */
0124 };
0125
0126 enum { LCDC_CHAN_DISABLED = 0,
0127        LCDC_CHAN_MAINLCD,
0128        LCDC_CHAN_SUBLCD };
0129
0130 enum { LCDC_CLK_BUS, LCDC_CLK_PERIPHERAL, LCDC_CLK_EXTERNAL };
0131
0132 #define LCDC_FLAGS_DWPOL (1 << 0) /* Rising edge dot clock data latch */
0133 #define LCDC_FLAGS_DIPOL (1 << 1) /* Active low display enable polarity */
0134 #define LCDC_FLAGS_DAPOL (1 << 2) /* Active low display data polarity */
0135 #define LCDC_FLAGS_HSCNT (1 << 3) /* Disable HSYNC during VBLANK */
0136 #define LCDC_FLAGS_DWCNT (1 << 4) /* Disable dotclock during blanking */
0137
0138 struct sh_mobile_lcdc_sys_bus_cfg {
0139     unsigned long ldmt2r;
0140     unsigned long ldmt3r;
0141     unsigned long deferred_io_msec;
0142 };
0143
0144 struct sh_mobile_lcdc_sys_bus_ops {
0145     void (*write_index)(void *handle, unsigned long data);
0146     void (*write_data)(void *handle, unsigned long data);
0147     unsigned long (*read_data)(void *handle);
0148 };
0149
0150 struct sh_mobile_lcdc_panel_cfg {
0151     unsigned long width;        /* Panel width in mm */
0152     unsigned long height;       /* Panel height in mm */
0153     int (*setup_sys)(void *sys_ops_handle,
0154              struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
0155     void (*start_transfer)(void *sys_ops_handle,
0156                    struct sh_mobile_lcdc_sys_bus_ops *sys_ops);
0157     void (*display_on)(void);
0158     void (*display_off)(void);
0159 };
0160
0161 /* backlight info */
0162 struct sh_mobile_lcdc_bl_info {
0163     const char *name;
0164     int max_brightness;
0165     int (*set_brightness)(int brightness);
0166 };
0167
0168 struct sh_mobile_lcdc_overlay_cfg {
0169     int fourcc;
0170     unsigned int max_xres;
0171     unsigned int max_yres;
0172 };
0173
0174 struct sh_mobile_lcdc_chan_cfg {
0175     int chan;
0176     int fourcc;
0177     int colorspace;
0178     int interface_type; /* selects RGBn or SYSn I/F, see above */
0179     int clock_divider;
0180     unsigned long flags; /* LCDC_FLAGS_... */
0181     const struct fb_videomode *lcd_modes;
0182     int num_modes;
0183     struct sh_mobile_lcdc_panel_cfg panel_cfg;
0184     struct sh_mobile_lcdc_bl_info bl_info;
0185     struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
0186
0187     struct platform_device *tx_dev; /* HDMI/DSI transmitter device */
0188 };
0189
0190 struct sh_mobile_lcdc_info {
0191     int clock_source;
0192     struct sh_mobile_lcdc_chan_cfg ch[2];
0193     struct sh_mobile_lcdc_overlay_cfg overlays[4];
0194 };
0195
0196 #endif /* __ASM_SH_MOBILE_LCDC_H__ */