include/video/pxa168fb.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Copyright (C) 2009 Marvell International Ltd.
0004  */
0005
0006 #ifndef __ASM_MACH_PXA168FB_H
0007 #define __ASM_MACH_PXA168FB_H
0008
0009 #include <linux/fb.h>
0010 #include <linux/interrupt.h>
0011
0012 /* Dumb interface */
0013 #define PIN_MODE_DUMB_24        0
0014 #define PIN_MODE_DUMB_18_SPI        1
0015 #define PIN_MODE_DUMB_18_GPIO       2
0016 #define PIN_MODE_DUMB_16_SPI        3
0017 #define PIN_MODE_DUMB_16_GPIO       4
0018 #define PIN_MODE_DUMB_12_SPI_GPIO   5
0019 #define PIN_MODE_SMART_18_SPI       6
0020 #define PIN_MODE_SMART_16_SPI       7
0021 #define PIN_MODE_SMART_8_SPI_GPIO   8
0022
0023 /* Dumb interface pin allocation */
0024 #define DUMB_MODE_RGB565        0
0025 #define DUMB_MODE_RGB565_UPPER      1
0026 #define DUMB_MODE_RGB666        2
0027 #define DUMB_MODE_RGB666_UPPER      3
0028 #define DUMB_MODE_RGB444        4
0029 #define DUMB_MODE_RGB444_UPPER      5
0030 #define DUMB_MODE_RGB888        6
0031
0032 /* default fb buffer size WVGA-32bits */
0033 #define DEFAULT_FB_SIZE (800 * 480 * 4)
0034
0035 /*
0036  * Buffer pixel format
0037  * bit0 is for rb swap.
0038  * bit12 is for Y UorV swap
0039  */
0040 #define PIX_FMT_RGB565      0
0041 #define PIX_FMT_BGR565      1
0042 #define PIX_FMT_RGB1555     2
0043 #define PIX_FMT_BGR1555     3
0044 #define PIX_FMT_RGB888PACK  4
0045 #define PIX_FMT_BGR888PACK  5
0046 #define PIX_FMT_RGB888UNPACK    6
0047 #define PIX_FMT_BGR888UNPACK    7
0048 #define PIX_FMT_RGBA888     8
0049 #define PIX_FMT_BGRA888     9
0050 #define PIX_FMT_YUV422PACK  10
0051 #define PIX_FMT_YVU422PACK  11
0052 #define PIX_FMT_YUV422PLANAR    12
0053 #define PIX_FMT_YVU422PLANAR    13
0054 #define PIX_FMT_YUV420PLANAR    14
0055 #define PIX_FMT_YVU420PLANAR    15
0056 #define PIX_FMT_PSEUDOCOLOR 20
0057 #define PIX_FMT_UYVY422PACK (0x1000|PIX_FMT_YUV422PACK)
0058
0059 /*
0060  * PXA LCD controller private state.
0061  */
0062 struct pxa168fb_info {
0063     struct device       *dev;
0064     struct clk      *clk;
0065     struct fb_info      *info;
0066
0067     void __iomem        *reg_base;
0068     dma_addr_t      fb_start_dma;
0069     u32         pseudo_palette[16];
0070
0071     int         pix_fmt;
0072     unsigned        is_blanked:1;
0073     unsigned        panel_rbswap:1;
0074     unsigned        active:1;
0075 };
0076
0077 /*
0078  * PXA fb machine information
0079  */
0080 struct pxa168fb_mach_info {
0081     char    id[16];
0082
0083     int     num_modes;
0084     struct fb_videomode *modes;
0085
0086     /*
0087      * Pix_fmt
0088      */
0089     unsigned    pix_fmt;
0090
0091     /*
0092      * I/O pin allocation.
0093      */
0094     unsigned    io_pin_allocation_mode:4;
0095
0096     /*
0097      * Dumb panel -- assignment of R/G/B component info to the 24
0098      * available external data lanes.
0099      */
0100     unsigned    dumb_mode:4;
0101     unsigned    panel_rgb_reverse_lanes:1;
0102
0103     /*
0104      * Dumb panel -- GPIO output data.
0105      */
0106     unsigned    gpio_output_mask:8;
0107     unsigned    gpio_output_data:8;
0108
0109     /*
0110      * Dumb panel -- configurable output signal polarity.
0111      */
0112     unsigned    invert_composite_blank:1;
0113     unsigned    invert_pix_val_ena:1;
0114     unsigned    invert_pixclock:1;
0115     unsigned    panel_rbswap:1;
0116     unsigned    active:1;
0117     unsigned    enable_lcd:1;
0118 };
0119
0120 #endif /* __ASM_MACH_PXA168FB_H */