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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* $Id: newport.h,v 1.5 1999/08/04 06:01:51 ulfc Exp $
0003  *
0004  * newport.h: Defines and register layout for NEWPORT graphics
0005  *            hardware.
0006  *
0007  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
0008  * 
0009  * Ulf Carlsson - Compatibility with the IRIX structures added
0010  */
0011 
0012 #ifndef _SGI_NEWPORT_H
0013 #define _SGI_NEWPORT_H
0014 
0015 
0016 typedef volatile unsigned int npireg_t;
0017 
0018 union npfloat {
0019     volatile float flt;
0020     npireg_t       word;
0021 };
0022 
0023 typedef union npfloat npfreg_t;
0024 
0025 union np_dcb {
0026     npireg_t byword;
0027     struct { volatile unsigned short s0, s1; } byshort;
0028     struct { volatile unsigned char b0, b1, b2, b3; } bybytes;
0029 };
0030 
0031 struct newport_rexregs {
0032     npireg_t drawmode1;      /* GL extra mode bits */
0033     
0034 #define DM1_PLANES         0x00000007
0035 #define    DM1_NOPLANES    0x00000000
0036 #define    DM1_RGBPLANES   0x00000001
0037 #define    DM1_RGBAPLANES  0x00000002
0038 #define    DM1_OLAYPLANES  0x00000004
0039 #define    DM1_PUPPLANES   0x00000005
0040 #define    DM1_CIDPLANES   0x00000006
0041     
0042 #define NPORT_DMODE1_DDMASK      0x00000018
0043 #define NPORT_DMODE1_DD4         0x00000000
0044 #define NPORT_DMODE1_DD8         0x00000008
0045 #define NPORT_DMODE1_DD12        0x00000010
0046 #define NPORT_DMODE1_DD24        0x00000018
0047 #define NPORT_DMODE1_DSRC        0x00000020
0048 #define NPORT_DMODE1_YFLIP       0x00000040
0049 #define NPORT_DMODE1_RWPCKD      0x00000080
0050 #define NPORT_DMODE1_HDMASK      0x00000300
0051 #define NPORT_DMODE1_HD4         0x00000000
0052 #define NPORT_DMODE1_HD8         0x00000100
0053 #define NPORT_DMODE1_HD12        0x00000200
0054 #define NPORT_DMODE1_HD32        0x00000300
0055 #define NPORT_DMODE1_RWDBL       0x00000400
0056 #define NPORT_DMODE1_ESWAP       0x00000800 /* Endian swap */
0057 #define NPORT_DMODE1_CCMASK      0x00007000
0058 #define NPORT_DMODE1_CCLT        0x00001000
0059 #define NPORT_DMODE1_CCEQ        0x00002000
0060 #define NPORT_DMODE1_CCGT        0x00004000
0061 #define NPORT_DMODE1_RGBMD       0x00008000
0062 #define NPORT_DMODE1_DENAB       0x00010000 /* Dither enable */
0063 #define NPORT_DMODE1_FCLR        0x00020000 /* Fast clear */
0064 #define NPORT_DMODE1_BENAB       0x00040000 /* Blend enable */
0065 #define NPORT_DMODE1_SFMASK      0x00380000
0066 #define NPORT_DMODE1_SF0         0x00000000
0067 #define NPORT_DMODE1_SF1         0x00080000
0068 #define NPORT_DMODE1_SFDC        0x00100000
0069 #define NPORT_DMODE1_SFMDC       0x00180000
0070 #define NPORT_DMODE1_SFSA        0x00200000
0071 #define NPORT_DMODE1_SFMSA       0x00280000
0072 #define NPORT_DMODE1_DFMASK      0x01c00000
0073 #define NPORT_DMODE1_DF0         0x00000000
0074 #define NPORT_DMODE1_DF1         0x00400000
0075 #define NPORT_DMODE1_DFSC        0x00800000
0076 #define NPORT_DMODE1_DFMSC       0x00c00000
0077 #define NPORT_DMODE1_DFSA        0x01000000
0078 #define NPORT_DMODE1_DFMSA       0x01400000
0079 #define NPORT_DMODE1_BBENAB      0x02000000 /* Back blend enable */
0080 #define NPORT_DMODE1_PFENAB      0x04000000 /* Pre-fetch enable */
0081 #define NPORT_DMODE1_ABLEND      0x08000000 /* Alpha blend */
0082 #define NPORT_DMODE1_LOMASK      0xf0000000
0083 #define NPORT_DMODE1_LOZERO      0x00000000
0084 #define NPORT_DMODE1_LOAND       0x10000000
0085 #define NPORT_DMODE1_LOANDR      0x20000000
0086 #define NPORT_DMODE1_LOSRC       0x30000000
0087 #define NPORT_DMODE1_LOANDI      0x40000000
0088 #define NPORT_DMODE1_LODST       0x50000000
0089 #define NPORT_DMODE1_LOXOR       0x60000000
0090 #define NPORT_DMODE1_LOOR        0x70000000
0091 #define NPORT_DMODE1_LONOR       0x80000000
0092 #define NPORT_DMODE1_LOXNOR      0x90000000
0093 #define NPORT_DMODE1_LONDST      0xa0000000
0094 #define NPORT_DMODE1_LOORR       0xb0000000
0095 #define NPORT_DMODE1_LONSRC      0xc0000000
0096 #define NPORT_DMODE1_LOORI       0xd0000000
0097 #define NPORT_DMODE1_LONAND      0xe0000000
0098 #define NPORT_DMODE1_LOONE       0xf0000000
0099 
0100     npireg_t drawmode0;      /* REX command register */
0101 
0102     /* These bits define the graphics opcode being performed. */
0103 #define NPORT_DMODE0_OPMASK   0x00000003 /* Opcode mask */
0104 #define NPORT_DMODE0_NOP      0x00000000 /* No operation */
0105 #define NPORT_DMODE0_RD       0x00000001 /* Read operation */
0106 #define NPORT_DMODE0_DRAW     0x00000002 /* Draw operation */
0107 #define NPORT_DMODE0_S2S      0x00000003 /* Screen to screen operation */
0108 
0109     /* The following decide what addressing mode(s) are to be used */
0110 #define NPORT_DMODE0_AMMASK   0x0000001c /* Address mode mask */
0111 #define NPORT_DMODE0_SPAN     0x00000000 /* Spanning address mode */
0112 #define NPORT_DMODE0_BLOCK    0x00000004 /* Block address mode */
0113 #define NPORT_DMODE0_ILINE    0x00000008 /* Iline address mode */
0114 #define NPORT_DMODE0_FLINE    0x0000000c /* Fline address mode */
0115 #define NPORT_DMODE0_ALINE    0x00000010 /* Aline address mode */
0116 #define NPORT_DMODE0_TLINE    0x00000014 /* Tline address mode */
0117 #define NPORT_DMODE0_BLINE    0x00000018 /* Bline address mode */
0118 
0119     /* And now some misc. operation control bits. */
0120 #define NPORT_DMODE0_DOSETUP  0x00000020
0121 #define NPORT_DMODE0_CHOST    0x00000040
0122 #define NPORT_DMODE0_AHOST    0x00000080
0123 #define NPORT_DMODE0_STOPX    0x00000100
0124 #define NPORT_DMODE0_STOPY    0x00000200
0125 #define NPORT_DMODE0_SK1ST    0x00000400
0126 #define NPORT_DMODE0_SKLST    0x00000800
0127 #define NPORT_DMODE0_ZPENAB   0x00001000
0128 #define NPORT_DMODE0_LISPENAB 0x00002000
0129 #define NPORT_DMODE0_LISLST   0x00004000
0130 #define NPORT_DMODE0_L32      0x00008000
0131 #define NPORT_DMODE0_ZOPQ     0x00010000
0132 #define NPORT_DMODE0_LISOPQ   0x00020000
0133 #define NPORT_DMODE0_SHADE    0x00040000
0134 #define NPORT_DMODE0_LRONLY   0x00080000
0135 #define NPORT_DMODE0_XYOFF    0x00100000
0136 #define NPORT_DMODE0_CLAMP    0x00200000
0137 #define NPORT_DMODE0_ENDPF    0x00400000
0138 #define NPORT_DMODE0_YSTR     0x00800000
0139 
0140     npireg_t lsmode;      /* Mode for line stipple ops */
0141     npireg_t lspattern;   /* Pattern for line stipple ops */
0142     npireg_t lspatsave;   /* Backup save pattern */
0143     npireg_t zpattern;    /* Pixel zpattern */
0144     npireg_t colorback;   /* Background color */
0145     npireg_t colorvram;   /* Clear color for fast vram */
0146     npireg_t alpharef;    /* Reference value for afunctions */
0147     unsigned int pad0;
0148     npireg_t smask0x;     /* Window GL relative screen mask 0 */
0149     npireg_t smask0y;     /* Window GL relative screen mask 0 */
0150     npireg_t _setup;
0151     npireg_t _stepz;
0152     npireg_t _lsrestore;
0153     npireg_t _lssave;
0154 
0155     unsigned int _pad1[0x30];
0156 
0157     /* Iterators, full state for context switch */
0158     npfreg_t _xstart;   /* X-start point (current) */
0159     npfreg_t _ystart;   /* Y-start point (current) */
0160     npfreg_t _xend;     /* x-end point */
0161     npfreg_t _yend;     /* y-end point */
0162     npireg_t xsave;     /* copy of xstart integer value for BLOCk addressing MODE */
0163     npireg_t xymove;    /* x.y offset from xstart, ystart for relative operations */
0164     npfreg_t bresd;
0165     npfreg_t bress1;
0166     npireg_t bresoctinc1;
0167     volatile int bresrndinc2;
0168     npireg_t brese1;
0169     npireg_t bress2;
0170     npireg_t aweight0;
0171     npireg_t aweight1;
0172     npfreg_t xstartf;
0173     npfreg_t ystartf;
0174     npfreg_t xendf;
0175     npfreg_t yendf;
0176     npireg_t xstarti;
0177     npfreg_t xendf1;
0178     npireg_t xystarti;
0179     npireg_t xyendi;
0180     npireg_t xstartendi;
0181 
0182     unsigned int _unused2[0x29];
0183 
0184     npfreg_t colorred;
0185     npfreg_t coloralpha;
0186     npfreg_t colorgrn;
0187     npfreg_t colorblue;
0188     npfreg_t slopered;
0189     npfreg_t slopealpha;
0190     npfreg_t slopegrn;
0191     npfreg_t slopeblue;
0192     npireg_t wrmask;
0193     npireg_t colori;
0194     npfreg_t colorx;
0195     npfreg_t slopered1;
0196     npireg_t hostrw0;
0197     npireg_t hostrw1;
0198     npireg_t dcbmode;
0199 #define NPORT_DMODE_WMASK   0x00000003
0200 #define NPORT_DMODE_W4      0x00000000
0201 #define NPORT_DMODE_W1      0x00000001
0202 #define NPORT_DMODE_W2      0x00000002
0203 #define NPORT_DMODE_W3      0x00000003
0204 #define NPORT_DMODE_EDPACK  0x00000004
0205 #define NPORT_DMODE_ECINC   0x00000008
0206 #define NPORT_DMODE_CMASK   0x00000070
0207 #define NPORT_DMODE_AMASK   0x00000780
0208 #define NPORT_DMODE_AVC2    0x00000000
0209 #define NPORT_DMODE_ACMALL  0x00000080
0210 #define NPORT_DMODE_ACM0    0x00000100
0211 #define NPORT_DMODE_ACM1    0x00000180
0212 #define NPORT_DMODE_AXMALL  0x00000200
0213 #define NPORT_DMODE_AXM0    0x00000280
0214 #define NPORT_DMODE_AXM1    0x00000300
0215 #define NPORT_DMODE_ABT     0x00000380
0216 #define NPORT_DMODE_AVCC1   0x00000400
0217 #define NPORT_DMODE_AVAB1   0x00000480
0218 #define NPORT_DMODE_ALG3V0  0x00000500
0219 #define NPORT_DMODE_A1562   0x00000580
0220 #define NPORT_DMODE_ESACK   0x00000800
0221 #define NPORT_DMODE_EASACK  0x00001000
0222 #define NPORT_DMODE_CWMASK  0x0003e000
0223 #define NPORT_DMODE_CHMASK  0x007c0000
0224 #define NPORT_DMODE_CSMASK  0x0f800000
0225 #define NPORT_DMODE_SENDIAN 0x10000000
0226 
0227     unsigned int _unused3;
0228 
0229     union np_dcb dcbdata0;
0230     npireg_t dcbdata1;
0231 };
0232 
0233 struct newport_cregs {
0234     npireg_t smask1x;
0235     npireg_t smask1y;
0236     npireg_t smask2x;
0237     npireg_t smask2y;
0238     npireg_t smask3x;
0239     npireg_t smask3y;
0240     npireg_t smask4x;
0241     npireg_t smask4y;
0242     npireg_t topscan;
0243     npireg_t xywin;
0244     npireg_t clipmode;
0245 #define NPORT_CMODE_SM0   0x00000001
0246 #define NPORT_CMODE_SM1   0x00000002
0247 #define NPORT_CMODE_SM2   0x00000004
0248 #define NPORT_CMODE_SM3   0x00000008
0249 #define NPORT_CMODE_SM4   0x00000010
0250 #define NPORT_CMODE_CMSK  0x00001e00
0251 
0252     unsigned int _unused0;
0253     unsigned int config;
0254 #define NPORT_CFG_G32MD   0x00000001
0255 #define NPORT_CFG_BWIDTH  0x00000002
0256 #define NPORT_CFG_ERCVR   0x00000004
0257 #define NPORT_CFG_BDMSK   0x00000078
0258 #define NPORT_CFG_BFAINT  0x00000080
0259 #define NPORT_CFG_GDMSK   0x00001f80
0260 #define NPORT_CFG_GD0     0x00000100
0261 #define NPORT_CFG_GD1     0x00000200
0262 #define NPORT_CFG_GD2     0x00000400
0263 #define NPORT_CFG_GD3     0x00000800
0264 #define NPORT_CFG_GD4     0x00001000
0265 #define NPORT_CFG_GFAINT  0x00002000
0266 #define NPORT_CFG_TOMSK   0x0001c000
0267 #define NPORT_CFG_VRMSK   0x000e0000
0268 #define NPORT_CFG_FBTYP   0x00100000
0269 
0270     npireg_t _unused1;
0271     npireg_t status;
0272 #define NPORT_STAT_VERS   0x00000007
0273 #define NPORT_STAT_GBUSY  0x00000008
0274 #define NPORT_STAT_BBUSY  0x00000010
0275 #define NPORT_STAT_VRINT  0x00000020
0276 #define NPORT_STAT_VIDINT 0x00000040
0277 #define NPORT_STAT_GLMSK  0x00001f80
0278 #define NPORT_STAT_BLMSK  0x0007e000
0279 #define NPORT_STAT_BFIRQ  0x00080000
0280 #define NPORT_STAT_GFIRQ  0x00100000
0281 
0282     npireg_t ustatus;
0283     npireg_t dcbreset;
0284 };
0285 
0286 struct newport_regs {
0287     struct newport_rexregs set;
0288     unsigned int _unused0[0x16e];
0289     struct newport_rexregs go;
0290     unsigned int _unused1[0x22e];
0291     struct newport_cregs cset;
0292     unsigned int _unused2[0x1ef];
0293     struct newport_cregs cgo;
0294 };
0295 
0296 typedef struct {
0297     unsigned int drawmode1;
0298     unsigned int drawmode0;
0299     unsigned int lsmode;   
0300     unsigned int lspattern;
0301     unsigned int lspatsave;
0302     unsigned int zpattern; 
0303     unsigned int colorback;
0304     unsigned int colorvram;
0305     unsigned int alpharef; 
0306     unsigned int smask0x;  
0307     unsigned int smask0y;  
0308     unsigned int _xstart;  
0309     unsigned int _ystart;  
0310     unsigned int _xend;    
0311     unsigned int _yend;    
0312     unsigned int xsave;    
0313     unsigned int xymove;   
0314     unsigned int bresd;    
0315     unsigned int bress1;   
0316     unsigned int bresoctinc1;
0317     unsigned int bresrndinc2;
0318     unsigned int brese1;     
0319     unsigned int bress2;     
0320     
0321     unsigned int aweight0;    
0322     unsigned int aweight1;    
0323     unsigned int colorred;    
0324     unsigned int coloralpha;  
0325     unsigned int colorgrn;    
0326     unsigned int colorblue;   
0327     unsigned int slopered;    
0328     unsigned int slopealpha;  
0329     unsigned int slopegrn;    
0330     unsigned int slopeblue;   
0331     unsigned int wrmask;      
0332     unsigned int hostrw0;     
0333     unsigned int hostrw1;     
0334     
0335         /* configregs */
0336     
0337     unsigned int smask1x;    
0338     unsigned int smask1y;    
0339     unsigned int smask2x;    
0340     unsigned int smask2y;    
0341     unsigned int smask3x;    
0342     unsigned int smask3y;    
0343     unsigned int smask4x;    
0344     unsigned int smask4y;    
0345     unsigned int topscan;    
0346     unsigned int xywin;      
0347     unsigned int clipmode;   
0348     unsigned int config;     
0349     
0350         /* dcb registers */
0351     unsigned int dcbmode;   
0352     unsigned int dcbdata0;  
0353     unsigned int dcbdata1;
0354 } newport_ctx;
0355 
0356 /* Reading/writing VC2 registers. */
0357 #define VC2_REGADDR_INDEX      0x00000000
0358 #define VC2_REGADDR_IREG       0x00000010
0359 #define VC2_REGADDR_RAM        0x00000030
0360 #define VC2_PROTOCOL           (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
0361 
0362 #define VC2_VLINET_ADDR        0x000
0363 #define VC2_VFRAMET_ADDR       0x400
0364 #define VC2_CGLYPH_ADDR        0x500
0365 
0366 /* Now the Indexed registers of the VC2. */
0367 #define VC2_IREG_VENTRY        0x00
0368 #define VC2_IREG_CENTRY        0x01
0369 #define VC2_IREG_CURSX         0x02
0370 #define VC2_IREG_CURSY         0x03
0371 #define VC2_IREG_CCURSX        0x04
0372 #define VC2_IREG_DENTRY        0x05
0373 #define VC2_IREG_SLEN          0x06
0374 #define VC2_IREG_RADDR         0x07
0375 #define VC2_IREG_VFPTR         0x08
0376 #define VC2_IREG_VLSPTR        0x09
0377 #define VC2_IREG_VLIR          0x0a
0378 #define VC2_IREG_VLCTR         0x0b
0379 #define VC2_IREG_CTPTR         0x0c
0380 #define VC2_IREG_WCURSY        0x0d
0381 #define VC2_IREG_DFPTR         0x0e
0382 #define VC2_IREG_DLTPTR        0x0f
0383 #define VC2_IREG_CONTROL       0x10
0384 #define VC2_IREG_CONFIG        0x20
0385 
0386 static inline void newport_vc2_set(struct newport_regs *regs,
0387                    unsigned char vc2ireg,
0388                    unsigned short val)
0389 {
0390     regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 |
0391                NPORT_DMODE_ECINC | VC2_PROTOCOL);
0392     regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8);
0393 }
0394 
0395 static inline unsigned short newport_vc2_get(struct newport_regs *regs,
0396                          unsigned char vc2ireg)
0397 {
0398     regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 |
0399                NPORT_DMODE_ECINC | VC2_PROTOCOL);
0400     regs->set.dcbdata0.bybytes.b3 = vc2ireg;
0401     regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 |
0402                NPORT_DMODE_ECINC | VC2_PROTOCOL);
0403     return regs->set.dcbdata0.byshort.s1;
0404 }
0405 
0406 /* VC2 Control register bits */
0407 #define VC2_CTRL_EVIRQ     0x0001
0408 #define VC2_CTRL_EDISP     0x0002
0409 #define VC2_CTRL_EVIDEO    0x0004
0410 #define VC2_CTRL_EDIDS     0x0008
0411 #define VC2_CTRL_ECURS     0x0010
0412 #define VC2_CTRL_EGSYNC    0x0020
0413 #define VC2_CTRL_EILACE    0x0040
0414 #define VC2_CTRL_ECDISP    0x0080
0415 #define VC2_CTRL_ECCURS    0x0100
0416 #define VC2_CTRL_ECG64     0x0200
0417 #define VC2_CTRL_GLSEL     0x0400
0418 
0419 /* Controlling the color map on NEWPORT. */
0420 #define NCMAP_REGADDR_AREG   0x00000000
0421 #define NCMAP_REGADDR_ALO    0x00000000
0422 #define NCMAP_REGADDR_AHI    0x00000010
0423 #define NCMAP_REGADDR_PBUF   0x00000020
0424 #define NCMAP_REGADDR_CREG   0x00000030
0425 #define NCMAP_REGADDR_SREG   0x00000040
0426 #define NCMAP_REGADDR_RREG   0x00000060
0427 #define NCMAP_PROTOCOL       (0x00008000 | 0x00040000 | 0x00800000)
0428 
0429 static __inline__ void newport_cmap_setaddr(struct newport_regs *regs,
0430                     unsigned short addr)
0431 {
0432     regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
0433                NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC |
0434                NCMAP_REGADDR_AREG | NPORT_DMODE_W2);
0435     regs->set.dcbdata0.byshort.s1 = addr;
0436     regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
0437                NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);
0438 }
0439 
0440 static __inline__ void newport_cmap_setrgb(struct newport_regs *regs,
0441                        unsigned char red,
0442                        unsigned char green,
0443                        unsigned char blue)
0444 {
0445     regs->set.dcbdata0.byword =
0446         (red << 24) |
0447         (green << 16) |
0448         (blue << 8);
0449 }
0450 
0451 /* Miscellaneous NEWPORT routines. */
0452 #define BUSY_TIMEOUT 100000
0453 static __inline__ int newport_wait(struct newport_regs *regs)
0454 {
0455     int t = BUSY_TIMEOUT;
0456 
0457     while (--t)
0458         if (!(regs->cset.status & NPORT_STAT_GBUSY))
0459             break;
0460     return !t;
0461 }
0462 
0463 static __inline__ int newport_bfwait(struct newport_regs *regs)
0464 {
0465     int t = BUSY_TIMEOUT;
0466 
0467     while (--t)
0468         if(!(regs->cset.status & NPORT_STAT_BBUSY))
0469             break;
0470     return !t;
0471 }
0472 
0473 /*
0474  * DCBMODE register defines:
0475  */
0476 
0477 /* Width of the data being transferred for each DCBDATA[01] word */
0478 #define DCB_DATAWIDTH_4 0x0
0479 #define DCB_DATAWIDTH_1 0x1
0480 #define DCB_DATAWIDTH_2 0x2
0481 #define DCB_DATAWIDTH_3 0x3
0482 
0483 /* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */
0484 #define DCB_ENDATAPACK   (1 << 2)
0485 
0486 /* Enables DCBCRS auto increment after each DCB transfer */
0487 #define DCB_ENCRSINC     (1 << 3)
0488 
0489 /* shift for accessing the control register select address (DBCCRS, 3 bits) */
0490 #define DCB_CRS_SHIFT    4
0491 
0492 /* DCBADDR (4 bits): display bus slave address */
0493 #define DCB_ADDR_SHIFT   7
0494 #define DCB_VC2          (0 <<  DCB_ADDR_SHIFT)
0495 #define DCB_CMAP_ALL     (1 <<  DCB_ADDR_SHIFT)
0496 #define DCB_CMAP0        (2 <<  DCB_ADDR_SHIFT)
0497 #define DCB_CMAP1        (3 <<  DCB_ADDR_SHIFT)
0498 #define DCB_XMAP_ALL     (4 <<  DCB_ADDR_SHIFT)
0499 #define DCB_XMAP0        (5 <<  DCB_ADDR_SHIFT)
0500 #define DCB_XMAP1        (6 <<  DCB_ADDR_SHIFT)
0501 #define DCB_BT445        (7 <<  DCB_ADDR_SHIFT)
0502 #define DCB_VCC1         (8 <<  DCB_ADDR_SHIFT)
0503 #define DCB_VAB1         (9 <<  DCB_ADDR_SHIFT)
0504 #define DCB_LG3_BDVERS0  (10 << DCB_ADDR_SHIFT)
0505 #define DCB_LG3_ICS1562  (11 << DCB_ADDR_SHIFT)
0506 #define DCB_RESERVED     (15 << DCB_ADDR_SHIFT)
0507 
0508 /* DCB protocol ack types */
0509 #define DCB_ENSYNCACK    (1 << 11)
0510 #define DCB_ENASYNCACK   (1 << 12)
0511 
0512 #define DCB_CSWIDTH_SHIFT 13
0513 #define DCB_CSHOLD_SHIFT  18
0514 #define DCB_CSSETUP_SHIFT 23
0515 
0516 /* XMAP9 specific defines */
0517 /*   XMAP9 -- registers as seen on the DCBMODE register*/
0518 #   define XM9_CRS_CONFIG            (0 << DCB_CRS_SHIFT)
0519 #       define XM9_PUPMODE           (1 << 0)
0520 #       define XM9_ODD_PIXEL         (1 << 1)
0521 #       define XM9_8_BITPLANES       (1 << 2)
0522 #       define XM9_SLOW_DCB          (1 << 3)
0523 #       define XM9_VIDEO_RGBMAP_MASK (3 << 4)
0524 #       define XM9_EXPRESS_VIDEO     (1 << 6)
0525 #       define XM9_VIDEO_OPTION      (1 << 7)
0526 #   define XM9_CRS_REVISION          (1 << DCB_CRS_SHIFT)
0527 #   define XM9_CRS_FIFO_AVAIL        (2 << DCB_CRS_SHIFT)
0528 #       define XM9_FIFO_0_AVAIL      0
0529 #       define XM9_FIFO_1_AVAIL      1
0530 #       define XM9_FIFO_2_AVAIL      3
0531 #       define XM9_FIFO_3_AVAIL      2
0532 #       define XM9_FIFO_FULL         XM9_FIFO_0_AVAIL
0533 #       define XM9_FIFO_EMPTY        XM9_FIFO_3_AVAIL
0534 #   define XM9_CRS_CURS_CMAP_MSB     (3 << DCB_CRS_SHIFT)
0535 #   define XM9_CRS_PUP_CMAP_MSB      (4 << DCB_CRS_SHIFT)
0536 #   define XM9_CRS_MODE_REG_DATA     (5 << DCB_CRS_SHIFT)
0537 #   define XM9_CRS_MODE_REG_INDEX    (7 << DCB_CRS_SHIFT)
0538 
0539 
0540 #define DCB_CYCLES(setup,hold,width)                \
0541                   ((hold << DCB_CSHOLD_SHIFT)  |    \
0542            (setup << DCB_CSSETUP_SHIFT)|    \
0543            (width << DCB_CSWIDTH_SHIFT))
0544 
0545 #define W_DCB_XMAP9_PROTOCOL       DCB_CYCLES (2, 1, 0)
0546 #define WSLOW_DCB_XMAP9_PROTOCOL   DCB_CYCLES (5, 5, 0)
0547 #define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
0548 #define R_DCB_XMAP9_PROTOCOL       DCB_CYCLES (2, 1, 3)
0549 
0550 static __inline__ void
0551 xmap9FIFOWait (struct newport_regs *rex)
0552 {
0553         rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |
0554         DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;
0555         newport_bfwait (rex);
0556     
0557         while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY)
0558         ;
0559 }
0560 
0561 static __inline__ void
0562 xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq)
0563 {
0564         if (cfreq > 119)
0565             rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
0566                         DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;
0567         else if (cfreq > 59)
0568             rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
0569             DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;    
0570         else
0571             rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
0572                         DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL; 
0573         rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff);
0574 }
0575 
0576 #define BT445_PROTOCOL      DCB_CYCLES(1,1,3)
0577 
0578 #define BT445_CSR_ADDR_REG  (0 << DCB_CRS_SHIFT)
0579 #define BT445_CSR_REVISION  (2 << DCB_CRS_SHIFT)
0580 
0581 #define BT445_REVISION_REG  0x01
0582 
0583 #endif /* !(_SGI_NEWPORT_H) */
0584
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