include/video/imx-ipu-v3.h

0001 /*
0002  * Copyright 2005-2009 Freescale Semiconductor, Inc.
0003  *
0004  * The code contained herein is licensed under the GNU Lesser General
0005  * Public License.  You may obtain a copy of the GNU Lesser General
0006  * Public License Version 2.1 or later at the following locations:
0007  *
0008  * http://www.opensource.org/licenses/lgpl-license.html
0009  * http://www.gnu.org/copyleft/lgpl.html
0010  */
0011
0012 #ifndef __DRM_IPU_H__
0013 #define __DRM_IPU_H__
0014
0015 #include <linux/types.h>
0016 #include <linux/videodev2.h>
0017 #include <linux/bitmap.h>
0018 #include <linux/fb.h>
0019 #include <linux/of.h>
0020 #include <drm/drm_color_mgmt.h>
0021 #include <media/v4l2-mediabus.h>
0022 #include <video/videomode.h>
0023
0024 struct ipu_soc;
0025
0026 enum ipuv3_type {
0027     IPUV3EX,
0028     IPUV3M,
0029     IPUV3H,
0030 };
0031
0032 #define IPU_PIX_FMT_GBR24   v4l2_fourcc('G', 'B', 'R', '3')
0033
0034 /*
0035  * Bitfield of Display Interface signal polarities.
0036  */
0037 struct ipu_di_signal_cfg {
0038     unsigned data_pol:1;    /* true = inverted */
0039     unsigned clk_pol:1; /* true = rising edge */
0040     unsigned enable_pol:1;
0041
0042     struct videomode mode;
0043
0044     u32 bus_format;
0045     u32 v_to_h_sync;
0046
0047 #define IPU_DI_CLKMODE_SYNC (1 << 0)
0048 #define IPU_DI_CLKMODE_EXT  (1 << 1)
0049     unsigned long clkflags;
0050
0051     u8 hsync_pin;
0052     u8 vsync_pin;
0053 };
0054
0055 /*
0056  * Enumeration of CSI destinations
0057  */
0058 enum ipu_csi_dest {
0059     IPU_CSI_DEST_IDMAC, /* to memory via SMFC */
0060     IPU_CSI_DEST_IC,    /* to Image Converter */
0061     IPU_CSI_DEST_VDIC,  /* to VDIC */
0062 };
0063
0064 /*
0065  * Enumeration of IPU rotation modes
0066  */
0067 #define IPU_ROT_BIT_VFLIP (1 << 0)
0068 #define IPU_ROT_BIT_HFLIP (1 << 1)
0069 #define IPU_ROT_BIT_90    (1 << 2)
0070
0071 enum ipu_rotate_mode {
0072     IPU_ROTATE_NONE = 0,
0073     IPU_ROTATE_VERT_FLIP = IPU_ROT_BIT_VFLIP,
0074     IPU_ROTATE_HORIZ_FLIP = IPU_ROT_BIT_HFLIP,
0075     IPU_ROTATE_180 = (IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
0076     IPU_ROTATE_90_RIGHT = IPU_ROT_BIT_90,
0077     IPU_ROTATE_90_RIGHT_VFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_VFLIP),
0078     IPU_ROTATE_90_RIGHT_HFLIP = (IPU_ROT_BIT_90 | IPU_ROT_BIT_HFLIP),
0079     IPU_ROTATE_90_LEFT = (IPU_ROT_BIT_90 |
0080                   IPU_ROT_BIT_VFLIP | IPU_ROT_BIT_HFLIP),
0081 };
0082
0083 /* 90-degree rotations require the IRT unit */
0084 #define ipu_rot_mode_is_irt(m) (((m) & IPU_ROT_BIT_90) != 0)
0085
0086 enum ipu_color_space {
0087     IPUV3_COLORSPACE_RGB,
0088     IPUV3_COLORSPACE_YUV,
0089     IPUV3_COLORSPACE_UNKNOWN,
0090 };
0091
0092 /*
0093  * Enumeration of VDI MOTION select
0094  */
0095 enum ipu_motion_sel {
0096     MOTION_NONE = 0,
0097     LOW_MOTION,
0098     MED_MOTION,
0099     HIGH_MOTION,
0100 };
0101
0102 struct ipuv3_channel;
0103
0104 enum ipu_channel_irq {
0105     IPU_IRQ_EOF = 0,
0106     IPU_IRQ_NFACK = 64,
0107     IPU_IRQ_NFB4EOF = 128,
0108     IPU_IRQ_EOS = 192,
0109 };
0110
0111 /*
0112  * Enumeration of IDMAC channels
0113  */
0114 #define IPUV3_CHANNEL_CSI0           0
0115 #define IPUV3_CHANNEL_CSI1           1
0116 #define IPUV3_CHANNEL_CSI2           2
0117 #define IPUV3_CHANNEL_CSI3           3
0118 #define IPUV3_CHANNEL_VDI_MEM_IC_VF      5
0119 /*
0120  * NOTE: channels 6,7 are unused in the IPU and are not IDMAC channels,
0121  * but the direct CSI->VDI linking is handled the same way as IDMAC
0122  * channel linking in the FSU via the IPU_FS_PROC_FLOW registers, so
0123  * these channel names are used to support the direct CSI->VDI link.
0124  */
0125 #define IPUV3_CHANNEL_CSI_DIRECT         6
0126 #define IPUV3_CHANNEL_CSI_VDI_PREV       7
0127 #define IPUV3_CHANNEL_MEM_VDI_PREV       8
0128 #define IPUV3_CHANNEL_MEM_VDI_CUR        9
0129 #define IPUV3_CHANNEL_MEM_VDI_NEXT      10
0130 #define IPUV3_CHANNEL_MEM_IC_PP         11
0131 #define IPUV3_CHANNEL_MEM_IC_PRP_VF     12
0132 #define IPUV3_CHANNEL_VDI_MEM_RECENT        13
0133 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF       14
0134 #define IPUV3_CHANNEL_G_MEM_IC_PP       15
0135 #define IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA 17
0136 #define IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA     18
0137 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA 19
0138 #define IPUV3_CHANNEL_IC_PRP_ENC_MEM        20
0139 #define IPUV3_CHANNEL_IC_PRP_VF_MEM     21
0140 #define IPUV3_CHANNEL_IC_PP_MEM         22
0141 #define IPUV3_CHANNEL_MEM_BG_SYNC       23
0142 #define IPUV3_CHANNEL_MEM_BG_ASYNC      24
0143 #define IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB   25
0144 #define IPUV3_CHANNEL_MEM_VDI_PLANE3_COMB   26
0145 #define IPUV3_CHANNEL_MEM_FG_SYNC       27
0146 #define IPUV3_CHANNEL_MEM_DC_SYNC       28
0147 #define IPUV3_CHANNEL_MEM_FG_ASYNC      29
0148 #define IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA     31
0149 #define IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA    33
0150 #define IPUV3_CHANNEL_DC_MEM_READ       40
0151 #define IPUV3_CHANNEL_MEM_DC_ASYNC      41
0152 #define IPUV3_CHANNEL_MEM_DC_COMMAND        42
0153 #define IPUV3_CHANNEL_MEM_DC_COMMAND2       43
0154 #define IPUV3_CHANNEL_MEM_DC_OUTPUT_MASK    44
0155 #define IPUV3_CHANNEL_MEM_ROT_ENC       45
0156 #define IPUV3_CHANNEL_MEM_ROT_VF        46
0157 #define IPUV3_CHANNEL_MEM_ROT_PP        47
0158 #define IPUV3_CHANNEL_ROT_ENC_MEM       48
0159 #define IPUV3_CHANNEL_ROT_VF_MEM        49
0160 #define IPUV3_CHANNEL_ROT_PP_MEM        50
0161 #define IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA     51
0162 #define IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA    52
0163 #define IPUV3_NUM_CHANNELS          64
0164
0165 static inline int ipu_channel_alpha_channel(int ch_num)
0166 {
0167     switch (ch_num) {
0168     case IPUV3_CHANNEL_G_MEM_IC_PRP_VF:
0169         return IPUV3_CHANNEL_G_MEM_IC_PRP_VF_ALPHA;
0170     case IPUV3_CHANNEL_G_MEM_IC_PP:
0171         return IPUV3_CHANNEL_G_MEM_IC_PP_ALPHA;
0172     case IPUV3_CHANNEL_MEM_FG_SYNC:
0173         return IPUV3_CHANNEL_MEM_FG_SYNC_ALPHA;
0174     case IPUV3_CHANNEL_MEM_FG_ASYNC:
0175         return IPUV3_CHANNEL_MEM_FG_ASYNC_ALPHA;
0176     case IPUV3_CHANNEL_MEM_BG_SYNC:
0177         return IPUV3_CHANNEL_MEM_BG_SYNC_ALPHA;
0178     case IPUV3_CHANNEL_MEM_BG_ASYNC:
0179         return IPUV3_CHANNEL_MEM_BG_ASYNC_ALPHA;
0180     case IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB:
0181         return IPUV3_CHANNEL_MEM_VDI_PLANE1_COMB_ALPHA;
0182     default:
0183         return -EINVAL;
0184     }
0185 }
0186
0187 int ipu_map_irq(struct ipu_soc *ipu, int irq);
0188 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
0189         enum ipu_channel_irq irq);
0190
0191 #define IPU_IRQ_DP_SF_START     (448 + 2)
0192 #define IPU_IRQ_DP_SF_END       (448 + 3)
0193 #define IPU_IRQ_BG_SF_END       IPU_IRQ_DP_SF_END,
0194 #define IPU_IRQ_DC_FC_0         (448 + 8)
0195 #define IPU_IRQ_DC_FC_1         (448 + 9)
0196 #define IPU_IRQ_DC_FC_2         (448 + 10)
0197 #define IPU_IRQ_DC_FC_3         (448 + 11)
0198 #define IPU_IRQ_DC_FC_4         (448 + 12)
0199 #define IPU_IRQ_DC_FC_6         (448 + 13)
0200 #define IPU_IRQ_VSYNC_PRE_0     (448 + 14)
0201 #define IPU_IRQ_VSYNC_PRE_1     (448 + 15)
0202
0203 /*
0204  * IPU Common functions
0205  */
0206 int ipu_get_num(struct ipu_soc *ipu);
0207 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
0208 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
0209 void ipu_dump(struct ipu_soc *ipu);
0210
0211 /*
0212  * IPU Image DMA Controller (idmac) functions
0213  */
0214 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
0215 void ipu_idmac_put(struct ipuv3_channel *);
0216
0217 int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
0218 int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
0219 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable);
0220 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts);
0221 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
0222
0223 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
0224         bool doublebuffer);
0225 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
0226 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num);
0227 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
0228 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num);
0229 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch);
0230 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch);
0231 int ipu_idmac_link(struct ipuv3_channel *src, struct ipuv3_channel *sink);
0232 int ipu_idmac_unlink(struct ipuv3_channel *src, struct ipuv3_channel *sink);
0233
0234 /*
0235  * IPU Channel Parameter Memory (cpmem) functions
0236  */
0237 struct ipu_rgb {
0238     struct fb_bitfield      red;
0239     struct fb_bitfield      green;
0240     struct fb_bitfield      blue;
0241     struct fb_bitfield      transp;
0242     int                     bits_per_pixel;
0243 };
0244
0245 struct ipu_image {
0246     struct v4l2_pix_format pix;
0247     struct v4l2_rect rect;
0248     dma_addr_t phys0;
0249     dma_addr_t phys1;
0250     /* chroma plane offset overrides */
0251     u32 u_offset;
0252     u32 v_offset;
0253 };
0254
0255 void ipu_cpmem_zero(struct ipuv3_channel *ch);
0256 void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
0257 void ipu_cpmem_skip_odd_chroma_rows(struct ipuv3_channel *ch);
0258 void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
0259 void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
0260 void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
0261 void ipu_cpmem_set_uv_offset(struct ipuv3_channel *ch, u32 u_off, u32 v_off);
0262 void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride,
0263                    u32 pixelformat);
0264 void ipu_cpmem_set_axi_id(struct ipuv3_channel *ch, u32 id);
0265 int ipu_cpmem_get_burstsize(struct ipuv3_channel *ch);
0266 void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
0267 void ipu_cpmem_set_block_mode(struct ipuv3_channel *ch);
0268 void ipu_cpmem_set_rotation(struct ipuv3_channel *ch,
0269                 enum ipu_rotate_mode rot);
0270 int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
0271                  const struct ipu_rgb *rgb);
0272 int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
0273 void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
0274 void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
0275                    unsigned int uv_stride,
0276                    unsigned int u_offset,
0277                    unsigned int v_offset);
0278 int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
0279 int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
0280 void ipu_cpmem_dump(struct ipuv3_channel *ch);
0281
0282 /*
0283  * IPU Display Controller (dc) functions
0284  */
0285 struct ipu_dc;
0286 struct ipu_di;
0287 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
0288 void ipu_dc_put(struct ipu_dc *dc);
0289 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
0290         u32 pixel_fmt, u32 width);
0291 void ipu_dc_enable(struct ipu_soc *ipu);
0292 void ipu_dc_enable_channel(struct ipu_dc *dc);
0293 void ipu_dc_disable_channel(struct ipu_dc *dc);
0294 void ipu_dc_disable(struct ipu_soc *ipu);
0295
0296 /*
0297  * IPU Display Interface (di) functions
0298  */
0299 struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
0300 void ipu_di_put(struct ipu_di *);
0301 int ipu_di_disable(struct ipu_di *);
0302 int ipu_di_enable(struct ipu_di *);
0303 int ipu_di_get_num(struct ipu_di *);
0304 int ipu_di_adjust_videomode(struct ipu_di *di, struct videomode *mode);
0305 int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
0306
0307 /*
0308  * IPU Display Multi FIFO Controller (dmfc) functions
0309  */
0310 struct dmfc_channel;
0311 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
0312 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
0313 void ipu_dmfc_config_wait4eot(struct dmfc_channel *dmfc, int width);
0314 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
0315 void ipu_dmfc_put(struct dmfc_channel *dmfc);
0316
0317 /*
0318  * IPU Display Processor (dp) functions
0319  */
0320 #define IPU_DP_FLOW_SYNC_BG 0
0321 #define IPU_DP_FLOW_SYNC_FG 1
0322 #define IPU_DP_FLOW_ASYNC0_BG   2
0323 #define IPU_DP_FLOW_ASYNC0_FG   3
0324 #define IPU_DP_FLOW_ASYNC1_BG   4
0325 #define IPU_DP_FLOW_ASYNC1_FG   5
0326
0327 struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
0328 void ipu_dp_put(struct ipu_dp *);
0329 int ipu_dp_enable(struct ipu_soc *ipu);
0330 int ipu_dp_enable_channel(struct ipu_dp *dp);
0331 void ipu_dp_disable_channel(struct ipu_dp *dp, bool sync);
0332 void ipu_dp_disable(struct ipu_soc *ipu);
0333 int ipu_dp_setup_channel(struct ipu_dp *dp,
0334         enum drm_color_encoding ycbcr_enc, enum drm_color_range range,
0335         enum ipu_color_space in, enum ipu_color_space out);
0336 int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
0337 int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
0338         bool bg_chan);
0339
0340 /*
0341  * IPU Prefetch Resolve Gasket (prg) functions
0342  */
0343 int ipu_prg_max_active_channels(void);
0344 bool ipu_prg_present(struct ipu_soc *ipu);
0345 bool ipu_prg_format_supported(struct ipu_soc *ipu, uint32_t format,
0346                   uint64_t modifier);
0347 int ipu_prg_enable(struct ipu_soc *ipu);
0348 void ipu_prg_disable(struct ipu_soc *ipu);
0349 void ipu_prg_channel_disable(struct ipuv3_channel *ipu_chan);
0350 int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
0351                   unsigned int axi_id,  unsigned int width,
0352                   unsigned int height, unsigned int stride,
0353                   u32 format, uint64_t modifier, unsigned long *eba);
0354 bool ipu_prg_channel_configure_pending(struct ipuv3_channel *ipu_chan);
0355
0356 /*
0357  * IPU CMOS Sensor Interface (csi) functions
0358  */
0359 struct ipu_csi;
0360 int ipu_csi_init_interface(struct ipu_csi *csi,
0361                const struct v4l2_mbus_config *mbus_cfg,
0362                const struct v4l2_mbus_framefmt *infmt,
0363                const struct v4l2_mbus_framefmt *outfmt);
0364 bool ipu_csi_is_interlaced(struct ipu_csi *csi);
0365 void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w);
0366 void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w);
0367 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert);
0368 void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
0369                 u32 r_value, u32 g_value, u32 b_value,
0370                 u32 pix_clk);
0371 int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
0372                   struct v4l2_mbus_framefmt *mbus_fmt);
0373 int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
0374               u32 max_ratio, u32 id);
0375 int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest);
0376 int ipu_csi_enable(struct ipu_csi *csi);
0377 int ipu_csi_disable(struct ipu_csi *csi);
0378 struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id);
0379 void ipu_csi_put(struct ipu_csi *csi);
0380 void ipu_csi_dump(struct ipu_csi *csi);
0381
0382 /*
0383  * IPU Image Converter (ic) functions
0384  */
0385 enum ipu_ic_task {
0386     IC_TASK_ENCODER,
0387     IC_TASK_VIEWFINDER,
0388     IC_TASK_POST_PROCESSOR,
0389     IC_NUM_TASKS,
0390 };
0391
0392 /*
0393  * The parameters that describe a colorspace according to the
0394  * Image Converter:
0395  *    - Y'CbCr encoding
0396  *    - quantization
0397  *    - "colorspace" (RGB or YUV).
0398  */
0399 struct ipu_ic_colorspace {
0400     enum v4l2_ycbcr_encoding enc;
0401     enum v4l2_quantization quant;
0402     enum ipu_color_space cs;
0403 };
0404
0405 static inline void
0406 ipu_ic_fill_colorspace(struct ipu_ic_colorspace *ic_cs,
0407                enum v4l2_ycbcr_encoding enc,
0408                enum v4l2_quantization quant,
0409                enum ipu_color_space cs)
0410 {
0411     ic_cs->enc = enc;
0412     ic_cs->quant = quant;
0413     ic_cs->cs = cs;
0414 }
0415
0416 struct ipu_ic_csc_params {
0417     s16 coeff[3][3];    /* signed 9-bit integer coefficients */
0418     s16 offset[3];      /* signed 11+2-bit fixed point offset */
0419     u8 scale:2;     /* scale coefficients * 2^(scale-1) */
0420     bool sat:1;     /* saturate to (16, 235(Y) / 240(U, V)) */
0421 };
0422
0423 struct ipu_ic_csc {
0424     struct ipu_ic_colorspace in_cs;
0425     struct ipu_ic_colorspace out_cs;
0426     struct ipu_ic_csc_params params;
0427 };
0428
0429 struct ipu_ic;
0430
0431 int __ipu_ic_calc_csc(struct ipu_ic_csc *csc);
0432 int ipu_ic_calc_csc(struct ipu_ic_csc *csc,
0433             enum v4l2_ycbcr_encoding in_enc,
0434             enum v4l2_quantization in_quant,
0435             enum ipu_color_space in_cs,
0436             enum v4l2_ycbcr_encoding out_enc,
0437             enum v4l2_quantization out_quant,
0438             enum ipu_color_space out_cs);
0439 int ipu_ic_task_init(struct ipu_ic *ic,
0440              const struct ipu_ic_csc *csc,
0441              int in_width, int in_height,
0442              int out_width, int out_height);
0443 int ipu_ic_task_init_rsc(struct ipu_ic *ic,
0444              const struct ipu_ic_csc *csc,
0445              int in_width, int in_height,
0446              int out_width, int out_height,
0447              u32 rsc);
0448 int ipu_ic_task_graphics_init(struct ipu_ic *ic,
0449                   const struct ipu_ic_colorspace *g_in_cs,
0450                   bool galpha_en, u32 galpha,
0451                   bool colorkey_en, u32 colorkey);
0452 void ipu_ic_task_enable(struct ipu_ic *ic);
0453 void ipu_ic_task_disable(struct ipu_ic *ic);
0454 int ipu_ic_task_idma_init(struct ipu_ic *ic, struct ipuv3_channel *channel,
0455               u32 width, u32 height, int burst_size,
0456               enum ipu_rotate_mode rot);
0457 int ipu_ic_enable(struct ipu_ic *ic);
0458 int ipu_ic_disable(struct ipu_ic *ic);
0459 struct ipu_ic *ipu_ic_get(struct ipu_soc *ipu, enum ipu_ic_task task);
0460 void ipu_ic_put(struct ipu_ic *ic);
0461 void ipu_ic_dump(struct ipu_ic *ic);
0462
0463 /*
0464  * IPU Video De-Interlacer (vdi) functions
0465  */
0466 struct ipu_vdi;
0467 void ipu_vdi_set_field_order(struct ipu_vdi *vdi, v4l2_std_id std, u32 field);
0468 void ipu_vdi_set_motion(struct ipu_vdi *vdi, enum ipu_motion_sel motion_sel);
0469 void ipu_vdi_setup(struct ipu_vdi *vdi, u32 code, int xres, int yres);
0470 void ipu_vdi_unsetup(struct ipu_vdi *vdi);
0471 int ipu_vdi_enable(struct ipu_vdi *vdi);
0472 int ipu_vdi_disable(struct ipu_vdi *vdi);
0473 struct ipu_vdi *ipu_vdi_get(struct ipu_soc *ipu);
0474 void ipu_vdi_put(struct ipu_vdi *vdi);
0475
0476 /*
0477  * IPU Sensor Multiple FIFO Controller (SMFC) functions
0478  */
0479 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno);
0480 void ipu_smfc_put(struct ipu_smfc *smfc);
0481 int ipu_smfc_enable(struct ipu_smfc *smfc);
0482 int ipu_smfc_disable(struct ipu_smfc *smfc);
0483 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id);
0484 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize);
0485 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level);
0486
0487 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
0488 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
0489 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
0490                 bool hflip, bool vflip);
0491 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
0492                 bool hflip, bool vflip);
0493
0494 struct ipu_client_platformdata {
0495     int csi;
0496     int di;
0497     int dc;
0498     int dp;
0499     int dma[2];
0500     struct device_node *of_node;
0501 };
0502
0503 #endif /* __DRM_IPU_H__ */