include/ufs/ufshci.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Universal Flash Storage Host controller driver
0004  * Copyright (C) 2011-2013 Samsung India Software Operations
0005  *
0006  * Authors:
0007  *  Santosh Yaraganavi <santosh.sy@samsung.com>
0008  *  Vinayak Holikatti <h.vinayak@samsung.com>
0009  */
0010
0011 #ifndef _UFSHCI_H
0012 #define _UFSHCI_H
0013
0014 #include <scsi/scsi_host.h>
0015
0016 enum {
0017     TASK_REQ_UPIU_SIZE_DWORDS   = 8,
0018     TASK_RSP_UPIU_SIZE_DWORDS   = 8,
0019     ALIGNED_UPIU_SIZE       = 512,
0020 };
0021
0022 /* UFSHCI Registers */
0023 enum {
0024     REG_CONTROLLER_CAPABILITIES     = 0x00,
0025     REG_UFS_VERSION             = 0x08,
0026     REG_CONTROLLER_DEV_ID           = 0x10,
0027     REG_CONTROLLER_PROD_ID          = 0x14,
0028     REG_AUTO_HIBERNATE_IDLE_TIMER       = 0x18,
0029     REG_INTERRUPT_STATUS            = 0x20,
0030     REG_INTERRUPT_ENABLE            = 0x24,
0031     REG_CONTROLLER_STATUS           = 0x30,
0032     REG_CONTROLLER_ENABLE           = 0x34,
0033     REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER    = 0x38,
0034     REG_UIC_ERROR_CODE_DATA_LINK_LAYER  = 0x3C,
0035     REG_UIC_ERROR_CODE_NETWORK_LAYER    = 0x40,
0036     REG_UIC_ERROR_CODE_TRANSPORT_LAYER  = 0x44,
0037     REG_UIC_ERROR_CODE_DME          = 0x48,
0038     REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL    = 0x4C,
0039     REG_UTP_TRANSFER_REQ_LIST_BASE_L    = 0x50,
0040     REG_UTP_TRANSFER_REQ_LIST_BASE_H    = 0x54,
0041     REG_UTP_TRANSFER_REQ_DOOR_BELL      = 0x58,
0042     REG_UTP_TRANSFER_REQ_LIST_CLEAR     = 0x5C,
0043     REG_UTP_TRANSFER_REQ_LIST_RUN_STOP  = 0x60,
0044     REG_UTP_TASK_REQ_LIST_BASE_L        = 0x70,
0045     REG_UTP_TASK_REQ_LIST_BASE_H        = 0x74,
0046     REG_UTP_TASK_REQ_DOOR_BELL      = 0x78,
0047     REG_UTP_TASK_REQ_LIST_CLEAR     = 0x7C,
0048     REG_UTP_TASK_REQ_LIST_RUN_STOP      = 0x80,
0049     REG_UIC_COMMAND             = 0x90,
0050     REG_UIC_COMMAND_ARG_1           = 0x94,
0051     REG_UIC_COMMAND_ARG_2           = 0x98,
0052     REG_UIC_COMMAND_ARG_3           = 0x9C,
0053
0054     UFSHCI_REG_SPACE_SIZE           = 0xA0,
0055
0056     REG_UFS_CCAP                = 0x100,
0057     REG_UFS_CRYPTOCAP           = 0x104,
0058
0059     UFSHCI_CRYPTO_REG_SPACE_SIZE        = 0x400,
0060 };
0061
0062 /* Controller capability masks */
0063 enum {
0064     MASK_TRANSFER_REQUESTS_SLOTS        = 0x0000001F,
0065     MASK_TASK_MANAGEMENT_REQUEST_SLOTS  = 0x00070000,
0066     MASK_AUTO_HIBERN8_SUPPORT       = 0x00800000,
0067     MASK_64_ADDRESSING_SUPPORT      = 0x01000000,
0068     MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
0069     MASK_UIC_DME_TEST_MODE_SUPPORT      = 0x04000000,
0070     MASK_CRYPTO_SUPPORT         = 0x10000000,
0071 };
0072
0073 #define UFS_MASK(mask, offset)      ((mask) << (offset))
0074
0075 /* UFS Version 08h */
0076 #define MINOR_VERSION_NUM_MASK      UFS_MASK(0xFFFF, 0)
0077 #define MAJOR_VERSION_NUM_MASK      UFS_MASK(0xFFFF, 16)
0078
0079 /*
0080  * Controller UFSHCI version
0081  * - 2.x and newer use the following scheme:
0082  *   major << 8 + minor << 4
0083  * - 1.x has been converted to match this in
0084  *   ufshcd_get_ufs_version()
0085  */
0086 static inline u32 ufshci_version(u32 major, u32 minor)
0087 {
0088     return (major << 8) + (minor << 4);
0089 }
0090
0091 /*
0092  * HCDDID - Host Controller Identification Descriptor
0093  *    - Device ID and Device Class 10h
0094  */
0095 #define DEVICE_CLASS    UFS_MASK(0xFFFF, 0)
0096 #define DEVICE_ID   UFS_MASK(0xFF, 24)
0097
0098 /*
0099  * HCPMID - Host Controller Identification Descriptor
0100  *    - Product/Manufacturer ID  14h
0101  */
0102 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
0103 #define PRODUCT_ID_MASK     UFS_MASK(0xFFFF, 16)
0104
0105 /* AHIT - Auto-Hibernate Idle Timer */
0106 #define UFSHCI_AHIBERN8_TIMER_MASK      GENMASK(9, 0)
0107 #define UFSHCI_AHIBERN8_SCALE_MASK      GENMASK(12, 10)
0108 #define UFSHCI_AHIBERN8_SCALE_FACTOR        10
0109 #define UFSHCI_AHIBERN8_MAX         (1023 * 100000)
0110
0111 /*
0112  * IS - Interrupt Status - 20h
0113  */
0114 #define UTP_TRANSFER_REQ_COMPL          0x1
0115 #define UIC_DME_END_PT_RESET            0x2
0116 #define UIC_ERROR               0x4
0117 #define UIC_TEST_MODE               0x8
0118 #define UIC_POWER_MODE              0x10
0119 #define UIC_HIBERNATE_EXIT          0x20
0120 #define UIC_HIBERNATE_ENTER         0x40
0121 #define UIC_LINK_LOST               0x80
0122 #define UIC_LINK_STARTUP            0x100
0123 #define UTP_TASK_REQ_COMPL          0x200
0124 #define UIC_COMMAND_COMPL           0x400
0125 #define DEVICE_FATAL_ERROR          0x800
0126 #define CONTROLLER_FATAL_ERROR          0x10000
0127 #define SYSTEM_BUS_FATAL_ERROR          0x20000
0128 #define CRYPTO_ENGINE_FATAL_ERROR       0x40000
0129
0130 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
0131                 UIC_HIBERNATE_EXIT)
0132
0133 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
0134                 UIC_POWER_MODE)
0135
0136 #define UFSHCD_UIC_MASK     (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
0137
0138 #define UFSHCD_ERROR_MASK   (UIC_ERROR | INT_FATAL_ERRORS)
0139
0140 #define INT_FATAL_ERRORS    (DEVICE_FATAL_ERROR |\
0141                 CONTROLLER_FATAL_ERROR |\
0142                 SYSTEM_BUS_FATAL_ERROR |\
0143                 CRYPTO_ENGINE_FATAL_ERROR |\
0144                 UIC_LINK_LOST)
0145
0146 /* HCS - Host Controller Status 30h */
0147 #define DEVICE_PRESENT              0x1
0148 #define UTP_TRANSFER_REQ_LIST_READY     0x2
0149 #define UTP_TASK_REQ_LIST_READY         0x4
0150 #define UIC_COMMAND_READY           0x8
0151 #define HOST_ERROR_INDICATOR            0x10
0152 #define DEVICE_ERROR_INDICATOR          0x20
0153 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK   UFS_MASK(0x7, 8)
0154
0155 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
0156                 UTP_TASK_REQ_LIST_READY |\
0157                 UIC_COMMAND_READY)
0158
0159 enum {
0160     PWR_OK      = 0x0,
0161     PWR_LOCAL   = 0x01,
0162     PWR_REMOTE  = 0x02,
0163     PWR_BUSY    = 0x03,
0164     PWR_ERROR_CAP   = 0x04,
0165     PWR_FATAL_ERROR = 0x05,
0166 };
0167
0168 /* HCE - Host Controller Enable 34h */
0169 #define CONTROLLER_ENABLE   0x1
0170 #define CONTROLLER_DISABLE  0x0
0171 #define CRYPTO_GENERAL_ENABLE   0x2
0172
0173 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
0174 #define UIC_PHY_ADAPTER_LAYER_ERROR         0x80000000
0175 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK       0x1F
0176 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK     0xF
0177 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR     0x10
0178
0179 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
0180 #define UIC_DATA_LINK_LAYER_ERROR       0x80000000
0181 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
0182 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
0183 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP    0x4
0184 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
0185 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
0186 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT   0x2000
0187 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED  0x0001
0188 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
0189
0190 /* UECN - Host UIC Error Code Network Layer 40h */
0191 #define UIC_NETWORK_LAYER_ERROR         0x80000000
0192 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK   0x7
0193 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
0194 #define UIC_NETWORK_BAD_DEVICEID_ENC        0x2
0195 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING   0x4
0196
0197 /* UECT - Host UIC Error Code Transport Layer 44h */
0198 #define UIC_TRANSPORT_LAYER_ERROR       0x80000000
0199 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
0200 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE   0x1
0201 #define UIC_TRANSPORT_UNKNOWN_CPORTID       0x2
0202 #define UIC_TRANSPORT_NO_CONNECTION_RX      0x4
0203 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING   0x8
0204 #define UIC_TRANSPORT_BAD_TC            0x10
0205 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW    0x20
0206 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
0207
0208 /* UECDME - Host UIC Error Code DME 48h */
0209 #define UIC_DME_ERROR           0x80000000
0210 #define UIC_DME_ERROR_CODE_MASK     0x1
0211
0212 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
0213 #define INT_AGGR_TIMEOUT_VAL_MASK       0xFF
0214 #define INT_AGGR_COUNTER_THRESHOLD_MASK     UFS_MASK(0x1F, 8)
0215 #define INT_AGGR_COUNTER_AND_TIMER_RESET    0x10000
0216 #define INT_AGGR_STATUS_BIT         0x100000
0217 #define INT_AGGR_PARAM_WRITE            0x1000000
0218 #define INT_AGGR_ENABLE             0x80000000
0219
0220 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
0221 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT  0x1
0222
0223 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
0224 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT      0x1
0225
0226 /* UICCMD - UIC Command */
0227 #define COMMAND_OPCODE_MASK     0xFF
0228 #define GEN_SELECTOR_INDEX_MASK     0xFFFF
0229
0230 #define MIB_ATTRIBUTE_MASK      UFS_MASK(0xFFFF, 16)
0231 #define RESET_LEVEL         0xFF
0232
0233 #define ATTR_SET_TYPE_MASK      UFS_MASK(0xFF, 16)
0234 #define CONFIG_RESULT_CODE_MASK     0xFF
0235 #define GENERIC_ERROR_CODE_MASK     0xFF
0236
0237 /* GenSelectorIndex calculation macros for M-PHY attributes */
0238 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
0239 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
0240
0241 #define UIC_ARG_MIB_SEL(attr, sel)  ((((attr) & 0xFFFF) << 16) |\
0242                      ((sel) & 0xFFFF))
0243 #define UIC_ARG_MIB(attr)       UIC_ARG_MIB_SEL(attr, 0)
0244 #define UIC_ARG_ATTR_TYPE(t)        (((t) & 0xFF) << 16)
0245 #define UIC_GET_ATTR_ID(v)      (((v) >> 16) & 0xFFFF)
0246
0247 /* Link Status*/
0248 enum link_status {
0249     UFSHCD_LINK_IS_DOWN = 1,
0250     UFSHCD_LINK_IS_UP   = 2,
0251 };
0252
0253 /* UIC Commands */
0254 enum uic_cmd_dme {
0255     UIC_CMD_DME_GET         = 0x01,
0256     UIC_CMD_DME_SET         = 0x02,
0257     UIC_CMD_DME_PEER_GET        = 0x03,
0258     UIC_CMD_DME_PEER_SET        = 0x04,
0259     UIC_CMD_DME_POWERON     = 0x10,
0260     UIC_CMD_DME_POWEROFF        = 0x11,
0261     UIC_CMD_DME_ENABLE      = 0x12,
0262     UIC_CMD_DME_RESET       = 0x14,
0263     UIC_CMD_DME_END_PT_RST      = 0x15,
0264     UIC_CMD_DME_LINK_STARTUP    = 0x16,
0265     UIC_CMD_DME_HIBER_ENTER     = 0x17,
0266     UIC_CMD_DME_HIBER_EXIT      = 0x18,
0267     UIC_CMD_DME_TEST_MODE       = 0x1A,
0268 };
0269
0270 /* UIC Config result code / Generic error code */
0271 enum {
0272     UIC_CMD_RESULT_SUCCESS          = 0x00,
0273     UIC_CMD_RESULT_INVALID_ATTR     = 0x01,
0274     UIC_CMD_RESULT_FAILURE          = 0x01,
0275     UIC_CMD_RESULT_INVALID_ATTR_VALUE   = 0x02,
0276     UIC_CMD_RESULT_READ_ONLY_ATTR       = 0x03,
0277     UIC_CMD_RESULT_WRITE_ONLY_ATTR      = 0x04,
0278     UIC_CMD_RESULT_BAD_INDEX        = 0x05,
0279     UIC_CMD_RESULT_LOCKED_ATTR      = 0x06,
0280     UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX   = 0x07,
0281     UIC_CMD_RESULT_PEER_COMM_FAILURE    = 0x08,
0282     UIC_CMD_RESULT_BUSY         = 0x09,
0283     UIC_CMD_RESULT_DME_FAILURE      = 0x0A,
0284 };
0285
0286 #define MASK_UIC_COMMAND_RESULT         0xFF
0287
0288 #define INT_AGGR_COUNTER_THLD_VAL(c)    (((c) & 0x1F) << 8)
0289 #define INT_AGGR_TIMEOUT_VAL(t)     (((t) & 0xFF) << 0)
0290
0291 /* Interrupt disable masks */
0292 enum {
0293     /* Interrupt disable mask for UFSHCI v1.0 */
0294     INTERRUPT_MASK_ALL_VER_10   = 0x30FFF,
0295     INTERRUPT_MASK_RW_VER_10    = 0x30000,
0296
0297     /* Interrupt disable mask for UFSHCI v1.1 */
0298     INTERRUPT_MASK_ALL_VER_11   = 0x31FFF,
0299
0300     /* Interrupt disable mask for UFSHCI v2.1 */
0301     INTERRUPT_MASK_ALL_VER_21   = 0x71FFF,
0302 };
0303
0304 /* CCAP - Crypto Capability 100h */
0305 union ufs_crypto_capabilities {
0306     __le32 reg_val;
0307     struct {
0308         u8 num_crypto_cap;
0309         u8 config_count;
0310         u8 reserved;
0311         u8 config_array_ptr;
0312     };
0313 };
0314
0315 enum ufs_crypto_key_size {
0316     UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
0317     UFS_CRYPTO_KEY_SIZE_128     = 0x1,
0318     UFS_CRYPTO_KEY_SIZE_192     = 0x2,
0319     UFS_CRYPTO_KEY_SIZE_256     = 0x3,
0320     UFS_CRYPTO_KEY_SIZE_512     = 0x4,
0321 };
0322
0323 enum ufs_crypto_alg {
0324     UFS_CRYPTO_ALG_AES_XTS          = 0x0,
0325     UFS_CRYPTO_ALG_BITLOCKER_AES_CBC    = 0x1,
0326     UFS_CRYPTO_ALG_AES_ECB          = 0x2,
0327     UFS_CRYPTO_ALG_ESSIV_AES_CBC        = 0x3,
0328 };
0329
0330 /* x-CRYPTOCAP - Crypto Capability X */
0331 union ufs_crypto_cap_entry {
0332     __le32 reg_val;
0333     struct {
0334         u8 algorithm_id;
0335         u8 sdus_mask; /* Supported data unit size mask */
0336         u8 key_size;
0337         u8 reserved;
0338     };
0339 };
0340
0341 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
0342 #define UFS_CRYPTO_KEY_MAX_SIZE 64
0343 /* x-CRYPTOCFG - Crypto Configuration X */
0344 union ufs_crypto_cfg_entry {
0345     __le32 reg_val[32];
0346     struct {
0347         u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
0348         u8 data_unit_size;
0349         u8 crypto_cap_idx;
0350         u8 reserved_1;
0351         u8 config_enable;
0352         u8 reserved_multi_host;
0353         u8 reserved_2;
0354         u8 vsb[2];
0355         u8 reserved_3[56];
0356     };
0357 };
0358
0359 /*
0360  * Request Descriptor Definitions
0361  */
0362
0363 /* Transfer request command type */
0364 enum {
0365     UTP_CMD_TYPE_SCSI       = 0x0,
0366     UTP_CMD_TYPE_UFS        = 0x1,
0367     UTP_CMD_TYPE_DEV_MANAGE     = 0x2,
0368 };
0369
0370 /* To accommodate UFS2.0 required Command type */
0371 enum {
0372     UTP_CMD_TYPE_UFS_STORAGE    = 0x1,
0373 };
0374
0375 enum {
0376     UTP_SCSI_COMMAND        = 0x00000000,
0377     UTP_NATIVE_UFS_COMMAND      = 0x10000000,
0378     UTP_DEVICE_MANAGEMENT_FUNCTION  = 0x20000000,
0379     UTP_REQ_DESC_INT_CMD        = 0x01000000,
0380     UTP_REQ_DESC_CRYPTO_ENABLE_CMD  = 0x00800000,
0381 };
0382
0383 /* UTP Transfer Request Data Direction (DD) */
0384 enum {
0385     UTP_NO_DATA_TRANSFER    = 0x00000000,
0386     UTP_HOST_TO_DEVICE  = 0x02000000,
0387     UTP_DEVICE_TO_HOST  = 0x04000000,
0388 };
0389
0390 /* Overall command status values */
0391 enum utp_ocs {
0392     OCS_SUCCESS         = 0x0,
0393     OCS_INVALID_CMD_TABLE_ATTR  = 0x1,
0394     OCS_INVALID_PRDT_ATTR       = 0x2,
0395     OCS_MISMATCH_DATA_BUF_SIZE  = 0x3,
0396     OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
0397     OCS_PEER_COMM_FAILURE       = 0x5,
0398     OCS_ABORTED         = 0x6,
0399     OCS_FATAL_ERROR         = 0x7,
0400     OCS_DEVICE_FATAL_ERROR      = 0x8,
0401     OCS_INVALID_CRYPTO_CONFIG   = 0x9,
0402     OCS_GENERAL_CRYPTO_ERROR    = 0xA,
0403     OCS_INVALID_COMMAND_STATUS  = 0x0F,
0404 };
0405
0406 enum {
0407     MASK_OCS            = 0x0F,
0408 };
0409
0410 /* The maximum length of the data byte count field in the PRDT is 256KB */
0411 #define PRDT_DATA_BYTE_COUNT_MAX    (256 * 1024)
0412 /* The granularity of the data byte count field in the PRDT is 32-bit */
0413 #define PRDT_DATA_BYTE_COUNT_PAD    4
0414
0415 /**
0416  * struct ufshcd_sg_entry - UFSHCI PRD Entry
0417  * @addr: Physical address; DW-0 and DW-1.
0418  * @reserved: Reserved for future use DW-2
0419  * @size: size of physical segment DW-3
0420  */
0421 struct ufshcd_sg_entry {
0422     __le64    addr;
0423     __le32    reserved;
0424     __le32    size;
0425 };
0426
0427 /**
0428  * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
0429  * @command_upiu: Command UPIU Frame address
0430  * @response_upiu: Response UPIU Frame address
0431  * @prd_table: Physical Region Descriptor
0432  */
0433 struct utp_transfer_cmd_desc {
0434     u8 command_upiu[ALIGNED_UPIU_SIZE];
0435     u8 response_upiu[ALIGNED_UPIU_SIZE];
0436     struct ufshcd_sg_entry    prd_table[SG_ALL];
0437 };
0438
0439 /**
0440  * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
0441  * @dword0: Descriptor Header DW0
0442  * @dword1: Descriptor Header DW1
0443  * @dword2: Descriptor Header DW2
0444  * @dword3: Descriptor Header DW3
0445  */
0446 struct request_desc_header {
0447     __le32 dword_0;
0448     __le32 dword_1;
0449     __le32 dword_2;
0450     __le32 dword_3;
0451 };
0452
0453 /**
0454  * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
0455  * @header: UTRD header DW-0 to DW-3
0456  * @command_desc_base_addr_lo: UCD base address low DW-4
0457  * @command_desc_base_addr_hi: UCD base address high DW-5
0458  * @response_upiu_length: response UPIU length DW-6
0459  * @response_upiu_offset: response UPIU offset DW-6
0460  * @prd_table_length: Physical region descriptor length DW-7
0461  * @prd_table_offset: Physical region descriptor offset DW-7
0462  */
0463 struct utp_transfer_req_desc {
0464
0465     /* DW 0-3 */
0466     struct request_desc_header header;
0467
0468     /* DW 4-5*/
0469     __le32  command_desc_base_addr_lo;
0470     __le32  command_desc_base_addr_hi;
0471
0472     /* DW 6 */
0473     __le16  response_upiu_length;
0474     __le16  response_upiu_offset;
0475
0476     /* DW 7 */
0477     __le16  prd_table_length;
0478     __le16  prd_table_offset;
0479 };
0480
0481 /*
0482  * UTMRD structure.
0483  */
0484 struct utp_task_req_desc {
0485     /* DW 0-3 */
0486     struct request_desc_header header;
0487
0488     /* DW 4-11 - Task request UPIU structure */
0489     struct {
0490         struct utp_upiu_header  req_header;
0491         __be32          input_param1;
0492         __be32          input_param2;
0493         __be32          input_param3;
0494         __be32          __reserved1[2];
0495     } upiu_req;
0496
0497     /* DW 12-19 - Task Management Response UPIU structure */
0498     struct {
0499         struct utp_upiu_header  rsp_header;
0500         __be32          output_param1;
0501         __be32          output_param2;
0502         __be32          __reserved2[3];
0503     } upiu_rsp;
0504 };
0505
0506 #endif /* End of Header */