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0011 #ifndef _UFS_H
0012 #define _UFS_H
0013
0014 #include <linux/mutex.h>
0015 #include <linux/types.h>
0016 #include <uapi/scsi/scsi_bsg_ufs.h>
0017
0018 #define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
0019 #define QUERY_DESC_MAX_SIZE 255
0020 #define QUERY_DESC_MIN_SIZE 2
0021 #define QUERY_DESC_HDR_SIZE 2
0022 #define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
0023 (sizeof(struct utp_upiu_header)))
0024 #define UFS_SENSE_SIZE 18
0025
0026 #define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
0027 cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
0028 (byte1 << 8) | (byte0))
0029
0030
0031
0032
0033
0034
0035
0036
0037
0038 #define UFS_UPIU_MAX_UNIT_NUM_ID 0x7F
0039 #define UFS_MAX_LUNS (SCSI_W_LUN_BASE + UFS_UPIU_MAX_UNIT_NUM_ID)
0040 #define UFS_UPIU_WLUN_ID (1 << 7)
0041 #define UFS_RPMB_UNIT 0xC4
0042
0043
0044 #define UFS_UPIU_MAX_WB_LUN_ID 8
0045
0046
0047
0048
0049
0050 #define UFS_WB_EXCEED_LIFETIME 0x0B
0051
0052
0053 enum {
0054 UFS_UPIU_REPORT_LUNS_WLUN = 0x81,
0055 UFS_UPIU_UFS_DEVICE_WLUN = 0xD0,
0056 UFS_UPIU_BOOT_WLUN = 0xB0,
0057 UFS_UPIU_RPMB_WLUN = 0xC4,
0058 };
0059
0060
0061
0062
0063
0064
0065 enum {
0066 UFS_ABORT_TASK = 0x01,
0067 UFS_ABORT_TASK_SET = 0x02,
0068 UFS_CLEAR_TASK_SET = 0x04,
0069 UFS_LOGICAL_RESET = 0x08,
0070 UFS_QUERY_TASK = 0x80,
0071 UFS_QUERY_TASK_SET = 0x81,
0072 };
0073
0074
0075 enum {
0076 UPIU_TRANSACTION_NOP_OUT = 0x00,
0077 UPIU_TRANSACTION_COMMAND = 0x01,
0078 UPIU_TRANSACTION_DATA_OUT = 0x02,
0079 UPIU_TRANSACTION_TASK_REQ = 0x04,
0080 UPIU_TRANSACTION_QUERY_REQ = 0x16,
0081 };
0082
0083
0084 enum {
0085 UPIU_TRANSACTION_NOP_IN = 0x20,
0086 UPIU_TRANSACTION_RESPONSE = 0x21,
0087 UPIU_TRANSACTION_DATA_IN = 0x22,
0088 UPIU_TRANSACTION_TASK_RSP = 0x24,
0089 UPIU_TRANSACTION_READY_XFER = 0x31,
0090 UPIU_TRANSACTION_QUERY_RSP = 0x36,
0091 UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
0092 };
0093
0094
0095 enum {
0096 UPIU_CMD_FLAGS_NONE = 0x00,
0097 UPIU_CMD_FLAGS_WRITE = 0x20,
0098 UPIU_CMD_FLAGS_READ = 0x40,
0099 };
0100
0101
0102 enum {
0103 UPIU_TASK_ATTR_SIMPLE = 0x00,
0104 UPIU_TASK_ATTR_ORDERED = 0x01,
0105 UPIU_TASK_ATTR_HEADQ = 0x02,
0106 UPIU_TASK_ATTR_ACA = 0x03,
0107 };
0108
0109
0110 enum {
0111 UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
0112 UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
0113 };
0114
0115
0116 enum flag_idn {
0117 QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
0118 QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
0119 QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
0120 QUERY_FLAG_IDN_BKOPS_EN = 0x04,
0121 QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
0122 QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
0123 QUERY_FLAG_IDN_RESERVED2 = 0x07,
0124 QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
0125 QUERY_FLAG_IDN_BUSY_RTC = 0x09,
0126 QUERY_FLAG_IDN_RESERVED3 = 0x0A,
0127 QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
0128 QUERY_FLAG_IDN_WB_EN = 0x0E,
0129 QUERY_FLAG_IDN_WB_BUFF_FLUSH_EN = 0x0F,
0130 QUERY_FLAG_IDN_WB_BUFF_FLUSH_DURING_HIBERN8 = 0x10,
0131 QUERY_FLAG_IDN_HPB_RESET = 0x11,
0132 QUERY_FLAG_IDN_HPB_EN = 0x12,
0133 };
0134
0135
0136 enum attr_idn {
0137 QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
0138 QUERY_ATTR_IDN_MAX_HPB_SINGLE_CMD = 0x01,
0139 QUERY_ATTR_IDN_POWER_MODE = 0x02,
0140 QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
0141 QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
0142 QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
0143 QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
0144 QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
0145 QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
0146 QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
0147 QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
0148 QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
0149 QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
0150 QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
0151 QUERY_ATTR_IDN_EE_STATUS = 0x0E,
0152 QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
0153 QUERY_ATTR_IDN_CNTX_CONF = 0x10,
0154 QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
0155 QUERY_ATTR_IDN_RESERVED2 = 0x12,
0156 QUERY_ATTR_IDN_RESERVED3 = 0x13,
0157 QUERY_ATTR_IDN_FFU_STATUS = 0x14,
0158 QUERY_ATTR_IDN_PSA_STATE = 0x15,
0159 QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
0160 QUERY_ATTR_IDN_REF_CLK_GATING_WAIT_TIME = 0x17,
0161 QUERY_ATTR_IDN_CASE_ROUGH_TEMP = 0x18,
0162 QUERY_ATTR_IDN_HIGH_TEMP_BOUND = 0x19,
0163 QUERY_ATTR_IDN_LOW_TEMP_BOUND = 0x1A,
0164 QUERY_ATTR_IDN_WB_FLUSH_STATUS = 0x1C,
0165 QUERY_ATTR_IDN_AVAIL_WB_BUFF_SIZE = 0x1D,
0166 QUERY_ATTR_IDN_WB_BUFF_LIFE_TIME_EST = 0x1E,
0167 QUERY_ATTR_IDN_CURR_WB_BUFF_SIZE = 0x1F,
0168 };
0169
0170
0171 enum desc_idn {
0172 QUERY_DESC_IDN_DEVICE = 0x0,
0173 QUERY_DESC_IDN_CONFIGURATION = 0x1,
0174 QUERY_DESC_IDN_UNIT = 0x2,
0175 QUERY_DESC_IDN_RFU_0 = 0x3,
0176 QUERY_DESC_IDN_INTERCONNECT = 0x4,
0177 QUERY_DESC_IDN_STRING = 0x5,
0178 QUERY_DESC_IDN_RFU_1 = 0x6,
0179 QUERY_DESC_IDN_GEOMETRY = 0x7,
0180 QUERY_DESC_IDN_POWER = 0x8,
0181 QUERY_DESC_IDN_HEALTH = 0x9,
0182 QUERY_DESC_IDN_MAX,
0183 };
0184
0185 enum desc_header_offset {
0186 QUERY_DESC_LENGTH_OFFSET = 0x00,
0187 QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
0188 };
0189
0190
0191 enum unit_desc_param {
0192 UNIT_DESC_PARAM_LEN = 0x0,
0193 UNIT_DESC_PARAM_TYPE = 0x1,
0194 UNIT_DESC_PARAM_UNIT_INDEX = 0x2,
0195 UNIT_DESC_PARAM_LU_ENABLE = 0x3,
0196 UNIT_DESC_PARAM_BOOT_LUN_ID = 0x4,
0197 UNIT_DESC_PARAM_LU_WR_PROTECT = 0x5,
0198 UNIT_DESC_PARAM_LU_Q_DEPTH = 0x6,
0199 UNIT_DESC_PARAM_PSA_SENSITIVE = 0x7,
0200 UNIT_DESC_PARAM_MEM_TYPE = 0x8,
0201 UNIT_DESC_PARAM_DATA_RELIABILITY = 0x9,
0202 UNIT_DESC_PARAM_LOGICAL_BLK_SIZE = 0xA,
0203 UNIT_DESC_PARAM_LOGICAL_BLK_COUNT = 0xB,
0204 UNIT_DESC_PARAM_ERASE_BLK_SIZE = 0x13,
0205 UNIT_DESC_PARAM_PROVISIONING_TYPE = 0x17,
0206 UNIT_DESC_PARAM_PHY_MEM_RSRC_CNT = 0x18,
0207 UNIT_DESC_PARAM_CTX_CAPABILITIES = 0x20,
0208 UNIT_DESC_PARAM_LARGE_UNIT_SIZE_M1 = 0x22,
0209 UNIT_DESC_PARAM_HPB_LU_MAX_ACTIVE_RGNS = 0x23,
0210 UNIT_DESC_PARAM_HPB_PIN_RGN_START_OFF = 0x25,
0211 UNIT_DESC_PARAM_HPB_NUM_PIN_RGNS = 0x27,
0212 UNIT_DESC_PARAM_WB_BUF_ALLOC_UNITS = 0x29,
0213 };
0214
0215
0216 enum device_desc_param {
0217 DEVICE_DESC_PARAM_LEN = 0x0,
0218 DEVICE_DESC_PARAM_TYPE = 0x1,
0219 DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
0220 DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
0221 DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
0222 DEVICE_DESC_PARAM_PRTCL = 0x5,
0223 DEVICE_DESC_PARAM_NUM_LU = 0x6,
0224 DEVICE_DESC_PARAM_NUM_WLU = 0x7,
0225 DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
0226 DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
0227 DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
0228 DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
0229 DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
0230 DEVICE_DESC_PARAM_SEC_LU = 0xD,
0231 DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
0232 DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
0233 DEVICE_DESC_PARAM_SPEC_VER = 0x10,
0234 DEVICE_DESC_PARAM_MANF_DATE = 0x12,
0235 DEVICE_DESC_PARAM_MANF_NAME = 0x14,
0236 DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
0237 DEVICE_DESC_PARAM_SN = 0x16,
0238 DEVICE_DESC_PARAM_OEM_ID = 0x17,
0239 DEVICE_DESC_PARAM_MANF_ID = 0x18,
0240 DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
0241 DEVICE_DESC_PARAM_UD_LEN = 0x1B,
0242 DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
0243 DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
0244 DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
0245 DEVICE_DESC_PARAM_FFU_TMT = 0x20,
0246 DEVICE_DESC_PARAM_Q_DPTH = 0x21,
0247 DEVICE_DESC_PARAM_DEV_VER = 0x22,
0248 DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
0249 DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
0250 DEVICE_DESC_PARAM_PSA_TMT = 0x29,
0251 DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
0252 DEVICE_DESC_PARAM_HPB_VER = 0x40,
0253 DEVICE_DESC_PARAM_HPB_CONTROL = 0x42,
0254 DEVICE_DESC_PARAM_EXT_UFS_FEATURE_SUP = 0x4F,
0255 DEVICE_DESC_PARAM_WB_PRESRV_USRSPC_EN = 0x53,
0256 DEVICE_DESC_PARAM_WB_TYPE = 0x54,
0257 DEVICE_DESC_PARAM_WB_SHARED_ALLOC_UNITS = 0x55,
0258 };
0259
0260
0261 enum interconnect_desc_param {
0262 INTERCONNECT_DESC_PARAM_LEN = 0x0,
0263 INTERCONNECT_DESC_PARAM_TYPE = 0x1,
0264 INTERCONNECT_DESC_PARAM_UNIPRO_VER = 0x2,
0265 INTERCONNECT_DESC_PARAM_MPHY_VER = 0x4,
0266 };
0267
0268
0269 enum geometry_desc_param {
0270 GEOMETRY_DESC_PARAM_LEN = 0x0,
0271 GEOMETRY_DESC_PARAM_TYPE = 0x1,
0272 GEOMETRY_DESC_PARAM_DEV_CAP = 0x4,
0273 GEOMETRY_DESC_PARAM_MAX_NUM_LUN = 0xC,
0274 GEOMETRY_DESC_PARAM_SEG_SIZE = 0xD,
0275 GEOMETRY_DESC_PARAM_ALLOC_UNIT_SIZE = 0x11,
0276 GEOMETRY_DESC_PARAM_MIN_BLK_SIZE = 0x12,
0277 GEOMETRY_DESC_PARAM_OPT_RD_BLK_SIZE = 0x13,
0278 GEOMETRY_DESC_PARAM_OPT_WR_BLK_SIZE = 0x14,
0279 GEOMETRY_DESC_PARAM_MAX_IN_BUF_SIZE = 0x15,
0280 GEOMETRY_DESC_PARAM_MAX_OUT_BUF_SIZE = 0x16,
0281 GEOMETRY_DESC_PARAM_RPMB_RW_SIZE = 0x17,
0282 GEOMETRY_DESC_PARAM_DYN_CAP_RSRC_PLC = 0x18,
0283 GEOMETRY_DESC_PARAM_DATA_ORDER = 0x19,
0284 GEOMETRY_DESC_PARAM_MAX_NUM_CTX = 0x1A,
0285 GEOMETRY_DESC_PARAM_TAG_UNIT_SIZE = 0x1B,
0286 GEOMETRY_DESC_PARAM_TAG_RSRC_SIZE = 0x1C,
0287 GEOMETRY_DESC_PARAM_SEC_RM_TYPES = 0x1D,
0288 GEOMETRY_DESC_PARAM_MEM_TYPES = 0x1E,
0289 GEOMETRY_DESC_PARAM_SCM_MAX_NUM_UNITS = 0x20,
0290 GEOMETRY_DESC_PARAM_SCM_CAP_ADJ_FCTR = 0x24,
0291 GEOMETRY_DESC_PARAM_NPM_MAX_NUM_UNITS = 0x26,
0292 GEOMETRY_DESC_PARAM_NPM_CAP_ADJ_FCTR = 0x2A,
0293 GEOMETRY_DESC_PARAM_ENM1_MAX_NUM_UNITS = 0x2C,
0294 GEOMETRY_DESC_PARAM_ENM1_CAP_ADJ_FCTR = 0x30,
0295 GEOMETRY_DESC_PARAM_ENM2_MAX_NUM_UNITS = 0x32,
0296 GEOMETRY_DESC_PARAM_ENM2_CAP_ADJ_FCTR = 0x36,
0297 GEOMETRY_DESC_PARAM_ENM3_MAX_NUM_UNITS = 0x38,
0298 GEOMETRY_DESC_PARAM_ENM3_CAP_ADJ_FCTR = 0x3C,
0299 GEOMETRY_DESC_PARAM_ENM4_MAX_NUM_UNITS = 0x3E,
0300 GEOMETRY_DESC_PARAM_ENM4_CAP_ADJ_FCTR = 0x42,
0301 GEOMETRY_DESC_PARAM_OPT_LOG_BLK_SIZE = 0x44,
0302 GEOMETRY_DESC_PARAM_HPB_REGION_SIZE = 0x48,
0303 GEOMETRY_DESC_PARAM_HPB_NUMBER_LU = 0x49,
0304 GEOMETRY_DESC_PARAM_HPB_SUBREGION_SIZE = 0x4A,
0305 GEOMETRY_DESC_PARAM_HPB_MAX_ACTIVE_REGS = 0x4B,
0306 GEOMETRY_DESC_PARAM_WB_MAX_ALLOC_UNITS = 0x4F,
0307 GEOMETRY_DESC_PARAM_WB_MAX_WB_LUNS = 0x53,
0308 GEOMETRY_DESC_PARAM_WB_BUFF_CAP_ADJ = 0x54,
0309 GEOMETRY_DESC_PARAM_WB_SUP_RED_TYPE = 0x55,
0310 GEOMETRY_DESC_PARAM_WB_SUP_WB_TYPE = 0x56,
0311 };
0312
0313
0314 enum health_desc_param {
0315 HEALTH_DESC_PARAM_LEN = 0x0,
0316 HEALTH_DESC_PARAM_TYPE = 0x1,
0317 HEALTH_DESC_PARAM_EOL_INFO = 0x2,
0318 HEALTH_DESC_PARAM_LIFE_TIME_EST_A = 0x3,
0319 HEALTH_DESC_PARAM_LIFE_TIME_EST_B = 0x4,
0320 };
0321
0322
0323 enum {
0324 WB_BUF_MODE_LU_DEDICATED = 0x0,
0325 WB_BUF_MODE_SHARED = 0x1,
0326 };
0327
0328
0329
0330
0331
0332
0333
0334 enum ufs_lu_wp_type {
0335 UFS_LU_NO_WP = 0x00,
0336 UFS_LU_POWER_ON_WP = 0x01,
0337 UFS_LU_PERM_WP = 0x02,
0338 };
0339
0340
0341 enum {
0342 UFSHCD_NANO_AMP = 0,
0343 UFSHCD_MICRO_AMP = 1,
0344 UFSHCD_MILI_AMP = 2,
0345 UFSHCD_AMP = 3,
0346 };
0347
0348
0349 enum {
0350 UFS_DEV_LOW_TEMP_NOTIF = BIT(4),
0351 UFS_DEV_HIGH_TEMP_NOTIF = BIT(5),
0352 UFS_DEV_EXT_TEMP_NOTIF = BIT(6),
0353 UFS_DEV_HPB_SUPPORT = BIT(7),
0354 UFS_DEV_WRITE_BOOSTER_SUP = BIT(8),
0355 };
0356 #define UFS_DEV_HPB_SUPPORT_VERSION 0x310
0357
0358 #define POWER_DESC_MAX_ACTV_ICC_LVLS 16
0359
0360
0361 #define ATTR_ICC_LVL_UNIT_OFFSET 14
0362 #define ATTR_ICC_LVL_UNIT_MASK (0x3 << ATTR_ICC_LVL_UNIT_OFFSET)
0363 #define ATTR_ICC_LVL_VALUE_MASK 0x3FF
0364
0365
0366 enum power_desc_param_offset {
0367 PWR_DESC_LEN = 0x0,
0368 PWR_DESC_TYPE = 0x1,
0369 PWR_DESC_ACTIVE_LVLS_VCC_0 = 0x2,
0370 PWR_DESC_ACTIVE_LVLS_VCCQ_0 = 0x22,
0371 PWR_DESC_ACTIVE_LVLS_VCCQ2_0 = 0x42,
0372 };
0373
0374
0375 enum {
0376 MASK_EE_STATUS = 0xFFFF,
0377 MASK_EE_DYNCAP_EVENT = BIT(0),
0378 MASK_EE_SYSPOOL_EVENT = BIT(1),
0379 MASK_EE_URGENT_BKOPS = BIT(2),
0380 MASK_EE_TOO_HIGH_TEMP = BIT(3),
0381 MASK_EE_TOO_LOW_TEMP = BIT(4),
0382 MASK_EE_WRITEBOOSTER_EVENT = BIT(5),
0383 MASK_EE_PERFORMANCE_THROTTLING = BIT(6),
0384 };
0385 #define MASK_EE_URGENT_TEMP (MASK_EE_TOO_HIGH_TEMP | MASK_EE_TOO_LOW_TEMP)
0386
0387
0388 enum bkops_status {
0389 BKOPS_STATUS_NO_OP = 0x0,
0390 BKOPS_STATUS_NON_CRITICAL = 0x1,
0391 BKOPS_STATUS_PERF_IMPACT = 0x2,
0392 BKOPS_STATUS_CRITICAL = 0x3,
0393 BKOPS_STATUS_MAX = BKOPS_STATUS_CRITICAL,
0394 };
0395
0396
0397 enum query_opcode {
0398 UPIU_QUERY_OPCODE_NOP = 0x0,
0399 UPIU_QUERY_OPCODE_READ_DESC = 0x1,
0400 UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
0401 UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
0402 UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
0403 UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
0404 UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
0405 UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
0406 UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
0407 };
0408
0409
0410 enum ufs_ref_clk_freq {
0411 REF_CLK_FREQ_19_2_MHZ = 0,
0412 REF_CLK_FREQ_26_MHZ = 1,
0413 REF_CLK_FREQ_38_4_MHZ = 2,
0414 REF_CLK_FREQ_52_MHZ = 3,
0415 REF_CLK_FREQ_INVAL = -1,
0416 };
0417
0418
0419 enum {
0420 QUERY_RESULT_SUCCESS = 0x00,
0421 QUERY_RESULT_NOT_READABLE = 0xF6,
0422 QUERY_RESULT_NOT_WRITEABLE = 0xF7,
0423 QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
0424 QUERY_RESULT_INVALID_LENGTH = 0xF9,
0425 QUERY_RESULT_INVALID_VALUE = 0xFA,
0426 QUERY_RESULT_INVALID_SELECTOR = 0xFB,
0427 QUERY_RESULT_INVALID_INDEX = 0xFC,
0428 QUERY_RESULT_INVALID_IDN = 0xFD,
0429 QUERY_RESULT_INVALID_OPCODE = 0xFE,
0430 QUERY_RESULT_GENERAL_FAILURE = 0xFF,
0431 };
0432
0433
0434 enum {
0435 UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
0436 UPIU_COMMAND_SET_TYPE_UFS = 0x1,
0437 UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
0438 };
0439
0440
0441 #define UPIU_COMMAND_TYPE_OFFSET 28
0442
0443
0444 #define UPIU_RSP_CODE_OFFSET 8
0445
0446 enum {
0447 MASK_SCSI_STATUS = 0xFF,
0448 MASK_TASK_RESPONSE = 0xFF00,
0449 MASK_RSP_UPIU_RESULT = 0xFFFF,
0450 MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
0451 MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
0452 MASK_RSP_EXCEPTION_EVENT = 0x10000,
0453 MASK_TM_SERVICE_RESP = 0xFF,
0454 MASK_TM_FUNC = 0xFF,
0455 };
0456
0457
0458 enum {
0459 UPIU_TASK_MANAGEMENT_FUNC_COMPL = 0x00,
0460 UPIU_TASK_MANAGEMENT_FUNC_NOT_SUPPORTED = 0x04,
0461 UPIU_TASK_MANAGEMENT_FUNC_SUCCEEDED = 0x08,
0462 UPIU_TASK_MANAGEMENT_FUNC_FAILED = 0x05,
0463 UPIU_INCORRECT_LOGICAL_UNIT_NO = 0x09,
0464 };
0465
0466
0467 enum ufs_dev_pwr_mode {
0468 UFS_ACTIVE_PWR_MODE = 1,
0469 UFS_SLEEP_PWR_MODE = 2,
0470 UFS_POWERDOWN_PWR_MODE = 3,
0471 UFS_DEEPSLEEP_PWR_MODE = 4,
0472 };
0473
0474 #define UFS_WB_BUF_REMAIN_PERCENT(val) ((val) / 10)
0475
0476
0477
0478
0479
0480
0481
0482
0483 struct utp_cmd_rsp {
0484 __be32 residual_transfer_count;
0485 __be32 reserved[4];
0486 __be16 sense_data_len;
0487 u8 sense_data[UFS_SENSE_SIZE];
0488 };
0489
0490 struct ufshpb_active_field {
0491 __be16 active_rgn;
0492 __be16 active_srgn;
0493 };
0494 #define HPB_ACT_FIELD_SIZE 4
0495
0496
0497
0498
0499
0500
0501
0502
0503
0504
0505
0506
0507
0508
0509
0510 struct utp_hpb_rsp {
0511 __be32 residual_transfer_count;
0512 __be32 reserved1[4];
0513 __be16 sense_data_len;
0514 u8 desc_type;
0515 u8 additional_len;
0516 u8 hpb_op;
0517 u8 lun;
0518 u8 active_rgn_cnt;
0519 u8 inactive_rgn_cnt;
0520 struct ufshpb_active_field hpb_active_field[2];
0521 __be16 hpb_inactive_field[2];
0522 };
0523 #define UTP_HPB_RSP_SIZE 40
0524
0525
0526
0527
0528
0529
0530
0531 struct utp_upiu_rsp {
0532 struct utp_upiu_header header;
0533 union {
0534 struct utp_cmd_rsp sr;
0535 struct utp_hpb_rsp hr;
0536 struct utp_upiu_query qr;
0537 };
0538 };
0539
0540
0541
0542
0543
0544
0545 struct ufs_query_req {
0546 u8 query_func;
0547 struct utp_upiu_query upiu_req;
0548 };
0549
0550
0551
0552
0553
0554
0555 struct ufs_query_res {
0556 u8 response;
0557 struct utp_upiu_query upiu_res;
0558 };
0559
0560
0561
0562
0563
0564 #define UFS_VREG_LPM_LOAD_UA 1000
0565
0566 struct ufs_vreg {
0567 struct regulator *reg;
0568 const char *name;
0569 bool always_on;
0570 bool enabled;
0571 int max_uA;
0572 };
0573
0574 struct ufs_vreg_info {
0575 struct ufs_vreg *vcc;
0576 struct ufs_vreg *vccq;
0577 struct ufs_vreg *vccq2;
0578 struct ufs_vreg *vdd_hba;
0579 };
0580
0581 struct ufs_dev_info {
0582 bool f_power_on_wp_en;
0583
0584 bool is_lu_power_on_wp;
0585
0586 u8 max_lu_supported;
0587 u16 wmanufacturerid;
0588
0589 u8 *model;
0590 u16 wspecversion;
0591 u32 clk_gating_wait_us;
0592
0593
0594 bool hpb_enabled;
0595
0596
0597 bool wb_enabled;
0598 bool wb_buf_flush_enabled;
0599 u8 wb_dedicated_lu;
0600 u8 wb_buffer_type;
0601
0602 bool b_rpm_dev_flush_capable;
0603 u8 b_presrv_uspc_en;
0604 };
0605
0606
0607
0608
0609 enum ufs_trace_str_t {
0610 UFS_CMD_SEND, UFS_CMD_COMP, UFS_DEV_COMP,
0611 UFS_QUERY_SEND, UFS_QUERY_COMP, UFS_QUERY_ERR,
0612 UFS_TM_SEND, UFS_TM_COMP, UFS_TM_ERR
0613 };
0614
0615
0616
0617
0618
0619 enum ufs_trace_tsf_t {
0620 UFS_TSF_CDB, UFS_TSF_OSF, UFS_TSF_TM_INPUT, UFS_TSF_TM_OUTPUT
0621 };
0622
0623 #endif