uapi/sound/skl-tplg-interface.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * skl-tplg-interface.h - Intel DSP FW private data interface
0004  *
0005  * Copyright (C) 2015 Intel Corp
0006  * Author: Jeeja KP <jeeja.kp@intel.com>
0007  *      Nilofer, Samreen <samreen.nilofer@intel.com>
0008  */
0009
0010 #ifndef __HDA_TPLG_INTERFACE_H__
0011 #define __HDA_TPLG_INTERFACE_H__
0012
0013 #include <linux/types.h>
0014
0015 /*
0016  * Default types range from 0~12. type can range from 0 to 0xff
0017  * SST types start at higher to avoid any overlapping in future
0018  */
0019 #define SKL_CONTROL_TYPE_BYTE_TLV   0x100
0020 #define SKL_CONTROL_TYPE_MIC_SELECT 0x102
0021 #define SKL_CONTROL_TYPE_MULTI_IO_SELECT    0x103
0022 #define SKL_CONTROL_TYPE_MULTI_IO_SELECT_DMIC   0x104
0023
0024 #define HDA_SST_CFG_MAX 900 /* size of copier cfg*/
0025 #define MAX_IN_QUEUE 8
0026 #define MAX_OUT_QUEUE 8
0027
0028 #define SKL_UUID_STR_SZ 40
0029 /* Event types goes here */
0030 /* Reserve event type 0 for no event handlers */
0031 enum skl_event_types {
0032     SKL_EVENT_NONE = 0,
0033     SKL_MIXER_EVENT,
0034     SKL_MUX_EVENT,
0035     SKL_VMIXER_EVENT,
0036     SKL_PGA_EVENT
0037 };
0038
0039 /**
0040  * enum skl_ch_cfg - channel configuration
0041  *
0042  * @SKL_CH_CFG_MONO:    One channel only
0043  * @SKL_CH_CFG_STEREO:  L & R
0044  * @SKL_CH_CFG_2_1: L, R & LFE
0045  * @SKL_CH_CFG_3_0: L, C & R
0046  * @SKL_CH_CFG_3_1: L, C, R & LFE
0047  * @SKL_CH_CFG_QUATRO:  L, R, Ls & Rs
0048  * @SKL_CH_CFG_4_0: L, C, R & Cs
0049  * @SKL_CH_CFG_5_0: L, C, R, Ls & Rs
0050  * @SKL_CH_CFG_5_1: L, C, R, Ls, Rs & LFE
0051  * @SKL_CH_CFG_DUAL_MONO: One channel replicated in two
0052  * @SKL_CH_CFG_I2S_DUAL_STEREO_0: Stereo(L,R) in 4 slots, 1st stream:[ L, R, -, - ]
0053  * @SKL_CH_CFG_I2S_DUAL_STEREO_1: Stereo(L,R) in 4 slots, 2nd stream:[ -, -, L, R ]
0054  * @SKL_CH_CFG_INVALID: Invalid
0055  */
0056 enum skl_ch_cfg {
0057     SKL_CH_CFG_MONO = 0,
0058     SKL_CH_CFG_STEREO = 1,
0059     SKL_CH_CFG_2_1 = 2,
0060     SKL_CH_CFG_3_0 = 3,
0061     SKL_CH_CFG_3_1 = 4,
0062     SKL_CH_CFG_QUATRO = 5,
0063     SKL_CH_CFG_4_0 = 6,
0064     SKL_CH_CFG_5_0 = 7,
0065     SKL_CH_CFG_5_1 = 8,
0066     SKL_CH_CFG_DUAL_MONO = 9,
0067     SKL_CH_CFG_I2S_DUAL_STEREO_0 = 10,
0068     SKL_CH_CFG_I2S_DUAL_STEREO_1 = 11,
0069     SKL_CH_CFG_4_CHANNEL = 12,
0070     SKL_CH_CFG_INVALID
0071 };
0072
0073 enum skl_module_type {
0074     SKL_MODULE_TYPE_MIXER = 0,
0075     SKL_MODULE_TYPE_COPIER,
0076     SKL_MODULE_TYPE_UPDWMIX,
0077     SKL_MODULE_TYPE_SRCINT,
0078     SKL_MODULE_TYPE_ALGO,
0079     SKL_MODULE_TYPE_BASE_OUTFMT,
0080     SKL_MODULE_TYPE_KPB,
0081     SKL_MODULE_TYPE_MIC_SELECT,
0082 };
0083
0084 enum skl_core_affinity {
0085     SKL_AFFINITY_CORE_0 = 0,
0086     SKL_AFFINITY_CORE_1,
0087     SKL_AFFINITY_CORE_MAX
0088 };
0089
0090 enum skl_pipe_conn_type {
0091     SKL_PIPE_CONN_TYPE_NONE = 0,
0092     SKL_PIPE_CONN_TYPE_FE,
0093     SKL_PIPE_CONN_TYPE_BE
0094 };
0095
0096 enum skl_hw_conn_type {
0097     SKL_CONN_NONE = 0,
0098     SKL_CONN_SOURCE = 1,
0099     SKL_CONN_SINK = 2
0100 };
0101
0102 enum skl_dev_type {
0103     SKL_DEVICE_BT = 0x0,
0104     SKL_DEVICE_DMIC = 0x1,
0105     SKL_DEVICE_I2S = 0x2,
0106     SKL_DEVICE_SLIMBUS = 0x3,
0107     SKL_DEVICE_HDALINK = 0x4,
0108     SKL_DEVICE_HDAHOST = 0x5,
0109     SKL_DEVICE_NONE
0110 };
0111
0112 /**
0113  * enum skl_interleaving - interleaving style
0114  *
0115  * @SKL_INTERLEAVING_PER_CHANNEL: [s1_ch1...s1_chN,...,sM_ch1...sM_chN]
0116  * @SKL_INTERLEAVING_PER_SAMPLE: [s1_ch1...sM_ch1,...,s1_chN...sM_chN]
0117  */
0118 enum skl_interleaving {
0119     SKL_INTERLEAVING_PER_CHANNEL = 0,
0120     SKL_INTERLEAVING_PER_SAMPLE = 1,
0121 };
0122
0123 enum skl_sample_type {
0124     SKL_SAMPLE_TYPE_INT_MSB = 0,
0125     SKL_SAMPLE_TYPE_INT_LSB = 1,
0126     SKL_SAMPLE_TYPE_INT_SIGNED = 2,
0127     SKL_SAMPLE_TYPE_INT_UNSIGNED = 3,
0128     SKL_SAMPLE_TYPE_FLOAT = 4
0129 };
0130
0131 enum module_pin_type {
0132     /* All pins of the module takes same PCM inputs or outputs
0133     * e.g. mixout
0134     */
0135     SKL_PIN_TYPE_HOMOGENEOUS,
0136     /* All pins of the module takes different PCM inputs or outputs
0137     * e.g mux
0138     */
0139     SKL_PIN_TYPE_HETEROGENEOUS,
0140 };
0141
0142 enum skl_module_param_type {
0143     SKL_PARAM_DEFAULT = 0,
0144     SKL_PARAM_INIT,
0145     SKL_PARAM_SET,
0146     SKL_PARAM_BIND
0147 };
0148
0149 struct skl_dfw_algo_data {
0150     __u32 set_params:2;
0151     __u32 rsvd:30;
0152     __u32 param_id;
0153     __u32 max;
0154     char params[];
0155 } __packed;
0156
0157 enum skl_tkn_dir {
0158     SKL_DIR_IN,
0159     SKL_DIR_OUT
0160 };
0161
0162 enum skl_tuple_type {
0163     SKL_TYPE_TUPLE,
0164     SKL_TYPE_DATA
0165 };
0166
0167 /* v4 configuration data */
0168
0169 struct skl_dfw_v4_module_pin {
0170     __u16 module_id;
0171     __u16 instance_id;
0172 } __packed;
0173
0174 struct skl_dfw_v4_module_fmt {
0175     __u32 channels;
0176     __u32 freq;
0177     __u32 bit_depth;
0178     __u32 valid_bit_depth;
0179     __u32 ch_cfg;
0180     __u32 interleaving_style;
0181     __u32 sample_type;
0182     __u32 ch_map;
0183 } __packed;
0184
0185 struct skl_dfw_v4_module_caps {
0186     __u32 set_params:2;
0187     __u32 rsvd:30;
0188     __u32 param_id;
0189     __u32 caps_size;
0190     __u32 caps[HDA_SST_CFG_MAX];
0191 } __packed;
0192
0193 struct skl_dfw_v4_pipe {
0194     __u8 pipe_id;
0195     __u8 pipe_priority;
0196     __u16 conn_type:4;
0197     __u16 rsvd:4;
0198     __u16 memory_pages:8;
0199 } __packed;
0200
0201 struct skl_dfw_v4_module {
0202     char uuid[SKL_UUID_STR_SZ];
0203
0204     __u16 module_id;
0205     __u16 instance_id;
0206     __u32 max_mcps;
0207     __u32 mem_pages;
0208     __u32 obs;
0209     __u32 ibs;
0210     __u32 vbus_id;
0211
0212     __u32 max_in_queue:8;
0213     __u32 max_out_queue:8;
0214     __u32 time_slot:8;
0215     __u32 core_id:4;
0216     __u32 rsvd1:4;
0217
0218     __u32 module_type:8;
0219     __u32 conn_type:4;
0220     __u32 dev_type:4;
0221     __u32 hw_conn_type:4;
0222     __u32 rsvd2:12;
0223
0224     __u32 params_fixup:8;
0225     __u32 converter:8;
0226     __u32 input_pin_type:1;
0227     __u32 output_pin_type:1;
0228     __u32 is_dynamic_in_pin:1;
0229     __u32 is_dynamic_out_pin:1;
0230     __u32 is_loadable:1;
0231     __u32 rsvd3:11;
0232
0233     struct skl_dfw_v4_pipe pipe;
0234     struct skl_dfw_v4_module_fmt in_fmt[MAX_IN_QUEUE];
0235     struct skl_dfw_v4_module_fmt out_fmt[MAX_OUT_QUEUE];
0236     struct skl_dfw_v4_module_pin in_pin[MAX_IN_QUEUE];
0237     struct skl_dfw_v4_module_pin out_pin[MAX_OUT_QUEUE];
0238     struct skl_dfw_v4_module_caps caps;
0239 } __packed;
0240
0241 #endif