uapi/sound/emu10k1.h

0001 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
0002 /*
0003  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
0004  *           Creative Labs, Inc.
0005  *  Definitions for EMU10K1 (SB Live!) chips
0006  *
0007  *
0008  *   This program is free software; you can redistribute it and/or modify
0009  *   it under the terms of the GNU General Public License as published by
0010  *   the Free Software Foundation; either version 2 of the License, or
0011  *   (at your option) any later version.
0012  *
0013  *   This program is distributed in the hope that it will be useful,
0014  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
0015  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0016  *   GNU General Public License for more details.
0017  *
0018  *   You should have received a copy of the GNU General Public License
0019  *   along with this program; if not, write to the Free Software
0020  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
0021  *
0022  */
0023 #ifndef _UAPI__SOUND_EMU10K1_H
0024 #define _UAPI__SOUND_EMU10K1_H
0025
0026 #ifdef __linux__
0027 #include <linux/types.h>
0028 #endif
0029
0030 /*
0031  * ---- FX8010 ----
0032  */
0033
0034 #define EMU10K1_CARD_CREATIVE           0x00000000
0035 #define EMU10K1_CARD_EMUAPS         0x00000001
0036
0037 #define EMU10K1_FX8010_PCM_COUNT        8
0038
0039 /*
0040  * Following definition is copied from linux/types.h to support compiling
0041  * this header file in userspace since they are not generally available for
0042  * uapi headers.
0043  */
0044 #define __EMU10K1_DECLARE_BITMAP(name,bits) \
0045     unsigned long name[(bits) / (sizeof(unsigned long) * 8)]
0046
0047 /* instruction set */
0048 #define iMAC0    0x00   /* R = A + (X * Y >> 31)   ; saturation */
0049 #define iMAC1    0x01   /* R = A + (-X * Y >> 31)  ; saturation */
0050 #define iMAC2    0x02   /* R = A + (X * Y >> 31)   ; wraparound */
0051 #define iMAC3    0x03   /* R = A + (-X * Y >> 31)  ; wraparound */
0052 #define iMACINT0 0x04   /* R = A + X * Y       ; saturation */
0053 #define iMACINT1 0x05   /* R = A + X * Y       ; wraparound (31-bit) */
0054 #define iACC3    0x06   /* R = A + X + Y       ; saturation */
0055 #define iMACMV   0x07   /* R = A, acc += X * Y >> 31 */
0056 #define iANDXOR  0x08   /* R = (A & X) ^ Y */
0057 #define iTSTNEG  0x09   /* R = (A >= Y) ? X : ~X */
0058 #define iLIMITGE 0x0a   /* R = (A >= Y) ? X : Y */
0059 #define iLIMITLT 0x0b   /* R = (A < Y) ? X : Y */
0060 #define iLOG     0x0c   /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
0061 #define iEXP     0x0d   /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
0062 #define iINTERP  0x0e   /* R = A + (X * (Y - A) >> 31)  ; saturation */
0063 #define iSKIP    0x0f   /* R = A (cc_reg), X (count), Y (cc_test) */
0064
0065 /* GPRs */
0066 #define FXBUS(x)    (0x00 + (x))    /* x = 0x00 - 0x0f */
0067 #define EXTIN(x)    (0x10 + (x))    /* x = 0x00 - 0x0f */
0068 #define EXTOUT(x)   (0x20 + (x))    /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
0069 #define FXBUS2(x)   (0x30 + (x))    /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
0070                     /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
0071
0072 #define C_00000000  0x40
0073 #define C_00000001  0x41
0074 #define C_00000002  0x42
0075 #define C_00000003  0x43
0076 #define C_00000004  0x44
0077 #define C_00000008  0x45
0078 #define C_00000010  0x46
0079 #define C_00000020  0x47
0080 #define C_00000100  0x48
0081 #define C_00010000  0x49
0082 #define C_00080000  0x4a
0083 #define C_10000000  0x4b
0084 #define C_20000000  0x4c
0085 #define C_40000000  0x4d
0086 #define C_80000000  0x4e
0087 #define C_7fffffff  0x4f
0088 #define C_ffffffff  0x50
0089 #define C_fffffffe  0x51
0090 #define C_c0000000  0x52
0091 #define C_4f1bbcdc  0x53
0092 #define C_5a7ef9db  0x54
0093 #define C_00100000  0x55        /* ?? */
0094 #define GPR_ACCU    0x56        /* ACCUM, accumulator */
0095 #define GPR_COND    0x57        /* CCR, condition register */
0096 #define GPR_NOISE0  0x58        /* noise source */
0097 #define GPR_NOISE1  0x59        /* noise source */
0098 #define GPR_IRQ     0x5a        /* IRQ register */
0099 #define GPR_DBAC    0x5b        /* TRAM Delay Base Address Counter */
0100 #define GPR(x)      (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
0101 #define ITRAM_DATA(x)   (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
0102 #define ETRAM_DATA(x)   (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
0103 #define ITRAM_ADDR(x)   (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
0104 #define ETRAM_ADDR(x)   (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
0105
0106 #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
0107 #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
0108 #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
0109 #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
0110 #define A_ITRAM_CTL(x)  (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
0111 #define A_ETRAM_CTL(x)  (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
0112
0113 #define A_FXBUS(x)  (0x00 + (x))    /* x = 0x00 - 0x3f FX buses */
0114 #define A_EXTIN(x)  (0x40 + (x))    /* x = 0x00 - 0x0f physical ins */
0115 #define A_P16VIN(x) (0x50 + (x))    /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
0116 #define A_EXTOUT(x) (0x60 + (x))    /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown   */
0117 #define A_FXBUS2(x) (0x80 + (x))    /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
0118 #define A_EMU32OUTH(x)  (0xa0 + (x))    /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
0119 #define A_EMU32OUTL(x)  (0xb0 + (x))    /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
0120 #define A3_EMU32IN(x)   (0x160 + (x))   /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */
0121 #define A3_EMU32OUT(x)  (0x1E0 + (x))   /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */
0122 #define A_GPR(x)    (A_FXGPREGBASE + (x))
0123
0124 /* cc_reg constants */
0125 #define CC_REG_NORMALIZED C_00000001
0126 #define CC_REG_BORROW   C_00000002
0127 #define CC_REG_MINUS    C_00000004
0128 #define CC_REG_ZERO C_00000008
0129 #define CC_REG_SATURATE C_00000010
0130 #define CC_REG_NONZERO  C_00000100
0131
0132 /* FX buses */
0133 #define FXBUS_PCM_LEFT      0x00
0134 #define FXBUS_PCM_RIGHT     0x01
0135 #define FXBUS_PCM_LEFT_REAR 0x02
0136 #define FXBUS_PCM_RIGHT_REAR    0x03
0137 #define FXBUS_MIDI_LEFT     0x04
0138 #define FXBUS_MIDI_RIGHT    0x05
0139 #define FXBUS_PCM_CENTER    0x06
0140 #define FXBUS_PCM_LFE       0x07
0141 #define FXBUS_PCM_LEFT_FRONT    0x08
0142 #define FXBUS_PCM_RIGHT_FRONT   0x09
0143 #define FXBUS_MIDI_REVERB   0x0c
0144 #define FXBUS_MIDI_CHORUS   0x0d
0145 #define FXBUS_PCM_LEFT_SIDE 0x0e
0146 #define FXBUS_PCM_RIGHT_SIDE    0x0f
0147 #define FXBUS_PT_LEFT       0x14
0148 #define FXBUS_PT_RIGHT      0x15
0149
0150 /* Inputs */
0151 #define EXTIN_AC97_L       0x00 /* AC'97 capture channel - left */
0152 #define EXTIN_AC97_R       0x01 /* AC'97 capture channel - right */
0153 #define EXTIN_SPDIF_CD_L   0x02 /* internal S/PDIF CD - onboard - left */
0154 #define EXTIN_SPDIF_CD_R   0x03 /* internal S/PDIF CD - onboard - right */
0155 #define EXTIN_ZOOM_L       0x04 /* Zoom Video I2S - left */
0156 #define EXTIN_ZOOM_R       0x05 /* Zoom Video I2S - right */
0157 #define EXTIN_TOSLINK_L    0x06 /* LiveDrive - TOSLink Optical - left */
0158 #define EXTIN_TOSLINK_R    0x07 /* LiveDrive - TOSLink Optical - right */
0159 #define EXTIN_LINE1_L      0x08 /* LiveDrive - Line/Mic 1 - left */
0160 #define EXTIN_LINE1_R      0x09 /* LiveDrive - Line/Mic 1 - right */
0161 #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
0162 #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
0163 #define EXTIN_LINE2_L      0x0c /* LiveDrive - Line/Mic 2 - left */
0164 #define EXTIN_LINE2_R      0x0d /* LiveDrive - Line/Mic 2 - right */
0165
0166 /* Outputs */
0167 #define EXTOUT_AC97_L      0x00 /* AC'97 playback channel - left */
0168 #define EXTOUT_AC97_R      0x01 /* AC'97 playback channel - right */
0169 #define EXTOUT_TOSLINK_L   0x02 /* LiveDrive - TOSLink Optical - left */
0170 #define EXTOUT_TOSLINK_R   0x03 /* LiveDrive - TOSLink Optical - right */
0171 #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
0172 #define EXTOUT_AC97_LFE    0x05 /* SB Live 5.1 - LFE */
0173 #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
0174 #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
0175 #define EXTOUT_REAR_L      0x08 /* Rear channel - left */
0176 #define EXTOUT_REAR_R      0x09 /* Rear channel - right */
0177 #define EXTOUT_ADC_CAP_L   0x0a /* ADC Capture buffer - left */
0178 #define EXTOUT_ADC_CAP_R   0x0b /* ADC Capture buffer - right */
0179 #define EXTOUT_MIC_CAP     0x0c /* MIC Capture buffer */
0180 #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
0181 #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
0182 #define EXTOUT_ACENTER     0x11 /* Analog Center */
0183 #define EXTOUT_ALFE    0x12 /* Analog LFE */
0184
0185 /* Audigy Inputs */
0186 #define A_EXTIN_AC97_L      0x00    /* AC'97 capture channel - left */
0187 #define A_EXTIN_AC97_R      0x01    /* AC'97 capture channel - right */
0188 #define A_EXTIN_SPDIF_CD_L  0x02    /* digital CD left */
0189 #define A_EXTIN_SPDIF_CD_R  0x03    /* digital CD left */
0190 #define A_EXTIN_OPT_SPDIF_L     0x04    /* audigy drive Optical SPDIF - left */
0191 #define A_EXTIN_OPT_SPDIF_R     0x05    /*                              right */
0192 #define A_EXTIN_LINE2_L     0x08    /* audigy drive line2/mic2 - left */
0193 #define A_EXTIN_LINE2_R     0x09    /*                           right */
0194 #define A_EXTIN_ADC_L       0x0a    /* Philips ADC - left */
0195 #define A_EXTIN_ADC_R       0x0b    /*               right */
0196 #define A_EXTIN_AUX2_L      0x0c    /* audigy drive aux2 - left */
0197 #define A_EXTIN_AUX2_R      0x0d    /*                   - right */
0198
0199 /* Audigiy Outputs */
0200 #define A_EXTOUT_FRONT_L    0x00    /* digital front left */
0201 #define A_EXTOUT_FRONT_R    0x01    /*               right */
0202 #define A_EXTOUT_CENTER     0x02    /* digital front center */
0203 #define A_EXTOUT_LFE        0x03    /* digital front lfe */
0204 #define A_EXTOUT_HEADPHONE_L    0x04    /* headphone audigy drive left */
0205 #define A_EXTOUT_HEADPHONE_R    0x05    /*                        right */
0206 #define A_EXTOUT_REAR_L     0x06    /* digital rear left */
0207 #define A_EXTOUT_REAR_R     0x07    /*              right */
0208 #define A_EXTOUT_AFRONT_L   0x08    /* analog front left */
0209 #define A_EXTOUT_AFRONT_R   0x09    /*              right */
0210 #define A_EXTOUT_ACENTER    0x0a    /* analog center */
0211 #define A_EXTOUT_ALFE       0x0b    /* analog LFE */
0212 #define A_EXTOUT_ASIDE_L    0x0c    /* analog side left  - Audigy 2 ZS */
0213 #define A_EXTOUT_ASIDE_R    0x0d    /*             right - Audigy 2 ZS */
0214 #define A_EXTOUT_AREAR_L    0x0e    /* analog rear left */
0215 #define A_EXTOUT_AREAR_R    0x0f    /*             right */
0216 #define A_EXTOUT_AC97_L     0x10    /* AC97 left (front) */
0217 #define A_EXTOUT_AC97_R     0x11    /*      right */
0218 #define A_EXTOUT_ADC_CAP_L  0x16    /* ADC capture buffer left */
0219 #define A_EXTOUT_ADC_CAP_R  0x17    /*                    right */
0220 #define A_EXTOUT_MIC_CAP    0x18    /* Mic capture buffer */
0221
0222 /* Audigy constants */
0223 #define A_C_00000000    0xc0
0224 #define A_C_00000001    0xc1
0225 #define A_C_00000002    0xc2
0226 #define A_C_00000003    0xc3
0227 #define A_C_00000004    0xc4
0228 #define A_C_00000008    0xc5
0229 #define A_C_00000010    0xc6
0230 #define A_C_00000020    0xc7
0231 #define A_C_00000100    0xc8
0232 #define A_C_00010000    0xc9
0233 #define A_C_00000800    0xca
0234 #define A_C_10000000    0xcb
0235 #define A_C_20000000    0xcc
0236 #define A_C_40000000    0xcd
0237 #define A_C_80000000    0xce
0238 #define A_C_7fffffff    0xcf
0239 #define A_C_ffffffff    0xd0
0240 #define A_C_fffffffe    0xd1
0241 #define A_C_c0000000    0xd2
0242 #define A_C_4f1bbcdc    0xd3
0243 #define A_C_5a7ef9db    0xd4
0244 #define A_C_00100000    0xd5
0245 #define A_GPR_ACCU  0xd6        /* ACCUM, accumulator */
0246 #define A_GPR_COND  0xd7        /* CCR, condition register */
0247 #define A_GPR_NOISE0    0xd8        /* noise source */
0248 #define A_GPR_NOISE1    0xd9        /* noise source */
0249 #define A_GPR_IRQ   0xda        /* IRQ register */
0250 #define A_GPR_DBAC  0xdb        /* TRAM Delay Base Address Counter - internal */
0251 #define A_GPR_DBACE 0xde        /* TRAM Delay Base Address Counter - external */
0252
0253 /* definitions for debug register */
0254 #define EMU10K1_DBG_ZC          0x80000000  /* zero tram counter */
0255 #define EMU10K1_DBG_SATURATION_OCCURED  0x02000000  /* saturation control */
0256 #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000  /* saturation address */
0257 #define EMU10K1_DBG_SINGLE_STEP     0x00008000  /* single step mode */
0258 #define EMU10K1_DBG_STEP        0x00004000  /* start single step */
0259 #define EMU10K1_DBG_CONDITION_CODE  0x00003e00  /* condition code */
0260 #define EMU10K1_DBG_SINGLE_STEP_ADDR    0x000001ff  /* single step address */
0261
0262 /* tank memory address line */
0263 #ifndef __KERNEL__
0264 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field            */
0265 #define TANKMEMADDRREG_CLEAR     0x00800000 /* Clear tank memory                */
0266 #define TANKMEMADDRREG_ALIGN     0x00400000 /* Align read or write relative to tank access  */
0267 #define TANKMEMADDRREG_WRITE     0x00200000 /* Write to tank memory             */
0268 #define TANKMEMADDRREG_READ  0x00100000 /* Read from tank memory            */
0269 #endif
0270
0271 struct snd_emu10k1_fx8010_info {
0272     unsigned int internal_tram_size;    /* in samples */
0273     unsigned int external_tram_size;    /* in samples */
0274     char fxbus_names[16][32];       /* names of FXBUSes */
0275     char extin_names[16][32];       /* names of external inputs */
0276     char extout_names[32][32];      /* names of external outputs */
0277     unsigned int gpr_controls;      /* count of GPR controls */
0278 };
0279
0280 #define EMU10K1_GPR_TRANSLATION_NONE        0
0281 #define EMU10K1_GPR_TRANSLATION_TABLE100    1
0282 #define EMU10K1_GPR_TRANSLATION_BASS        2
0283 #define EMU10K1_GPR_TRANSLATION_TREBLE      3
0284 #define EMU10K1_GPR_TRANSLATION_ONOFF       4
0285
0286 enum emu10k1_ctl_elem_iface {
0287     EMU10K1_CTL_ELEM_IFACE_MIXER = 2,   /* virtual mixer device */
0288     EMU10K1_CTL_ELEM_IFACE_PCM = 3,     /* PCM device */
0289 };
0290
0291 struct emu10k1_ctl_elem_id {
0292     unsigned int pad;       /* don't use */
0293     int iface;          /* interface identifier */
0294     unsigned int device;        /* device/client number */
0295     unsigned int subdevice;     /* subdevice (substream) number */
0296     unsigned char name[44];     /* ASCII name of item */
0297     unsigned int index;     /* index of item */
0298 };
0299
0300 struct snd_emu10k1_fx8010_control_gpr {
0301     struct emu10k1_ctl_elem_id id;  /* full control ID definition */
0302     unsigned int vcount;        /* visible count */
0303     unsigned int count;     /* count of GPR (1..16) */
0304     unsigned short gpr[32];     /* GPR number(s) */
0305     unsigned int value[32];     /* initial values */
0306     unsigned int min;       /* minimum range */
0307     unsigned int max;       /* maximum range */
0308     unsigned int translation;   /* translation type (EMU10K1_GPR_TRANSLATION*) */
0309     const unsigned int *tlv;
0310 };
0311
0312 /* old ABI without TLV support */
0313 struct snd_emu10k1_fx8010_control_old_gpr {
0314     struct emu10k1_ctl_elem_id id;
0315     unsigned int vcount;
0316     unsigned int count;
0317     unsigned short gpr[32];
0318     unsigned int value[32];
0319     unsigned int min;
0320     unsigned int max;
0321     unsigned int translation;
0322 };
0323
0324 struct snd_emu10k1_fx8010_code {
0325     char name[128];
0326
0327     __EMU10K1_DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
0328     __u32 *gpr_map;         /* initializers */
0329
0330     unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
0331     struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */
0332
0333     unsigned int gpr_del_control_count; /* count of GPR controls to remove */
0334     struct emu10k1_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */
0335
0336     unsigned int gpr_list_control_count; /* count of GPR controls to list */
0337     unsigned int gpr_list_control_total; /* total count of GPR controls */
0338     struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */
0339
0340     __EMU10K1_DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
0341     __u32 *tram_data_map;         /* data initializers */
0342     __u32 *tram_addr_map;         /* map initializers */
0343
0344     __EMU10K1_DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
0345     __u32 *code;              /* one instruction - 64 bits */
0346 };
0347
0348 struct snd_emu10k1_fx8010_tram {
0349     unsigned int address;       /* 31.bit == 1 -> external TRAM */
0350     unsigned int size;      /* size in samples (4 bytes) */
0351     unsigned int *samples;      /* pointer to samples (20-bit) */
0352                     /* NULL->clear memory */
0353 };
0354
0355 struct snd_emu10k1_fx8010_pcm_rec {
0356     unsigned int substream;     /* substream number */
0357     unsigned int res1;      /* reserved */
0358     unsigned int channels;      /* 16-bit channels count, zero = remove this substream */
0359     unsigned int tram_start;    /* ring buffer position in TRAM (in samples) */
0360     unsigned int buffer_size;   /* count of buffered samples */
0361     unsigned short gpr_size;        /* GPR containing size of ringbuffer in samples (host) */
0362     unsigned short gpr_ptr;     /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
0363     unsigned short gpr_count;   /* GPR containing count of samples between two interrupts (host) */
0364     unsigned short gpr_tmpcount;    /* GPR containing current count of samples to interrupt (host = set, FX8010) */
0365     unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
0366     unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
0367     unsigned char pad;      /* reserved */
0368     unsigned char etram[32];    /* external TRAM address & data (one per channel) */
0369     unsigned int res2;      /* reserved */
0370 };
0371
0372 #define SNDRV_EMU10K1_VERSION       SNDRV_PROTOCOL_VERSION(1, 0, 1)
0373
0374 #define SNDRV_EMU10K1_IOCTL_INFO    _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
0375 #define SNDRV_EMU10K1_IOCTL_CODE_POKE   _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
0376 #define SNDRV_EMU10K1_IOCTL_CODE_PEEK   _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
0377 #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP  _IOW ('H', 0x20, int)
0378 #define SNDRV_EMU10K1_IOCTL_TRAM_POKE   _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
0379 #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK   _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
0380 #define SNDRV_EMU10K1_IOCTL_PCM_POKE    _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
0381 #define SNDRV_EMU10K1_IOCTL_PCM_PEEK    _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
0382 #define SNDRV_EMU10K1_IOCTL_PVERSION    _IOR ('H', 0x40, int)
0383 #define SNDRV_EMU10K1_IOCTL_STOP    _IO  ('H', 0x80)
0384 #define SNDRV_EMU10K1_IOCTL_CONTINUE    _IO  ('H', 0x81)
0385 #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
0386 #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
0387 #define SNDRV_EMU10K1_IOCTL_DBG_READ    _IOR ('H', 0x84, int)
0388
0389 #endif /* _UAPI__SOUND_EMU10K1_H */