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0033 #ifndef __QEDR_USER_H__
0034 #define __QEDR_USER_H__
0035
0036 #include <linux/types.h>
0037
0038 #define QEDR_ABI_VERSION (8)
0039
0040
0041 enum qedr_alloc_ucontext_flags {
0042 QEDR_ALLOC_UCTX_EDPM_MODE = 1 << 0,
0043 QEDR_ALLOC_UCTX_DB_REC = 1 << 1,
0044 QEDR_SUPPORT_DPM_SIZES = 1 << 2,
0045 };
0046
0047 struct qedr_alloc_ucontext_req {
0048 __u32 context_flags;
0049 __u32 reserved;
0050 };
0051
0052 #define QEDR_LDPM_MAX_SIZE (8192)
0053 #define QEDR_EDPM_TRANS_SIZE (64)
0054 #define QEDR_EDPM_MAX_SIZE (ROCE_REQ_MAX_INLINE_DATA_SIZE)
0055
0056 enum qedr_rdma_dpm_type {
0057 QEDR_DPM_TYPE_NONE = 0,
0058 QEDR_DPM_TYPE_ROCE_ENHANCED = 1 << 0,
0059 QEDR_DPM_TYPE_ROCE_LEGACY = 1 << 1,
0060 QEDR_DPM_TYPE_IWARP_LEGACY = 1 << 2,
0061 QEDR_DPM_TYPE_ROCE_EDPM_MODE = 1 << 3,
0062 QEDR_DPM_SIZES_SET = 1 << 4,
0063 };
0064
0065 struct qedr_alloc_ucontext_resp {
0066 __aligned_u64 db_pa;
0067 __u32 db_size;
0068
0069 __u32 max_send_wr;
0070 __u32 max_recv_wr;
0071 __u32 max_srq_wr;
0072 __u32 sges_per_send_wr;
0073 __u32 sges_per_recv_wr;
0074 __u32 sges_per_srq_wr;
0075 __u32 max_cqes;
0076 __u8 dpm_flags;
0077 __u8 wids_enabled;
0078 __u16 wid_count;
0079 __u16 ldpm_limit_size;
0080 __u8 edpm_trans_size;
0081 __u8 reserved;
0082 __u16 edpm_limit_size;
0083 __u8 padding[6];
0084 };
0085
0086 struct qedr_alloc_pd_ureq {
0087 __aligned_u64 rsvd1;
0088 };
0089
0090 struct qedr_alloc_pd_uresp {
0091 __u32 pd_id;
0092 __u32 reserved;
0093 };
0094
0095 struct qedr_create_cq_ureq {
0096 __aligned_u64 addr;
0097 __aligned_u64 len;
0098 };
0099
0100 struct qedr_create_cq_uresp {
0101 __u32 db_offset;
0102 __u16 icid;
0103 __u16 reserved;
0104 __aligned_u64 db_rec_addr;
0105 };
0106
0107 struct qedr_create_qp_ureq {
0108 __u32 qp_handle_hi;
0109 __u32 qp_handle_lo;
0110
0111
0112
0113 __aligned_u64 sq_addr;
0114
0115
0116 __aligned_u64 sq_len;
0117
0118
0119
0120 __aligned_u64 rq_addr;
0121
0122
0123 __aligned_u64 rq_len;
0124 };
0125
0126 struct qedr_create_qp_uresp {
0127 __u32 qp_id;
0128 __u32 atomic_supported;
0129
0130
0131 __u32 sq_db_offset;
0132 __u16 sq_icid;
0133
0134
0135 __u32 rq_db_offset;
0136 __u16 rq_icid;
0137
0138 __u32 rq_db2_offset;
0139 __u32 reserved;
0140
0141
0142 __aligned_u64 sq_db_rec_addr;
0143
0144
0145 __aligned_u64 rq_db_rec_addr;
0146
0147 };
0148
0149 struct qedr_create_srq_ureq {
0150
0151 __aligned_u64 prod_pair_addr;
0152
0153
0154 __aligned_u64 srq_addr;
0155
0156
0157 __aligned_u64 srq_len;
0158 };
0159
0160 struct qedr_create_srq_uresp {
0161 __u16 srq_id;
0162 __u16 reserved0;
0163 __u32 reserved1;
0164 };
0165
0166
0167
0168
0169
0170 struct qedr_user_db_rec {
0171 __aligned_u64 db_data;
0172 };
0173
0174 #endif