uapi/linux/virtio_gpu.h

0001 /*
0002  * Virtio GPU Device
0003  *
0004  * Copyright Red Hat, Inc. 2013-2014
0005  *
0006  * Authors:
0007  *     Dave Airlie <airlied@redhat.com>
0008  *     Gerd Hoffmann <kraxel@redhat.com>
0009  *
0010  * This header is BSD licensed so anyone can use the definitions
0011  * to implement compatible drivers/servers:
0012  *
0013  * Redistribution and use in source and binary forms, with or without
0014  * modification, are permitted provided that the following conditions
0015  * are met:
0016  * 1. Redistributions of source code must retain the above copyright
0017  *    notice, this list of conditions and the following disclaimer.
0018  * 2. Redistributions in binary form must reproduce the above copyright
0019  *    notice, this list of conditions and the following disclaimer in the
0020  *    documentation and/or other materials provided with the distribution.
0021  * 3. Neither the name of IBM nor the names of its contributors
0022  *    may be used to endorse or promote products derived from this software
0023  *    without specific prior written permission.
0024  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
0025  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
0026  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
0027  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL IBM OR
0028  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
0029  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
0030  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
0031  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
0032  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
0033  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
0034  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
0035  * SUCH DAMAGE.
0036  */
0037
0038 #ifndef VIRTIO_GPU_HW_H
0039 #define VIRTIO_GPU_HW_H
0040
0041 #include <linux/types.h>
0042
0043 /*
0044  * VIRTIO_GPU_CMD_CTX_*
0045  * VIRTIO_GPU_CMD_*_3D
0046  */
0047 #define VIRTIO_GPU_F_VIRGL               0
0048
0049 /*
0050  * VIRTIO_GPU_CMD_GET_EDID
0051  */
0052 #define VIRTIO_GPU_F_EDID                1
0053 /*
0054  * VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID
0055  */
0056 #define VIRTIO_GPU_F_RESOURCE_UUID       2
0057
0058 /*
0059  * VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB
0060  */
0061 #define VIRTIO_GPU_F_RESOURCE_BLOB       3
0062 /*
0063  * VIRTIO_GPU_CMD_CREATE_CONTEXT with
0064  * context_init and multiple timelines
0065  */
0066 #define VIRTIO_GPU_F_CONTEXT_INIT        4
0067
0068 enum virtio_gpu_ctrl_type {
0069     VIRTIO_GPU_UNDEFINED = 0,
0070
0071     /* 2d commands */
0072     VIRTIO_GPU_CMD_GET_DISPLAY_INFO = 0x0100,
0073     VIRTIO_GPU_CMD_RESOURCE_CREATE_2D,
0074     VIRTIO_GPU_CMD_RESOURCE_UNREF,
0075     VIRTIO_GPU_CMD_SET_SCANOUT,
0076     VIRTIO_GPU_CMD_RESOURCE_FLUSH,
0077     VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D,
0078     VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING,
0079     VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING,
0080     VIRTIO_GPU_CMD_GET_CAPSET_INFO,
0081     VIRTIO_GPU_CMD_GET_CAPSET,
0082     VIRTIO_GPU_CMD_GET_EDID,
0083     VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID,
0084     VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB,
0085     VIRTIO_GPU_CMD_SET_SCANOUT_BLOB,
0086
0087     /* 3d commands */
0088     VIRTIO_GPU_CMD_CTX_CREATE = 0x0200,
0089     VIRTIO_GPU_CMD_CTX_DESTROY,
0090     VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE,
0091     VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE,
0092     VIRTIO_GPU_CMD_RESOURCE_CREATE_3D,
0093     VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D,
0094     VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D,
0095     VIRTIO_GPU_CMD_SUBMIT_3D,
0096     VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB,
0097     VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB,
0098
0099     /* cursor commands */
0100     VIRTIO_GPU_CMD_UPDATE_CURSOR = 0x0300,
0101     VIRTIO_GPU_CMD_MOVE_CURSOR,
0102
0103     /* success responses */
0104     VIRTIO_GPU_RESP_OK_NODATA = 0x1100,
0105     VIRTIO_GPU_RESP_OK_DISPLAY_INFO,
0106     VIRTIO_GPU_RESP_OK_CAPSET_INFO,
0107     VIRTIO_GPU_RESP_OK_CAPSET,
0108     VIRTIO_GPU_RESP_OK_EDID,
0109     VIRTIO_GPU_RESP_OK_RESOURCE_UUID,
0110     VIRTIO_GPU_RESP_OK_MAP_INFO,
0111
0112     /* error responses */
0113     VIRTIO_GPU_RESP_ERR_UNSPEC = 0x1200,
0114     VIRTIO_GPU_RESP_ERR_OUT_OF_MEMORY,
0115     VIRTIO_GPU_RESP_ERR_INVALID_SCANOUT_ID,
0116     VIRTIO_GPU_RESP_ERR_INVALID_RESOURCE_ID,
0117     VIRTIO_GPU_RESP_ERR_INVALID_CONTEXT_ID,
0118     VIRTIO_GPU_RESP_ERR_INVALID_PARAMETER,
0119 };
0120
0121 enum virtio_gpu_shm_id {
0122     VIRTIO_GPU_SHM_ID_UNDEFINED = 0,
0123     /*
0124      * VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB
0125      * VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB
0126      */
0127     VIRTIO_GPU_SHM_ID_HOST_VISIBLE = 1
0128 };
0129
0130 #define VIRTIO_GPU_FLAG_FENCE         (1 << 0)
0131 /*
0132  * If the following flag is set, then ring_idx contains the index
0133  * of the command ring that needs to used when creating the fence
0134  */
0135 #define VIRTIO_GPU_FLAG_INFO_RING_IDX (1 << 1)
0136
0137 struct virtio_gpu_ctrl_hdr {
0138     __le32 type;
0139     __le32 flags;
0140     __le64 fence_id;
0141     __le32 ctx_id;
0142     __u8 ring_idx;
0143     __u8 padding[3];
0144 };
0145
0146 /* data passed in the cursor vq */
0147
0148 struct virtio_gpu_cursor_pos {
0149     __le32 scanout_id;
0150     __le32 x;
0151     __le32 y;
0152     __le32 padding;
0153 };
0154
0155 /* VIRTIO_GPU_CMD_UPDATE_CURSOR, VIRTIO_GPU_CMD_MOVE_CURSOR */
0156 struct virtio_gpu_update_cursor {
0157     struct virtio_gpu_ctrl_hdr hdr;
0158     struct virtio_gpu_cursor_pos pos;  /* update & move */
0159     __le32 resource_id;           /* update only */
0160     __le32 hot_x;                 /* update only */
0161     __le32 hot_y;                 /* update only */
0162     __le32 padding;
0163 };
0164
0165 /* data passed in the control vq, 2d related */
0166
0167 struct virtio_gpu_rect {
0168     __le32 x;
0169     __le32 y;
0170     __le32 width;
0171     __le32 height;
0172 };
0173
0174 /* VIRTIO_GPU_CMD_RESOURCE_UNREF */
0175 struct virtio_gpu_resource_unref {
0176     struct virtio_gpu_ctrl_hdr hdr;
0177     __le32 resource_id;
0178     __le32 padding;
0179 };
0180
0181 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_2D: create a 2d resource with a format */
0182 struct virtio_gpu_resource_create_2d {
0183     struct virtio_gpu_ctrl_hdr hdr;
0184     __le32 resource_id;
0185     __le32 format;
0186     __le32 width;
0187     __le32 height;
0188 };
0189
0190 /* VIRTIO_GPU_CMD_SET_SCANOUT */
0191 struct virtio_gpu_set_scanout {
0192     struct virtio_gpu_ctrl_hdr hdr;
0193     struct virtio_gpu_rect r;
0194     __le32 scanout_id;
0195     __le32 resource_id;
0196 };
0197
0198 /* VIRTIO_GPU_CMD_RESOURCE_FLUSH */
0199 struct virtio_gpu_resource_flush {
0200     struct virtio_gpu_ctrl_hdr hdr;
0201     struct virtio_gpu_rect r;
0202     __le32 resource_id;
0203     __le32 padding;
0204 };
0205
0206 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_2D: simple transfer to_host */
0207 struct virtio_gpu_transfer_to_host_2d {
0208     struct virtio_gpu_ctrl_hdr hdr;
0209     struct virtio_gpu_rect r;
0210     __le64 offset;
0211     __le32 resource_id;
0212     __le32 padding;
0213 };
0214
0215 struct virtio_gpu_mem_entry {
0216     __le64 addr;
0217     __le32 length;
0218     __le32 padding;
0219 };
0220
0221 /* VIRTIO_GPU_CMD_RESOURCE_ATTACH_BACKING */
0222 struct virtio_gpu_resource_attach_backing {
0223     struct virtio_gpu_ctrl_hdr hdr;
0224     __le32 resource_id;
0225     __le32 nr_entries;
0226 };
0227
0228 /* VIRTIO_GPU_CMD_RESOURCE_DETACH_BACKING */
0229 struct virtio_gpu_resource_detach_backing {
0230     struct virtio_gpu_ctrl_hdr hdr;
0231     __le32 resource_id;
0232     __le32 padding;
0233 };
0234
0235 /* VIRTIO_GPU_RESP_OK_DISPLAY_INFO */
0236 #define VIRTIO_GPU_MAX_SCANOUTS 16
0237 struct virtio_gpu_resp_display_info {
0238     struct virtio_gpu_ctrl_hdr hdr;
0239     struct virtio_gpu_display_one {
0240         struct virtio_gpu_rect r;
0241         __le32 enabled;
0242         __le32 flags;
0243     } pmodes[VIRTIO_GPU_MAX_SCANOUTS];
0244 };
0245
0246 /* data passed in the control vq, 3d related */
0247
0248 struct virtio_gpu_box {
0249     __le32 x, y, z;
0250     __le32 w, h, d;
0251 };
0252
0253 /* VIRTIO_GPU_CMD_TRANSFER_TO_HOST_3D, VIRTIO_GPU_CMD_TRANSFER_FROM_HOST_3D */
0254 struct virtio_gpu_transfer_host_3d {
0255     struct virtio_gpu_ctrl_hdr hdr;
0256     struct virtio_gpu_box box;
0257     __le64 offset;
0258     __le32 resource_id;
0259     __le32 level;
0260     __le32 stride;
0261     __le32 layer_stride;
0262 };
0263
0264 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_3D */
0265 #define VIRTIO_GPU_RESOURCE_FLAG_Y_0_TOP (1 << 0)
0266 struct virtio_gpu_resource_create_3d {
0267     struct virtio_gpu_ctrl_hdr hdr;
0268     __le32 resource_id;
0269     __le32 target;
0270     __le32 format;
0271     __le32 bind;
0272     __le32 width;
0273     __le32 height;
0274     __le32 depth;
0275     __le32 array_size;
0276     __le32 last_level;
0277     __le32 nr_samples;
0278     __le32 flags;
0279     __le32 padding;
0280 };
0281
0282 /* VIRTIO_GPU_CMD_CTX_CREATE */
0283 #define VIRTIO_GPU_CONTEXT_INIT_CAPSET_ID_MASK 0x000000ff
0284 struct virtio_gpu_ctx_create {
0285     struct virtio_gpu_ctrl_hdr hdr;
0286     __le32 nlen;
0287     __le32 context_init;
0288     char debug_name[64];
0289 };
0290
0291 /* VIRTIO_GPU_CMD_CTX_DESTROY */
0292 struct virtio_gpu_ctx_destroy {
0293     struct virtio_gpu_ctrl_hdr hdr;
0294 };
0295
0296 /* VIRTIO_GPU_CMD_CTX_ATTACH_RESOURCE, VIRTIO_GPU_CMD_CTX_DETACH_RESOURCE */
0297 struct virtio_gpu_ctx_resource {
0298     struct virtio_gpu_ctrl_hdr hdr;
0299     __le32 resource_id;
0300     __le32 padding;
0301 };
0302
0303 /* VIRTIO_GPU_CMD_SUBMIT_3D */
0304 struct virtio_gpu_cmd_submit {
0305     struct virtio_gpu_ctrl_hdr hdr;
0306     __le32 size;
0307     __le32 padding;
0308 };
0309
0310 #define VIRTIO_GPU_CAPSET_VIRGL 1
0311 #define VIRTIO_GPU_CAPSET_VIRGL2 2
0312
0313 /* VIRTIO_GPU_CMD_GET_CAPSET_INFO */
0314 struct virtio_gpu_get_capset_info {
0315     struct virtio_gpu_ctrl_hdr hdr;
0316     __le32 capset_index;
0317     __le32 padding;
0318 };
0319
0320 /* VIRTIO_GPU_RESP_OK_CAPSET_INFO */
0321 struct virtio_gpu_resp_capset_info {
0322     struct virtio_gpu_ctrl_hdr hdr;
0323     __le32 capset_id;
0324     __le32 capset_max_version;
0325     __le32 capset_max_size;
0326     __le32 padding;
0327 };
0328
0329 /* VIRTIO_GPU_CMD_GET_CAPSET */
0330 struct virtio_gpu_get_capset {
0331     struct virtio_gpu_ctrl_hdr hdr;
0332     __le32 capset_id;
0333     __le32 capset_version;
0334 };
0335
0336 /* VIRTIO_GPU_RESP_OK_CAPSET */
0337 struct virtio_gpu_resp_capset {
0338     struct virtio_gpu_ctrl_hdr hdr;
0339     __u8 capset_data[];
0340 };
0341
0342 /* VIRTIO_GPU_CMD_GET_EDID */
0343 struct virtio_gpu_cmd_get_edid {
0344     struct virtio_gpu_ctrl_hdr hdr;
0345     __le32 scanout;
0346     __le32 padding;
0347 };
0348
0349 /* VIRTIO_GPU_RESP_OK_EDID */
0350 struct virtio_gpu_resp_edid {
0351     struct virtio_gpu_ctrl_hdr hdr;
0352     __le32 size;
0353     __le32 padding;
0354     __u8 edid[1024];
0355 };
0356
0357 #define VIRTIO_GPU_EVENT_DISPLAY (1 << 0)
0358
0359 struct virtio_gpu_config {
0360     __le32 events_read;
0361     __le32 events_clear;
0362     __le32 num_scanouts;
0363     __le32 num_capsets;
0364 };
0365
0366 /* simple formats for fbcon/X use */
0367 enum virtio_gpu_formats {
0368     VIRTIO_GPU_FORMAT_B8G8R8A8_UNORM  = 1,
0369     VIRTIO_GPU_FORMAT_B8G8R8X8_UNORM  = 2,
0370     VIRTIO_GPU_FORMAT_A8R8G8B8_UNORM  = 3,
0371     VIRTIO_GPU_FORMAT_X8R8G8B8_UNORM  = 4,
0372
0373     VIRTIO_GPU_FORMAT_R8G8B8A8_UNORM  = 67,
0374     VIRTIO_GPU_FORMAT_X8B8G8R8_UNORM  = 68,
0375
0376     VIRTIO_GPU_FORMAT_A8B8G8R8_UNORM  = 121,
0377     VIRTIO_GPU_FORMAT_R8G8B8X8_UNORM  = 134,
0378 };
0379
0380 /* VIRTIO_GPU_CMD_RESOURCE_ASSIGN_UUID */
0381 struct virtio_gpu_resource_assign_uuid {
0382     struct virtio_gpu_ctrl_hdr hdr;
0383     __le32 resource_id;
0384     __le32 padding;
0385 };
0386
0387 /* VIRTIO_GPU_RESP_OK_RESOURCE_UUID */
0388 struct virtio_gpu_resp_resource_uuid {
0389     struct virtio_gpu_ctrl_hdr hdr;
0390     __u8 uuid[16];
0391 };
0392
0393 /* VIRTIO_GPU_CMD_RESOURCE_CREATE_BLOB */
0394 struct virtio_gpu_resource_create_blob {
0395     struct virtio_gpu_ctrl_hdr hdr;
0396     __le32 resource_id;
0397 #define VIRTIO_GPU_BLOB_MEM_GUEST             0x0001
0398 #define VIRTIO_GPU_BLOB_MEM_HOST3D            0x0002
0399 #define VIRTIO_GPU_BLOB_MEM_HOST3D_GUEST      0x0003
0400
0401 #define VIRTIO_GPU_BLOB_FLAG_USE_MAPPABLE     0x0001
0402 #define VIRTIO_GPU_BLOB_FLAG_USE_SHAREABLE    0x0002
0403 #define VIRTIO_GPU_BLOB_FLAG_USE_CROSS_DEVICE 0x0004
0404     /* zero is invalid blob mem */
0405     __le32 blob_mem;
0406     __le32 blob_flags;
0407     __le32 nr_entries;
0408     __le64 blob_id;
0409     __le64 size;
0410     /*
0411      * sizeof(nr_entries * virtio_gpu_mem_entry) bytes follow
0412      */
0413 };
0414
0415 /* VIRTIO_GPU_CMD_SET_SCANOUT_BLOB */
0416 struct virtio_gpu_set_scanout_blob {
0417     struct virtio_gpu_ctrl_hdr hdr;
0418     struct virtio_gpu_rect r;
0419     __le32 scanout_id;
0420     __le32 resource_id;
0421     __le32 width;
0422     __le32 height;
0423     __le32 format;
0424     __le32 padding;
0425     __le32 strides[4];
0426     __le32 offsets[4];
0427 };
0428
0429 /* VIRTIO_GPU_CMD_RESOURCE_MAP_BLOB */
0430 struct virtio_gpu_resource_map_blob {
0431     struct virtio_gpu_ctrl_hdr hdr;
0432     __le32 resource_id;
0433     __le32 padding;
0434     __le64 offset;
0435 };
0436
0437 /* VIRTIO_GPU_RESP_OK_MAP_INFO */
0438 #define VIRTIO_GPU_MAP_CACHE_MASK     0x0f
0439 #define VIRTIO_GPU_MAP_CACHE_NONE     0x00
0440 #define VIRTIO_GPU_MAP_CACHE_CACHED   0x01
0441 #define VIRTIO_GPU_MAP_CACHE_UNCACHED 0x02
0442 #define VIRTIO_GPU_MAP_CACHE_WC       0x03
0443 struct virtio_gpu_resp_map_info {
0444     struct virtio_gpu_ctrl_hdr hdr;
0445     __u32 map_info;
0446     __u32 padding;
0447 };
0448
0449 /* VIRTIO_GPU_CMD_RESOURCE_UNMAP_BLOB */
0450 struct virtio_gpu_resource_unmap_blob {
0451     struct virtio_gpu_ctrl_hdr hdr;
0452     __le32 resource_id;
0453     __le32 padding;
0454 };
0455
0456 #endif