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0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * V4L2 DV timings header.
0004  *
0005  * Copyright (C) 2012-2016  Hans Verkuil <hans.verkuil@cisco.com>
0006  *
0007  * This program is free software; you can redistribute it and/or
0008  * modify it under the terms of the GNU General Public License
0009  * version 2 as published by the Free Software Foundation.
0010  *
0011  * This program is distributed in the hope that it will be useful, but
0012  * WITHOUT ANY WARRANTY; without even the implied warranty of
0013  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
0014  * General Public License for more details.
0015  */
0016 
0017 #ifndef _V4L2_DV_TIMINGS_H
0018 #define _V4L2_DV_TIMINGS_H
0019 
0020 #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
0021 /* Sadly gcc versions older than 4.6 have a bug in how they initialize
0022    anonymous unions where they require additional curly brackets.
0023    This violates the C1x standard. This workaround adds the curly brackets
0024    if needed. */
0025 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
0026     { .bt = { _width , ## args } }
0027 #else
0028 #define V4L2_INIT_BT_TIMINGS(_width, args...) \
0029     .bt = { _width , ## args }
0030 #endif
0031 
0032 /* CEA-861-F timings (i.e. standard HDTV timings) */
0033 
0034 #define V4L2_DV_BT_CEA_640X480P59_94 { \
0035     .type = V4L2_DV_BT_656_1120, \
0036     V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
0037         25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
0038         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
0039         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
0040 }
0041 
0042 /* Note: these are the nominal timings, for HDMI links this format is typically
0043  * double-clocked to meet the minimum pixelclock requirements.  */
0044 #define V4L2_DV_BT_CEA_720X480I59_94 { \
0045     .type = V4L2_DV_BT_656_1120, \
0046     V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
0047         13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
0048         V4L2_DV_BT_STD_CEA861, \
0049         V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
0050         V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
0051         { 4, 3 }, 6) \
0052 }
0053 
0054 #define V4L2_DV_BT_CEA_720X480P59_94 { \
0055     .type = V4L2_DV_BT_656_1120, \
0056     V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
0057         27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
0058         V4L2_DV_BT_STD_CEA861, \
0059         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
0060         V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
0061 }
0062 
0063 /* Note: these are the nominal timings, for HDMI links this format is typically
0064  * double-clocked to meet the minimum pixelclock requirements.  */
0065 #define V4L2_DV_BT_CEA_720X576I50 { \
0066     .type = V4L2_DV_BT_656_1120, \
0067     V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
0068         13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
0069         V4L2_DV_BT_STD_CEA861, \
0070         V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
0071         V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
0072         { 4, 3 }, 21) \
0073 }
0074 
0075 #define V4L2_DV_BT_CEA_720X576P50 { \
0076     .type = V4L2_DV_BT_656_1120, \
0077     V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
0078         27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
0079         V4L2_DV_BT_STD_CEA861, \
0080         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
0081         V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
0082 }
0083 
0084 #define V4L2_DV_BT_CEA_1280X720P24 { \
0085     .type = V4L2_DV_BT_656_1120, \
0086     V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
0087         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0088         59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
0089         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
0090         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
0091 }
0092 
0093 #define V4L2_DV_BT_CEA_1280X720P25 { \
0094     .type = V4L2_DV_BT_656_1120, \
0095     V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
0096         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0097         74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
0098         V4L2_DV_BT_STD_CEA861, \
0099         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
0100 }
0101 
0102 #define V4L2_DV_BT_CEA_1280X720P30 { \
0103     .type = V4L2_DV_BT_656_1120, \
0104     V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
0105         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0106         74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
0107         V4L2_DV_BT_STD_CEA861, \
0108         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0109         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
0110 }
0111 
0112 #define V4L2_DV_BT_CEA_1280X720P50 { \
0113     .type = V4L2_DV_BT_656_1120, \
0114     V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
0115         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0116         74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
0117         V4L2_DV_BT_STD_CEA861, \
0118         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
0119 }
0120 
0121 #define V4L2_DV_BT_CEA_1280X720P60 { \
0122     .type = V4L2_DV_BT_656_1120, \
0123     V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
0124         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0125         74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
0126         V4L2_DV_BT_STD_CEA861, \
0127         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0128         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
0129 }
0130 
0131 #define V4L2_DV_BT_CEA_1920X1080P24 { \
0132     .type = V4L2_DV_BT_656_1120, \
0133     V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
0134         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0135         74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
0136         V4L2_DV_BT_STD_CEA861, \
0137         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0138         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
0139 }
0140 
0141 #define V4L2_DV_BT_CEA_1920X1080P25 { \
0142     .type = V4L2_DV_BT_656_1120, \
0143     V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
0144         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0145         74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
0146         V4L2_DV_BT_STD_CEA861, \
0147         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
0148 }
0149 
0150 #define V4L2_DV_BT_CEA_1920X1080P30 { \
0151     .type = V4L2_DV_BT_656_1120, \
0152     V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
0153         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0154         74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
0155         V4L2_DV_BT_STD_CEA861, \
0156         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0157         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
0158 }
0159 
0160 #define V4L2_DV_BT_CEA_1920X1080I50 { \
0161     .type = V4L2_DV_BT_656_1120, \
0162     V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
0163         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0164         74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
0165         V4L2_DV_BT_STD_CEA861, \
0166         V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
0167         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
0168 }
0169 
0170 #define V4L2_DV_BT_CEA_1920X1080P50 { \
0171     .type = V4L2_DV_BT_656_1120, \
0172     V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
0173         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0174         148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
0175         V4L2_DV_BT_STD_CEA861, \
0176         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \
0177 }
0178 
0179 #define V4L2_DV_BT_CEA_1920X1080I60 { \
0180     .type = V4L2_DV_BT_656_1120, \
0181     V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
0182         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0183         74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
0184         V4L2_DV_BT_STD_CEA861, \
0185         V4L2_DV_FL_CAN_REDUCE_FPS | \
0186         V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
0187         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \
0188 }
0189 
0190 #define V4L2_DV_BT_CEA_1920X1080P60 { \
0191     .type = V4L2_DV_BT_656_1120, \
0192     V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
0193         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0194         148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
0195         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
0196         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0197         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \
0198 }
0199 
0200 #define V4L2_DV_BT_CEA_3840X2160P24 { \
0201     .type = V4L2_DV_BT_656_1120, \
0202     V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
0203         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0204         297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
0205         V4L2_DV_BT_STD_CEA861, \
0206         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0207         V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
0208         { 0, 0 }, 93, 3) \
0209 }
0210 
0211 #define V4L2_DV_BT_CEA_3840X2160P25 { \
0212     .type = V4L2_DV_BT_656_1120, \
0213     V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
0214         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0215         297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
0216         V4L2_DV_BT_STD_CEA861, \
0217         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \
0218         V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \
0219 }
0220 
0221 #define V4L2_DV_BT_CEA_3840X2160P30 { \
0222     .type = V4L2_DV_BT_656_1120, \
0223     V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
0224         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0225         297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
0226         V4L2_DV_BT_STD_CEA861, \
0227         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0228         V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
0229         { 0, 0 }, 95, 1) \
0230 }
0231 
0232 #define V4L2_DV_BT_CEA_3840X2160P50 { \
0233     .type = V4L2_DV_BT_656_1120, \
0234     V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
0235         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0236         594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
0237         V4L2_DV_BT_STD_CEA861, \
0238         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \
0239 }
0240 
0241 #define V4L2_DV_BT_CEA_3840X2160P60 { \
0242     .type = V4L2_DV_BT_656_1120, \
0243     V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
0244         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0245         594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
0246         V4L2_DV_BT_STD_CEA861, \
0247         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0248         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \
0249 }
0250 
0251 #define V4L2_DV_BT_CEA_4096X2160P24 { \
0252     .type = V4L2_DV_BT_656_1120, \
0253     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
0254         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0255         297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
0256         V4L2_DV_BT_STD_CEA861, \
0257         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0258         V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
0259         { 0, 0 }, 98, 4) \
0260 }
0261 
0262 #define V4L2_DV_BT_CEA_4096X2160P25 { \
0263     .type = V4L2_DV_BT_656_1120, \
0264     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
0265         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0266         297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
0267         V4L2_DV_BT_STD_CEA861, \
0268         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \
0269 }
0270 
0271 #define V4L2_DV_BT_CEA_4096X2160P30 { \
0272     .type = V4L2_DV_BT_656_1120, \
0273     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
0274         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0275         297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
0276         V4L2_DV_BT_STD_CEA861, \
0277         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0278         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
0279 }
0280 
0281 #define V4L2_DV_BT_CEA_4096X2160P50 { \
0282     .type = V4L2_DV_BT_656_1120, \
0283     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
0284         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0285         594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
0286         V4L2_DV_BT_STD_CEA861, \
0287         V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \
0288 }
0289 
0290 #define V4L2_DV_BT_CEA_4096X2160P60 { \
0291     .type = V4L2_DV_BT_656_1120, \
0292     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
0293         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0294         594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
0295         V4L2_DV_BT_STD_CEA861, \
0296         V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
0297         V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
0298 }
0299 
0300 
0301 /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
0302 
0303 #define V4L2_DV_BT_DMT_640X350P85 { \
0304     .type = V4L2_DV_BT_656_1120, \
0305     V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
0306         31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
0307         V4L2_DV_BT_STD_DMT, 0) \
0308 }
0309 
0310 #define V4L2_DV_BT_DMT_640X400P85 { \
0311     .type = V4L2_DV_BT_656_1120, \
0312     V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
0313         31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
0314         V4L2_DV_BT_STD_DMT, 0) \
0315 }
0316 
0317 #define V4L2_DV_BT_DMT_720X400P85 { \
0318     .type = V4L2_DV_BT_656_1120, \
0319     V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
0320         35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
0321         V4L2_DV_BT_STD_DMT, 0) \
0322 }
0323 
0324 /* VGA resolutions */
0325 #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
0326 
0327 #define V4L2_DV_BT_DMT_640X480P72 { \
0328     .type = V4L2_DV_BT_656_1120, \
0329     V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
0330         31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
0331         V4L2_DV_BT_STD_DMT, 0) \
0332 }
0333 
0334 #define V4L2_DV_BT_DMT_640X480P75 { \
0335     .type = V4L2_DV_BT_656_1120, \
0336     V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
0337         31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
0338         V4L2_DV_BT_STD_DMT, 0) \
0339 }
0340 
0341 #define V4L2_DV_BT_DMT_640X480P85 { \
0342     .type = V4L2_DV_BT_656_1120, \
0343     V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
0344         36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
0345         V4L2_DV_BT_STD_DMT, 0) \
0346 }
0347 
0348 /* SVGA resolutions */
0349 #define V4L2_DV_BT_DMT_800X600P56 { \
0350     .type = V4L2_DV_BT_656_1120, \
0351     V4L2_INIT_BT_TIMINGS(800, 600, 0, \
0352         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0353         36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
0354         V4L2_DV_BT_STD_DMT, 0) \
0355 }
0356 
0357 #define V4L2_DV_BT_DMT_800X600P60 { \
0358     .type = V4L2_DV_BT_656_1120, \
0359     V4L2_INIT_BT_TIMINGS(800, 600, 0, \
0360         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0361         40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
0362         V4L2_DV_BT_STD_DMT, 0) \
0363 }
0364 
0365 #define V4L2_DV_BT_DMT_800X600P72 { \
0366     .type = V4L2_DV_BT_656_1120, \
0367     V4L2_INIT_BT_TIMINGS(800, 600, 0, \
0368         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0369         50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
0370         V4L2_DV_BT_STD_DMT, 0) \
0371 }
0372 
0373 #define V4L2_DV_BT_DMT_800X600P75 { \
0374     .type = V4L2_DV_BT_656_1120, \
0375     V4L2_INIT_BT_TIMINGS(800, 600, 0, \
0376         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0377         49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
0378         V4L2_DV_BT_STD_DMT, 0) \
0379 }
0380 
0381 #define V4L2_DV_BT_DMT_800X600P85 { \
0382     .type = V4L2_DV_BT_656_1120, \
0383     V4L2_INIT_BT_TIMINGS(800, 600, 0, \
0384         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0385         56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
0386         V4L2_DV_BT_STD_DMT, 0) \
0387 }
0388 
0389 #define V4L2_DV_BT_DMT_800X600P120_RB { \
0390     .type = V4L2_DV_BT_656_1120, \
0391     V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
0392         73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
0393         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0394         V4L2_DV_FL_REDUCED_BLANKING) \
0395 }
0396 
0397 #define V4L2_DV_BT_DMT_848X480P60 { \
0398     .type = V4L2_DV_BT_656_1120, \
0399     V4L2_INIT_BT_TIMINGS(848, 480, 0, \
0400         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0401         33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
0402         V4L2_DV_BT_STD_DMT, 0) \
0403 }
0404 
0405 #define V4L2_DV_BT_DMT_1024X768I43 { \
0406     .type = V4L2_DV_BT_656_1120, \
0407     V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
0408         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0409         44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
0410         V4L2_DV_BT_STD_DMT, 0) \
0411 }
0412 
0413 /* XGA resolutions */
0414 #define V4L2_DV_BT_DMT_1024X768P60 { \
0415     .type = V4L2_DV_BT_656_1120, \
0416     V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
0417         65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
0418         V4L2_DV_BT_STD_DMT, 0) \
0419 }
0420 
0421 #define V4L2_DV_BT_DMT_1024X768P70 { \
0422     .type = V4L2_DV_BT_656_1120, \
0423     V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
0424         75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
0425         V4L2_DV_BT_STD_DMT, 0) \
0426 }
0427 
0428 #define V4L2_DV_BT_DMT_1024X768P75 { \
0429     .type = V4L2_DV_BT_656_1120, \
0430     V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
0431         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0432         78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
0433         V4L2_DV_BT_STD_DMT, 0) \
0434 }
0435 
0436 #define V4L2_DV_BT_DMT_1024X768P85 { \
0437     .type = V4L2_DV_BT_656_1120, \
0438     V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
0439         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0440         94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
0441         V4L2_DV_BT_STD_DMT, 0) \
0442 }
0443 
0444 #define V4L2_DV_BT_DMT_1024X768P120_RB { \
0445     .type = V4L2_DV_BT_656_1120, \
0446     V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
0447         115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
0448         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0449         V4L2_DV_FL_REDUCED_BLANKING) \
0450 }
0451 
0452 /* XGA+ resolution */
0453 #define V4L2_DV_BT_DMT_1152X864P75 { \
0454     .type = V4L2_DV_BT_656_1120, \
0455     V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
0456         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0457         108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
0458         V4L2_DV_BT_STD_DMT, 0) \
0459 }
0460 
0461 #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
0462 
0463 /* WXGA resolutions */
0464 #define V4L2_DV_BT_DMT_1280X768P60_RB { \
0465     .type = V4L2_DV_BT_656_1120, \
0466     V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
0467         68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
0468         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0469         V4L2_DV_FL_REDUCED_BLANKING) \
0470 }
0471 
0472 #define V4L2_DV_BT_DMT_1280X768P60 { \
0473     .type = V4L2_DV_BT_656_1120, \
0474     V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
0475         79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
0476         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0477 }
0478 
0479 #define V4L2_DV_BT_DMT_1280X768P75 { \
0480     .type = V4L2_DV_BT_656_1120, \
0481     V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
0482         102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
0483         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0484 }
0485 
0486 #define V4L2_DV_BT_DMT_1280X768P85 { \
0487     .type = V4L2_DV_BT_656_1120, \
0488     V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
0489         117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
0490         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0491 }
0492 
0493 #define V4L2_DV_BT_DMT_1280X768P120_RB { \
0494     .type = V4L2_DV_BT_656_1120, \
0495     V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
0496         140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
0497         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0498         V4L2_DV_FL_REDUCED_BLANKING) \
0499 }
0500 
0501 #define V4L2_DV_BT_DMT_1280X800P60_RB { \
0502     .type = V4L2_DV_BT_656_1120, \
0503     V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
0504         71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
0505         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0506         V4L2_DV_FL_REDUCED_BLANKING) \
0507 }
0508 
0509 #define V4L2_DV_BT_DMT_1280X800P60 { \
0510     .type = V4L2_DV_BT_656_1120, \
0511     V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
0512         83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
0513         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0514 }
0515 
0516 #define V4L2_DV_BT_DMT_1280X800P75 { \
0517     .type = V4L2_DV_BT_656_1120, \
0518     V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
0519         106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
0520         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0521 }
0522 
0523 #define V4L2_DV_BT_DMT_1280X800P85 { \
0524     .type = V4L2_DV_BT_656_1120, \
0525     V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
0526         122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
0527         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0528 }
0529 
0530 #define V4L2_DV_BT_DMT_1280X800P120_RB { \
0531     .type = V4L2_DV_BT_656_1120, \
0532     V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
0533         146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
0534         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0535         V4L2_DV_FL_REDUCED_BLANKING) \
0536 }
0537 
0538 #define V4L2_DV_BT_DMT_1280X960P60 { \
0539     .type = V4L2_DV_BT_656_1120, \
0540     V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
0541         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0542         108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
0543         V4L2_DV_BT_STD_DMT, 0) \
0544 }
0545 
0546 #define V4L2_DV_BT_DMT_1280X960P85 { \
0547     .type = V4L2_DV_BT_656_1120, \
0548     V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
0549         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0550         148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
0551         V4L2_DV_BT_STD_DMT, 0) \
0552 }
0553 
0554 #define V4L2_DV_BT_DMT_1280X960P120_RB { \
0555     .type = V4L2_DV_BT_656_1120, \
0556     V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
0557         175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
0558         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0559         V4L2_DV_FL_REDUCED_BLANKING) \
0560 }
0561 
0562 /* SXGA resolutions */
0563 #define V4L2_DV_BT_DMT_1280X1024P60 { \
0564     .type = V4L2_DV_BT_656_1120, \
0565     V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
0566         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0567         108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
0568         V4L2_DV_BT_STD_DMT, 0) \
0569 }
0570 
0571 #define V4L2_DV_BT_DMT_1280X1024P75 { \
0572     .type = V4L2_DV_BT_656_1120, \
0573     V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
0574         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0575         135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
0576         V4L2_DV_BT_STD_DMT, 0) \
0577 }
0578 
0579 #define V4L2_DV_BT_DMT_1280X1024P85 { \
0580     .type = V4L2_DV_BT_656_1120, \
0581     V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
0582         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0583         157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
0584         V4L2_DV_BT_STD_DMT, 0) \
0585 }
0586 
0587 #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
0588     .type = V4L2_DV_BT_656_1120, \
0589     V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
0590         187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
0591         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0592         V4L2_DV_FL_REDUCED_BLANKING) \
0593 }
0594 
0595 #define V4L2_DV_BT_DMT_1360X768P60 { \
0596     .type = V4L2_DV_BT_656_1120, \
0597     V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
0598         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0599         85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
0600         V4L2_DV_BT_STD_DMT, 0) \
0601 }
0602 
0603 #define V4L2_DV_BT_DMT_1360X768P120_RB { \
0604     .type = V4L2_DV_BT_656_1120, \
0605     V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
0606         148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
0607         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0608         V4L2_DV_FL_REDUCED_BLANKING) \
0609 }
0610 
0611 #define V4L2_DV_BT_DMT_1366X768P60 { \
0612     .type = V4L2_DV_BT_656_1120, \
0613     V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
0614         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0615         85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
0616         V4L2_DV_BT_STD_DMT, 0) \
0617 }
0618 
0619 #define V4L2_DV_BT_DMT_1366X768P60_RB { \
0620     .type = V4L2_DV_BT_656_1120, \
0621     V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
0622         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0623         72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
0624         V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
0625 }
0626 
0627 /* SXGA+ resolutions */
0628 #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
0629     .type = V4L2_DV_BT_656_1120, \
0630     V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
0631         101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
0632         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0633         V4L2_DV_FL_REDUCED_BLANKING) \
0634 }
0635 
0636 #define V4L2_DV_BT_DMT_1400X1050P60 { \
0637     .type = V4L2_DV_BT_656_1120, \
0638     V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
0639         121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
0640         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0641 }
0642 
0643 #define V4L2_DV_BT_DMT_1400X1050P75 { \
0644     .type = V4L2_DV_BT_656_1120, \
0645     V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
0646         156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
0647         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0648 }
0649 
0650 #define V4L2_DV_BT_DMT_1400X1050P85 { \
0651     .type = V4L2_DV_BT_656_1120, \
0652     V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
0653         179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
0654         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0655 }
0656 
0657 #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
0658     .type = V4L2_DV_BT_656_1120, \
0659     V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
0660         208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
0661         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0662         V4L2_DV_FL_REDUCED_BLANKING) \
0663 }
0664 
0665 /* WXGA+ resolutions */
0666 #define V4L2_DV_BT_DMT_1440X900P60_RB { \
0667     .type = V4L2_DV_BT_656_1120, \
0668     V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
0669         88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
0670         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0671         V4L2_DV_FL_REDUCED_BLANKING) \
0672 }
0673 
0674 #define V4L2_DV_BT_DMT_1440X900P60 { \
0675     .type = V4L2_DV_BT_656_1120, \
0676     V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
0677         106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
0678         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0679 }
0680 
0681 #define V4L2_DV_BT_DMT_1440X900P75 { \
0682     .type = V4L2_DV_BT_656_1120, \
0683     V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
0684         136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
0685         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0686 }
0687 
0688 #define V4L2_DV_BT_DMT_1440X900P85 { \
0689     .type = V4L2_DV_BT_656_1120, \
0690     V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
0691         157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
0692         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0693 }
0694 
0695 #define V4L2_DV_BT_DMT_1440X900P120_RB { \
0696     .type = V4L2_DV_BT_656_1120, \
0697     V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
0698         182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
0699         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0700         V4L2_DV_FL_REDUCED_BLANKING) \
0701 }
0702 
0703 #define V4L2_DV_BT_DMT_1600X900P60_RB { \
0704     .type = V4L2_DV_BT_656_1120, \
0705     V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
0706         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0707         108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
0708         V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
0709 }
0710 
0711 /* UXGA resolutions */
0712 #define V4L2_DV_BT_DMT_1600X1200P60 { \
0713     .type = V4L2_DV_BT_656_1120, \
0714     V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
0715         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0716         162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
0717         V4L2_DV_BT_STD_DMT, 0) \
0718 }
0719 
0720 #define V4L2_DV_BT_DMT_1600X1200P65 { \
0721     .type = V4L2_DV_BT_656_1120, \
0722     V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
0723         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0724         175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
0725         V4L2_DV_BT_STD_DMT, 0) \
0726 }
0727 
0728 #define V4L2_DV_BT_DMT_1600X1200P70 { \
0729     .type = V4L2_DV_BT_656_1120, \
0730     V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
0731         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0732         189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
0733         V4L2_DV_BT_STD_DMT, 0) \
0734 }
0735 
0736 #define V4L2_DV_BT_DMT_1600X1200P75 { \
0737     .type = V4L2_DV_BT_656_1120, \
0738     V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
0739         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0740         202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
0741         V4L2_DV_BT_STD_DMT, 0) \
0742 }
0743 
0744 #define V4L2_DV_BT_DMT_1600X1200P85 { \
0745     .type = V4L2_DV_BT_656_1120, \
0746     V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
0747         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0748         229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
0749         V4L2_DV_BT_STD_DMT, 0) \
0750 }
0751 
0752 #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
0753     .type = V4L2_DV_BT_656_1120, \
0754     V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
0755         268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
0756         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0757         V4L2_DV_FL_REDUCED_BLANKING) \
0758 }
0759 
0760 /* WSXGA+ resolutions */
0761 #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
0762     .type = V4L2_DV_BT_656_1120, \
0763     V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
0764         119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
0765         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0766         V4L2_DV_FL_REDUCED_BLANKING) \
0767 }
0768 
0769 #define V4L2_DV_BT_DMT_1680X1050P60 { \
0770     .type = V4L2_DV_BT_656_1120, \
0771     V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
0772         146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
0773         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0774 }
0775 
0776 #define V4L2_DV_BT_DMT_1680X1050P75 { \
0777     .type = V4L2_DV_BT_656_1120, \
0778     V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
0779         187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
0780         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0781 }
0782 
0783 #define V4L2_DV_BT_DMT_1680X1050P85 { \
0784     .type = V4L2_DV_BT_656_1120, \
0785     V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
0786         214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
0787         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0788 }
0789 
0790 #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
0791     .type = V4L2_DV_BT_656_1120, \
0792     V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
0793         245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
0794         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0795         V4L2_DV_FL_REDUCED_BLANKING) \
0796 }
0797 
0798 #define V4L2_DV_BT_DMT_1792X1344P60 { \
0799     .type = V4L2_DV_BT_656_1120, \
0800     V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
0801         204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
0802         V4L2_DV_BT_STD_DMT, 0) \
0803 }
0804 
0805 #define V4L2_DV_BT_DMT_1792X1344P75 { \
0806     .type = V4L2_DV_BT_656_1120, \
0807     V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
0808         261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
0809         V4L2_DV_BT_STD_DMT, 0) \
0810 }
0811 
0812 #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
0813     .type = V4L2_DV_BT_656_1120, \
0814     V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
0815         333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
0816         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0817         V4L2_DV_FL_REDUCED_BLANKING) \
0818 }
0819 
0820 #define V4L2_DV_BT_DMT_1856X1392P60 { \
0821     .type = V4L2_DV_BT_656_1120, \
0822     V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
0823         218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
0824         V4L2_DV_BT_STD_DMT, 0) \
0825 }
0826 
0827 #define V4L2_DV_BT_DMT_1856X1392P75 { \
0828     .type = V4L2_DV_BT_656_1120, \
0829     V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
0830         288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
0831         V4L2_DV_BT_STD_DMT, 0) \
0832 }
0833 
0834 #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
0835     .type = V4L2_DV_BT_656_1120, \
0836     V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
0837         356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
0838         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0839         V4L2_DV_FL_REDUCED_BLANKING) \
0840 }
0841 
0842 #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
0843 
0844 /* WUXGA resolutions */
0845 #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
0846     .type = V4L2_DV_BT_656_1120, \
0847     V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
0848         154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
0849         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0850         V4L2_DV_FL_REDUCED_BLANKING) \
0851 }
0852 
0853 #define V4L2_DV_BT_DMT_1920X1200P60 { \
0854     .type = V4L2_DV_BT_656_1120, \
0855     V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
0856         193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
0857         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0858 }
0859 
0860 #define V4L2_DV_BT_DMT_1920X1200P75 { \
0861     .type = V4L2_DV_BT_656_1120, \
0862     V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
0863         245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
0864         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0865 }
0866 
0867 #define V4L2_DV_BT_DMT_1920X1200P85 { \
0868     .type = V4L2_DV_BT_656_1120, \
0869     V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
0870         281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
0871         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0872 }
0873 
0874 #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
0875     .type = V4L2_DV_BT_656_1120, \
0876     V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
0877         317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
0878         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0879         V4L2_DV_FL_REDUCED_BLANKING) \
0880 }
0881 
0882 #define V4L2_DV_BT_DMT_1920X1440P60 { \
0883     .type = V4L2_DV_BT_656_1120, \
0884     V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
0885         234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
0886         V4L2_DV_BT_STD_DMT, 0) \
0887 }
0888 
0889 #define V4L2_DV_BT_DMT_1920X1440P75 { \
0890     .type = V4L2_DV_BT_656_1120, \
0891     V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
0892         297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
0893         V4L2_DV_BT_STD_DMT, 0) \
0894 }
0895 
0896 #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
0897     .type = V4L2_DV_BT_656_1120, \
0898     V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
0899         380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
0900         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0901         V4L2_DV_FL_REDUCED_BLANKING) \
0902 }
0903 
0904 #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
0905     .type = V4L2_DV_BT_656_1120, \
0906     V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
0907         V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
0908         162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
0909         V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
0910 }
0911 
0912 /* WQXGA resolutions */
0913 #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
0914     .type = V4L2_DV_BT_656_1120, \
0915     V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
0916         268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
0917         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0918         V4L2_DV_FL_REDUCED_BLANKING) \
0919 }
0920 
0921 #define V4L2_DV_BT_DMT_2560X1600P60 { \
0922     .type = V4L2_DV_BT_656_1120, \
0923     V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
0924         348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
0925         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0926 }
0927 
0928 #define V4L2_DV_BT_DMT_2560X1600P75 { \
0929     .type = V4L2_DV_BT_656_1120, \
0930     V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
0931         443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
0932         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0933 }
0934 
0935 #define V4L2_DV_BT_DMT_2560X1600P85 { \
0936     .type = V4L2_DV_BT_656_1120, \
0937     V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
0938         505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
0939         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
0940 }
0941 
0942 #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
0943     .type = V4L2_DV_BT_656_1120, \
0944     V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
0945         552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
0946         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0947         V4L2_DV_FL_REDUCED_BLANKING) \
0948 }
0949 
0950 /* 4K resolutions */
0951 #define V4L2_DV_BT_DMT_4096X2160P60_RB { \
0952     .type = V4L2_DV_BT_656_1120, \
0953     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
0954         556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
0955         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0956         V4L2_DV_FL_REDUCED_BLANKING) \
0957 }
0958 
0959 #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
0960     .type = V4L2_DV_BT_656_1120, \
0961     V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
0962         556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
0963         V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
0964         V4L2_DV_FL_REDUCED_BLANKING) \
0965 }
0966 
0967 /* SDI timings definitions */
0968 
0969 /* SMPTE-125M */
0970 #define V4L2_DV_BT_SDI_720X487I60 { \
0971     .type = V4L2_DV_BT_656_1120, \
0972     V4L2_INIT_BT_TIMINGS(720, 487, 1, \
0973         V4L2_DV_HSYNC_POS_POL, \
0974         13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \
0975         V4L2_DV_BT_STD_SDI, \
0976         V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \
0977 }
0978 
0979 #endif
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