0001
0002 #ifndef __TARGET_CORE_USER_H
0003 #define __TARGET_CORE_USER_H
0004
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0007 #include <linux/types.h>
0008 #include <linux/uio.h>
0009
0010 #define TCMU_VERSION "2.0"
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0044 #define TCMU_MAILBOX_VERSION 2
0045 #define ALIGN_SIZE 64
0046 #define TCMU_MAILBOX_FLAG_CAP_OOOC (1 << 0)
0047 #define TCMU_MAILBOX_FLAG_CAP_READ_LEN (1 << 1)
0048 #define TCMU_MAILBOX_FLAG_CAP_TMR (1 << 2)
0049 #define TCMU_MAILBOX_FLAG_CAP_KEEP_BUF (1<<3)
0050
0051 struct tcmu_mailbox {
0052 __u16 version;
0053 __u16 flags;
0054 __u32 cmdr_off;
0055 __u32 cmdr_size;
0056
0057 __u32 cmd_head;
0058
0059
0060 __u32 cmd_tail __attribute__((__aligned__(ALIGN_SIZE)));
0061
0062 } __packed;
0063
0064 enum tcmu_opcode {
0065 TCMU_OP_PAD = 0,
0066 TCMU_OP_CMD,
0067 TCMU_OP_TMR,
0068 };
0069
0070
0071
0072
0073 struct tcmu_cmd_entry_hdr {
0074 __u32 len_op;
0075 __u16 cmd_id;
0076 __u8 kflags;
0077 #define TCMU_UFLAG_UNKNOWN_OP 0x1
0078 #define TCMU_UFLAG_READ_LEN 0x2
0079 #define TCMU_UFLAG_KEEP_BUF 0x4
0080 __u8 uflags;
0081
0082 } __packed;
0083
0084 #define TCMU_OP_MASK 0x7
0085
0086 static inline enum tcmu_opcode tcmu_hdr_get_op(__u32 len_op)
0087 {
0088 return len_op & TCMU_OP_MASK;
0089 }
0090
0091 static inline void tcmu_hdr_set_op(__u32 *len_op, enum tcmu_opcode op)
0092 {
0093 *len_op &= ~TCMU_OP_MASK;
0094 *len_op |= (op & TCMU_OP_MASK);
0095 }
0096
0097 static inline __u32 tcmu_hdr_get_len(__u32 len_op)
0098 {
0099 return len_op & ~TCMU_OP_MASK;
0100 }
0101
0102 static inline void tcmu_hdr_set_len(__u32 *len_op, __u32 len)
0103 {
0104 *len_op &= TCMU_OP_MASK;
0105 *len_op |= len;
0106 }
0107
0108
0109 #define TCMU_SENSE_BUFFERSIZE 96
0110
0111 struct tcmu_cmd_entry {
0112 struct tcmu_cmd_entry_hdr hdr;
0113
0114 union {
0115 struct {
0116 __u32 iov_cnt;
0117 __u32 iov_bidi_cnt;
0118 __u32 iov_dif_cnt;
0119 __u64 cdb_off;
0120 __u64 __pad1;
0121 __u64 __pad2;
0122 struct iovec iov[0];
0123 } req;
0124 struct {
0125 __u8 scsi_status;
0126 __u8 __pad1;
0127 __u16 __pad2;
0128 __u32 read_len;
0129 char sense_buffer[TCMU_SENSE_BUFFERSIZE];
0130 } rsp;
0131 };
0132
0133 } __packed;
0134
0135 struct tcmu_tmr_entry {
0136 struct tcmu_cmd_entry_hdr hdr;
0137
0138 #define TCMU_TMR_UNKNOWN 0
0139 #define TCMU_TMR_ABORT_TASK 1
0140 #define TCMU_TMR_ABORT_TASK_SET 2
0141 #define TCMU_TMR_CLEAR_ACA 3
0142 #define TCMU_TMR_CLEAR_TASK_SET 4
0143 #define TCMU_TMR_LUN_RESET 5
0144 #define TCMU_TMR_TARGET_WARM_RESET 6
0145 #define TCMU_TMR_TARGET_COLD_RESET 7
0146
0147 #define TCMU_TMR_LUN_RESET_PRO 128
0148 __u8 tmr_type;
0149
0150 __u8 __pad1;
0151 __u16 __pad2;
0152 __u32 cmd_cnt;
0153 __u64 __pad3;
0154 __u64 __pad4;
0155 __u16 cmd_ids[];
0156 } __packed;
0157
0158 #define TCMU_OP_ALIGN_SIZE sizeof(__u64)
0159
0160 enum tcmu_genl_cmd {
0161 TCMU_CMD_UNSPEC,
0162 TCMU_CMD_ADDED_DEVICE,
0163 TCMU_CMD_REMOVED_DEVICE,
0164 TCMU_CMD_RECONFIG_DEVICE,
0165 TCMU_CMD_ADDED_DEVICE_DONE,
0166 TCMU_CMD_REMOVED_DEVICE_DONE,
0167 TCMU_CMD_RECONFIG_DEVICE_DONE,
0168 TCMU_CMD_SET_FEATURES,
0169 __TCMU_CMD_MAX,
0170 };
0171 #define TCMU_CMD_MAX (__TCMU_CMD_MAX - 1)
0172
0173 enum tcmu_genl_attr {
0174 TCMU_ATTR_UNSPEC,
0175 TCMU_ATTR_DEVICE,
0176 TCMU_ATTR_MINOR,
0177 TCMU_ATTR_PAD,
0178 TCMU_ATTR_DEV_CFG,
0179 TCMU_ATTR_DEV_SIZE,
0180 TCMU_ATTR_WRITECACHE,
0181 TCMU_ATTR_CMD_STATUS,
0182 TCMU_ATTR_DEVICE_ID,
0183 TCMU_ATTR_SUPP_KERN_CMD_REPLY,
0184 __TCMU_ATTR_MAX,
0185 };
0186 #define TCMU_ATTR_MAX (__TCMU_ATTR_MAX - 1)
0187
0188 #endif