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0013 #ifndef __NDCTL_H__
0014 #define __NDCTL_H__
0015
0016 #include <linux/types.h>
0017
0018 struct nd_cmd_dimm_flags {
0019 __u32 status;
0020 __u32 flags;
0021 } __packed;
0022
0023 struct nd_cmd_get_config_size {
0024 __u32 status;
0025 __u32 config_size;
0026 __u32 max_xfer;
0027 } __packed;
0028
0029 struct nd_cmd_get_config_data_hdr {
0030 __u32 in_offset;
0031 __u32 in_length;
0032 __u32 status;
0033 __u8 out_buf[];
0034 } __packed;
0035
0036 struct nd_cmd_set_config_hdr {
0037 __u32 in_offset;
0038 __u32 in_length;
0039 __u8 in_buf[];
0040 } __packed;
0041
0042 struct nd_cmd_vendor_hdr {
0043 __u32 opcode;
0044 __u32 in_length;
0045 __u8 in_buf[];
0046 } __packed;
0047
0048 struct nd_cmd_vendor_tail {
0049 __u32 status;
0050 __u32 out_length;
0051 __u8 out_buf[];
0052 } __packed;
0053
0054 struct nd_cmd_ars_cap {
0055 __u64 address;
0056 __u64 length;
0057 __u32 status;
0058 __u32 max_ars_out;
0059 __u32 clear_err_unit;
0060 __u16 flags;
0061 __u16 reserved;
0062 } __packed;
0063
0064 struct nd_cmd_ars_start {
0065 __u64 address;
0066 __u64 length;
0067 __u16 type;
0068 __u8 flags;
0069 __u8 reserved[5];
0070 __u32 status;
0071 __u32 scrub_time;
0072 } __packed;
0073
0074 struct nd_cmd_ars_status {
0075 __u32 status;
0076 __u32 out_length;
0077 __u64 address;
0078 __u64 length;
0079 __u64 restart_address;
0080 __u64 restart_length;
0081 __u16 type;
0082 __u16 flags;
0083 __u32 num_records;
0084 struct nd_ars_record {
0085 __u32 handle;
0086 __u32 reserved;
0087 __u64 err_address;
0088 __u64 length;
0089 } __packed records[];
0090 } __packed;
0091
0092 struct nd_cmd_clear_error {
0093 __u64 address;
0094 __u64 length;
0095 __u32 status;
0096 __u8 reserved[4];
0097 __u64 cleared;
0098 } __packed;
0099
0100 enum {
0101 ND_CMD_IMPLEMENTED = 0,
0102
0103
0104 ND_CMD_ARS_CAP = 1,
0105 ND_CMD_ARS_START = 2,
0106 ND_CMD_ARS_STATUS = 3,
0107 ND_CMD_CLEAR_ERROR = 4,
0108
0109
0110 ND_CMD_SMART = 1,
0111 ND_CMD_SMART_THRESHOLD = 2,
0112 ND_CMD_DIMM_FLAGS = 3,
0113 ND_CMD_GET_CONFIG_SIZE = 4,
0114 ND_CMD_GET_CONFIG_DATA = 5,
0115 ND_CMD_SET_CONFIG_DATA = 6,
0116 ND_CMD_VENDOR_EFFECT_LOG_SIZE = 7,
0117 ND_CMD_VENDOR_EFFECT_LOG = 8,
0118 ND_CMD_VENDOR = 9,
0119 ND_CMD_CALL = 10,
0120 };
0121
0122 enum {
0123 ND_ARS_VOLATILE = 1,
0124 ND_ARS_PERSISTENT = 2,
0125 ND_ARS_RETURN_PREV_DATA = 1 << 1,
0126 ND_CONFIG_LOCKED = 1,
0127 };
0128
0129 static inline const char *nvdimm_bus_cmd_name(unsigned cmd)
0130 {
0131 switch (cmd) {
0132 case ND_CMD_ARS_CAP: return "ars_cap";
0133 case ND_CMD_ARS_START: return "ars_start";
0134 case ND_CMD_ARS_STATUS: return "ars_status";
0135 case ND_CMD_CLEAR_ERROR: return "clear_error";
0136 case ND_CMD_CALL: return "cmd_call";
0137 default: return "unknown";
0138 }
0139 }
0140
0141 static inline const char *nvdimm_cmd_name(unsigned cmd)
0142 {
0143 switch (cmd) {
0144 case ND_CMD_SMART: return "smart";
0145 case ND_CMD_SMART_THRESHOLD: return "smart_thresh";
0146 case ND_CMD_DIMM_FLAGS: return "flags";
0147 case ND_CMD_GET_CONFIG_SIZE: return "get_size";
0148 case ND_CMD_GET_CONFIG_DATA: return "get_data";
0149 case ND_CMD_SET_CONFIG_DATA: return "set_data";
0150 case ND_CMD_VENDOR_EFFECT_LOG_SIZE: return "effect_size";
0151 case ND_CMD_VENDOR_EFFECT_LOG: return "effect_log";
0152 case ND_CMD_VENDOR: return "vendor";
0153 case ND_CMD_CALL: return "cmd_call";
0154 default: return "unknown";
0155 }
0156 }
0157
0158 #define ND_IOCTL 'N'
0159
0160 #define ND_IOCTL_DIMM_FLAGS _IOWR(ND_IOCTL, ND_CMD_DIMM_FLAGS,\
0161 struct nd_cmd_dimm_flags)
0162
0163 #define ND_IOCTL_GET_CONFIG_SIZE _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_SIZE,\
0164 struct nd_cmd_get_config_size)
0165
0166 #define ND_IOCTL_GET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_GET_CONFIG_DATA,\
0167 struct nd_cmd_get_config_data_hdr)
0168
0169 #define ND_IOCTL_SET_CONFIG_DATA _IOWR(ND_IOCTL, ND_CMD_SET_CONFIG_DATA,\
0170 struct nd_cmd_set_config_hdr)
0171
0172 #define ND_IOCTL_VENDOR _IOWR(ND_IOCTL, ND_CMD_VENDOR,\
0173 struct nd_cmd_vendor_hdr)
0174
0175 #define ND_IOCTL_ARS_CAP _IOWR(ND_IOCTL, ND_CMD_ARS_CAP,\
0176 struct nd_cmd_ars_cap)
0177
0178 #define ND_IOCTL_ARS_START _IOWR(ND_IOCTL, ND_CMD_ARS_START,\
0179 struct nd_cmd_ars_start)
0180
0181 #define ND_IOCTL_ARS_STATUS _IOWR(ND_IOCTL, ND_CMD_ARS_STATUS,\
0182 struct nd_cmd_ars_status)
0183
0184 #define ND_IOCTL_CLEAR_ERROR _IOWR(ND_IOCTL, ND_CMD_CLEAR_ERROR,\
0185 struct nd_cmd_clear_error)
0186
0187 #define ND_DEVICE_DIMM 1
0188 #define ND_DEVICE_REGION_PMEM 2
0189 #define ND_DEVICE_REGION_BLK 3
0190 #define ND_DEVICE_NAMESPACE_IO 4
0191 #define ND_DEVICE_NAMESPACE_PMEM 5
0192 #define ND_DEVICE_DAX_PMEM 7
0193
0194 enum nd_driver_flags {
0195 ND_DRIVER_DIMM = 1 << ND_DEVICE_DIMM,
0196 ND_DRIVER_REGION_PMEM = 1 << ND_DEVICE_REGION_PMEM,
0197 ND_DRIVER_REGION_BLK = 1 << ND_DEVICE_REGION_BLK,
0198 ND_DRIVER_NAMESPACE_IO = 1 << ND_DEVICE_NAMESPACE_IO,
0199 ND_DRIVER_NAMESPACE_PMEM = 1 << ND_DEVICE_NAMESPACE_PMEM,
0200 ND_DRIVER_DAX_PMEM = 1 << ND_DEVICE_DAX_PMEM,
0201 };
0202
0203 enum ars_masks {
0204 ARS_STATUS_MASK = 0x0000FFFF,
0205 ARS_EXT_STATUS_SHIFT = 16,
0206 };
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0229 struct nd_cmd_pkg {
0230 __u64 nd_family;
0231 __u64 nd_command;
0232 __u32 nd_size_in;
0233 __u32 nd_size_out;
0234 __u32 nd_reserved2[9];
0235 __u32 nd_fw_size;
0236 unsigned char nd_payload[];
0237 };
0238
0239
0240 #define NVDIMM_FAMILY_INTEL 0
0241 #define NVDIMM_FAMILY_HPE1 1
0242 #define NVDIMM_FAMILY_HPE2 2
0243 #define NVDIMM_FAMILY_MSFT 3
0244 #define NVDIMM_FAMILY_HYPERV 4
0245 #define NVDIMM_FAMILY_PAPR 5
0246 #define NVDIMM_FAMILY_MAX NVDIMM_FAMILY_PAPR
0247
0248 #define NVDIMM_BUS_FAMILY_NFIT 0
0249 #define NVDIMM_BUS_FAMILY_INTEL 1
0250 #define NVDIMM_BUS_FAMILY_MAX NVDIMM_BUS_FAMILY_INTEL
0251
0252 #define ND_IOCTL_CALL _IOWR(ND_IOCTL, ND_CMD_CALL,\
0253 struct nd_cmd_pkg)
0254
0255 #endif