uapi/linux/idxd.h

0001 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
0002 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
0003 #ifndef _USR_IDXD_H_
0004 #define _USR_IDXD_H_
0005
0006 #ifdef __KERNEL__
0007 #include <linux/types.h>
0008 #else
0009 #include <stdint.h>
0010 #endif
0011
0012 /* Driver command error status */
0013 enum idxd_scmd_stat {
0014     IDXD_SCMD_DEV_ENABLED = 0x80000010,
0015     IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
0016     IDXD_SCMD_WQ_ENABLED = 0x80000021,
0017     IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
0018     IDXD_SCMD_WQ_NO_GRP = 0x80030000,
0019     IDXD_SCMD_WQ_NO_NAME = 0x80040000,
0020     IDXD_SCMD_WQ_NO_SVM = 0x80050000,
0021     IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
0022     IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
0023     IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
0024     IDXD_SCMD_PERCPU_ERR = 0x80090000,
0025     IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
0026     IDXD_SCMD_CDEV_ERR = 0x800b0000,
0027     IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
0028     IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
0029     IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
0030     IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
0031     IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
0032 };
0033
0034 #define IDXD_SCMD_SOFTERR_MASK  0x80000000
0035 #define IDXD_SCMD_SOFTERR_SHIFT 16
0036
0037 /* Descriptor flags */
0038 #define IDXD_OP_FLAG_FENCE  0x0001
0039 #define IDXD_OP_FLAG_BOF    0x0002
0040 #define IDXD_OP_FLAG_CRAV   0x0004
0041 #define IDXD_OP_FLAG_RCR    0x0008
0042 #define IDXD_OP_FLAG_RCI    0x0010
0043 #define IDXD_OP_FLAG_CRSTS  0x0020
0044 #define IDXD_OP_FLAG_CR     0x0080
0045 #define IDXD_OP_FLAG_CC     0x0100
0046 #define IDXD_OP_FLAG_ADDR1_TCS  0x0200
0047 #define IDXD_OP_FLAG_ADDR2_TCS  0x0400
0048 #define IDXD_OP_FLAG_ADDR3_TCS  0x0800
0049 #define IDXD_OP_FLAG_CR_TCS 0x1000
0050 #define IDXD_OP_FLAG_STORD  0x2000
0051 #define IDXD_OP_FLAG_DRDBK  0x4000
0052 #define IDXD_OP_FLAG_DSTS   0x8000
0053
0054 /* IAX */
0055 #define IDXD_OP_FLAG_RD_SRC2_AECS   0x010000
0056 #define IDXD_OP_FLAG_RD_SRC2_2ND    0x020000
0057 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP  0x040000
0058 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL  0x080000
0059 #define IDXD_OP_FLAG_SRC2_STS       0x100000
0060 #define IDXD_OP_FLAG_CRC_RFC3720    0x200000
0061
0062 /* Opcode */
0063 enum dsa_opcode {
0064     DSA_OPCODE_NOOP = 0,
0065     DSA_OPCODE_BATCH,
0066     DSA_OPCODE_DRAIN,
0067     DSA_OPCODE_MEMMOVE,
0068     DSA_OPCODE_MEMFILL,
0069     DSA_OPCODE_COMPARE,
0070     DSA_OPCODE_COMPVAL,
0071     DSA_OPCODE_CR_DELTA,
0072     DSA_OPCODE_AP_DELTA,
0073     DSA_OPCODE_DUALCAST,
0074     DSA_OPCODE_CRCGEN = 0x10,
0075     DSA_OPCODE_COPY_CRC,
0076     DSA_OPCODE_DIF_CHECK,
0077     DSA_OPCODE_DIF_INS,
0078     DSA_OPCODE_DIF_STRP,
0079     DSA_OPCODE_DIF_UPDT,
0080     DSA_OPCODE_CFLUSH = 0x20,
0081 };
0082
0083 enum iax_opcode {
0084     IAX_OPCODE_NOOP = 0,
0085     IAX_OPCODE_DRAIN = 2,
0086     IAX_OPCODE_MEMMOVE,
0087     IAX_OPCODE_DECOMPRESS = 0x42,
0088     IAX_OPCODE_COMPRESS,
0089     IAX_OPCODE_CRC64,
0090     IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
0091     IAX_OPCODE_ZERO_DECOMP_16,
0092     IAX_OPCODE_ZERO_COMP_32 = 0x4c,
0093     IAX_OPCODE_ZERO_COMP_16,
0094     IAX_OPCODE_SCAN = 0x50,
0095     IAX_OPCODE_SET_MEMBER,
0096     IAX_OPCODE_EXTRACT,
0097     IAX_OPCODE_SELECT,
0098     IAX_OPCODE_RLE_BURST,
0099     IAX_OPCODE_FIND_UNIQUE,
0100     IAX_OPCODE_EXPAND,
0101 };
0102
0103 /* Completion record status */
0104 enum dsa_completion_status {
0105     DSA_COMP_NONE = 0,
0106     DSA_COMP_SUCCESS,
0107     DSA_COMP_SUCCESS_PRED,
0108     DSA_COMP_PAGE_FAULT_NOBOF,
0109     DSA_COMP_PAGE_FAULT_IR,
0110     DSA_COMP_BATCH_FAIL,
0111     DSA_COMP_BATCH_PAGE_FAULT,
0112     DSA_COMP_DR_OFFSET_NOINC,
0113     DSA_COMP_DR_OFFSET_ERANGE,
0114     DSA_COMP_DIF_ERR,
0115     DSA_COMP_BAD_OPCODE = 0x10,
0116     DSA_COMP_INVALID_FLAGS,
0117     DSA_COMP_NOZERO_RESERVE,
0118     DSA_COMP_XFER_ERANGE,
0119     DSA_COMP_DESC_CNT_ERANGE,
0120     DSA_COMP_DR_ERANGE,
0121     DSA_COMP_OVERLAP_BUFFERS,
0122     DSA_COMP_DCAST_ERR,
0123     DSA_COMP_DESCLIST_ALIGN,
0124     DSA_COMP_INT_HANDLE_INVAL,
0125     DSA_COMP_CRA_XLAT,
0126     DSA_COMP_CRA_ALIGN,
0127     DSA_COMP_ADDR_ALIGN,
0128     DSA_COMP_PRIV_BAD,
0129     DSA_COMP_TRAFFIC_CLASS_CONF,
0130     DSA_COMP_PFAULT_RDBA,
0131     DSA_COMP_HW_ERR1,
0132     DSA_COMP_HW_ERR_DRB,
0133     DSA_COMP_TRANSLATION_FAIL,
0134 };
0135
0136 enum iax_completion_status {
0137     IAX_COMP_NONE = 0,
0138     IAX_COMP_SUCCESS,
0139     IAX_COMP_PAGE_FAULT_IR = 0x04,
0140     IAX_COMP_ANALYTICS_ERROR = 0x0a,
0141     IAX_COMP_OUTBUF_OVERFLOW,
0142     IAX_COMP_BAD_OPCODE = 0x10,
0143     IAX_COMP_INVALID_FLAGS,
0144     IAX_COMP_NOZERO_RESERVE,
0145     IAX_COMP_INVALID_SIZE,
0146     IAX_COMP_OVERLAP_BUFFERS = 0x16,
0147     IAX_COMP_INT_HANDLE_INVAL = 0x19,
0148     IAX_COMP_CRA_XLAT,
0149     IAX_COMP_CRA_ALIGN,
0150     IAX_COMP_ADDR_ALIGN,
0151     IAX_COMP_PRIV_BAD,
0152     IAX_COMP_TRAFFIC_CLASS_CONF,
0153     IAX_COMP_PFAULT_RDBA,
0154     IAX_COMP_HW_ERR1,
0155     IAX_COMP_HW_ERR_DRB,
0156     IAX_COMP_TRANSLATION_FAIL,
0157     IAX_COMP_PRS_TIMEOUT,
0158     IAX_COMP_WATCHDOG,
0159     IAX_COMP_INVALID_COMP_FLAG = 0x30,
0160     IAX_COMP_INVALID_FILTER_FLAG,
0161     IAX_COMP_INVALID_INPUT_SIZE,
0162     IAX_COMP_INVALID_NUM_ELEMS,
0163     IAX_COMP_INVALID_SRC1_WIDTH,
0164     IAX_COMP_INVALID_INVERT_OUT,
0165 };
0166
0167 #define DSA_COMP_STATUS_MASK        0x7f
0168 #define DSA_COMP_STATUS_WRITE       0x80
0169
0170 struct dsa_hw_desc {
0171     uint32_t    pasid:20;
0172     uint32_t    rsvd:11;
0173     uint32_t    priv:1;
0174     uint32_t    flags:24;
0175     uint32_t    opcode:8;
0176     uint64_t    completion_addr;
0177     union {
0178         uint64_t    src_addr;
0179         uint64_t    rdback_addr;
0180         uint64_t    pattern;
0181         uint64_t    desc_list_addr;
0182     };
0183     union {
0184         uint64_t    dst_addr;
0185         uint64_t    rdback_addr2;
0186         uint64_t    src2_addr;
0187         uint64_t    comp_pattern;
0188     };
0189     union {
0190         uint32_t    xfer_size;
0191         uint32_t    desc_count;
0192     };
0193     uint16_t    int_handle;
0194     uint16_t    rsvd1;
0195     union {
0196         uint8_t     expected_res;
0197         /* create delta record */
0198         struct {
0199             uint64_t    delta_addr;
0200             uint32_t    max_delta_size;
0201             uint32_t    delt_rsvd;
0202             uint8_t     expected_res_mask;
0203         };
0204         uint32_t    delta_rec_size;
0205         uint64_t    dest2;
0206         /* CRC */
0207         struct {
0208             uint32_t    crc_seed;
0209             uint32_t    crc_rsvd;
0210             uint64_t    seed_addr;
0211         };
0212         /* DIF check or strip */
0213         struct {
0214             uint8_t     src_dif_flags;
0215             uint8_t     dif_chk_res;
0216             uint8_t     dif_chk_flags;
0217             uint8_t     dif_chk_res2[5];
0218             uint32_t    chk_ref_tag_seed;
0219             uint16_t    chk_app_tag_mask;
0220             uint16_t    chk_app_tag_seed;
0221         };
0222         /* DIF insert */
0223         struct {
0224             uint8_t     dif_ins_res;
0225             uint8_t     dest_dif_flag;
0226             uint8_t     dif_ins_flags;
0227             uint8_t     dif_ins_res2[13];
0228             uint32_t    ins_ref_tag_seed;
0229             uint16_t    ins_app_tag_mask;
0230             uint16_t    ins_app_tag_seed;
0231         };
0232         /* DIF update */
0233         struct {
0234             uint8_t     src_upd_flags;
0235             uint8_t     upd_dest_flags;
0236             uint8_t     dif_upd_flags;
0237             uint8_t     dif_upd_res[5];
0238             uint32_t    src_ref_tag_seed;
0239             uint16_t    src_app_tag_mask;
0240             uint16_t    src_app_tag_seed;
0241             uint32_t    dest_ref_tag_seed;
0242             uint16_t    dest_app_tag_mask;
0243             uint16_t    dest_app_tag_seed;
0244         };
0245
0246         uint8_t     op_specific[24];
0247     };
0248 } __attribute__((packed));
0249
0250 struct iax_hw_desc {
0251     uint32_t        pasid:20;
0252     uint32_t        rsvd:11;
0253     uint32_t        priv:1;
0254     uint32_t        flags:24;
0255     uint32_t        opcode:8;
0256     uint64_t        completion_addr;
0257     uint64_t        src1_addr;
0258     uint64_t        dst_addr;
0259     uint32_t        src1_size;
0260     uint16_t        int_handle;
0261     union {
0262         uint16_t        compr_flags;
0263         uint16_t        decompr_flags;
0264     };
0265     uint64_t        src2_addr;
0266     uint32_t        max_dst_size;
0267     uint32_t        src2_size;
0268     uint32_t    filter_flags;
0269     uint32_t    num_inputs;
0270 } __attribute__((packed));
0271
0272 struct dsa_raw_desc {
0273     uint64_t    field[8];
0274 } __attribute__((packed));
0275
0276 /*
0277  * The status field will be modified by hardware, therefore it should be
0278  * volatile and prevent the compiler from optimize the read.
0279  */
0280 struct dsa_completion_record {
0281     volatile uint8_t    status;
0282     union {
0283         uint8_t     result;
0284         uint8_t     dif_status;
0285     };
0286     uint16_t        rsvd;
0287     uint32_t        bytes_completed;
0288     uint64_t        fault_addr;
0289     union {
0290         /* common record */
0291         struct {
0292             uint32_t    invalid_flags:24;
0293             uint32_t    rsvd2:8;
0294         };
0295
0296         uint32_t    delta_rec_size;
0297         uint32_t    crc_val;
0298
0299         /* DIF check & strip */
0300         struct {
0301             uint32_t    dif_chk_ref_tag;
0302             uint16_t    dif_chk_app_tag_mask;
0303             uint16_t    dif_chk_app_tag;
0304         };
0305
0306         /* DIF insert */
0307         struct {
0308             uint64_t    dif_ins_res;
0309             uint32_t    dif_ins_ref_tag;
0310             uint16_t    dif_ins_app_tag_mask;
0311             uint16_t    dif_ins_app_tag;
0312         };
0313
0314         /* DIF update */
0315         struct {
0316             uint32_t    dif_upd_src_ref_tag;
0317             uint16_t    dif_upd_src_app_tag_mask;
0318             uint16_t    dif_upd_src_app_tag;
0319             uint32_t    dif_upd_dest_ref_tag;
0320             uint16_t    dif_upd_dest_app_tag_mask;
0321             uint16_t    dif_upd_dest_app_tag;
0322         };
0323
0324         uint8_t     op_specific[16];
0325     };
0326 } __attribute__((packed));
0327
0328 struct dsa_raw_completion_record {
0329     uint64_t    field[4];
0330 } __attribute__((packed));
0331
0332 struct iax_completion_record {
0333     volatile uint8_t        status;
0334     uint8_t                 error_code;
0335     uint16_t                rsvd;
0336     uint32_t                bytes_completed;
0337     uint64_t                fault_addr;
0338     uint32_t                invalid_flags;
0339     uint32_t                rsvd2;
0340     uint32_t                output_size;
0341     uint8_t                 output_bits;
0342     uint8_t                 rsvd3;
0343     uint16_t                xor_csum;
0344     uint32_t                crc;
0345     uint32_t                min;
0346     uint32_t                max;
0347     uint32_t                sum;
0348     uint64_t                rsvd4[2];
0349 } __attribute__((packed));
0350
0351 struct iax_raw_completion_record {
0352     uint64_t    field[8];
0353 } __attribute__((packed));
0354
0355 #endif