linux/genwqe/genwqe_card.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 #ifndef __GENWQE_CARD_H__
0003 #define __GENWQE_CARD_H__
0004
0005 /**
0006  * IBM Accelerator Family 'GenWQE'
0007  *
0008  * (C) Copyright IBM Corp. 2013
0009  *
0010  * Author: Frank Haverkamp <haver@linux.vnet.ibm.com>
0011  * Author: Joerg-Stephan Vogt <jsvogt@de.ibm.com>
0012  * Author: Michael Jung <mijung@gmx.net>
0013  * Author: Michael Ruettger <michael@ibmra.de>
0014  *
0015  * This program is free software; you can redistribute it and/or modify
0016  * it under the terms of the GNU General Public License (version 2 only)
0017  * as published by the Free Software Foundation.
0018  *
0019  * This program is distributed in the hope that it will be useful,
0020  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0021  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0022  * GNU General Public License for more details.
0023  */
0024
0025 /*
0026  * User-space API for the GenWQE card. For debugging and test purposes
0027  * the register addresses are included here too.
0028  */
0029
0030 #include <linux/types.h>
0031 #include <linux/ioctl.h>
0032
0033 /* Basename of sysfs, debugfs and /dev interfaces */
0034 #define GENWQE_DEVNAME          "genwqe"
0035
0036 #define GENWQE_TYPE_ALTERA_230      0x00 /* GenWQE4 Stratix-IV-230 */
0037 #define GENWQE_TYPE_ALTERA_530      0x01 /* GenWQE4 Stratix-IV-530 */
0038 #define GENWQE_TYPE_ALTERA_A4       0x02 /* GenWQE5 A4 Stratix-V-A4 */
0039 #define GENWQE_TYPE_ALTERA_A7       0x03 /* GenWQE5 A7 Stratix-V-A7 */
0040
0041 /* MMIO Unit offsets: Each UnitID occupies a defined address range */
0042 #define GENWQE_UID_OFFS(uid)        ((uid) << 24)
0043 #define GENWQE_SLU_OFFS         GENWQE_UID_OFFS(0)
0044 #define GENWQE_HSU_OFFS         GENWQE_UID_OFFS(1)
0045 #define GENWQE_APP_OFFS         GENWQE_UID_OFFS(2)
0046 #define GENWQE_MAX_UNITS        3
0047
0048 /* Common offsets per UnitID */
0049 #define IO_EXTENDED_ERROR_POINTER   0x00000048
0050 #define IO_ERROR_INJECT_SELECTOR    0x00000060
0051 #define IO_EXTENDED_DIAG_SELECTOR   0x00000070
0052 #define IO_EXTENDED_DIAG_READ_MBX   0x00000078
0053 #define IO_EXTENDED_DIAG_MAP(ring)  (0x00000500 | ((ring) << 3))
0054
0055 #define GENWQE_EXTENDED_DIAG_SELECTOR(ring, trace) (((ring) << 8) | (trace))
0056
0057 /* UnitID 0: Service Layer Unit (SLU) */
0058
0059 /* SLU: Unit Configuration Register */
0060 #define IO_SLU_UNITCFG          0x00000000
0061 #define IO_SLU_UNITCFG_TYPE_MASK    0x000000000ff00000 /* 27:20 */
0062
0063 /* SLU: Fault Isolation Register (FIR) (ac_slu_fir) */
0064 #define IO_SLU_FIR          0x00000008 /* read only, wr direct */
0065 #define IO_SLU_FIR_CLR          0x00000010 /* read and clear */
0066
0067 /* SLU: First Error Capture Register (FEC/WOF) */
0068 #define IO_SLU_FEC          0x00000018
0069
0070 #define IO_SLU_ERR_ACT_MASK     0x00000020
0071 #define IO_SLU_ERR_ATTN_MASK        0x00000028
0072 #define IO_SLU_FIRX1_ACT_MASK       0x00000030
0073 #define IO_SLU_FIRX0_ACT_MASK       0x00000038
0074 #define IO_SLU_SEC_LEM_DEBUG_OVR    0x00000040
0075 #define IO_SLU_EXTENDED_ERR_PTR     0x00000048
0076 #define IO_SLU_COMMON_CONFIG        0x00000060
0077
0078 #define IO_SLU_FLASH_FIR        0x00000108
0079 #define IO_SLU_SLC_FIR          0x00000110
0080 #define IO_SLU_RIU_TRAP         0x00000280
0081 #define IO_SLU_FLASH_FEC        0x00000308
0082 #define IO_SLU_SLC_FEC          0x00000310
0083
0084 /*
0085  * The  Virtual Function's Access is from offset 0x00010000
0086  * The Physical Function's Access is from offset 0x00050000
0087  * Single Shared Registers exists only at offset 0x00060000
0088  *
0089  * SLC: Queue Virtual Window Window for accessing into a specific VF
0090  * queue. When accessing the 0x10000 space using the 0x50000 address
0091  * segment, the value indicated here is used to specify which VF
0092  * register is decoded. This register, and the 0x50000 register space
0093  * can only be accessed by the PF. Example, if this register is set to
0094  * 0x2, then a read from 0x50000 is the same as a read from 0x10000
0095  * from VF=2.
0096  */
0097
0098 /* SLC: Queue Segment */
0099 #define IO_SLC_QUEUE_SEGMENT        0x00010000
0100 #define IO_SLC_VF_QUEUE_SEGMENT     0x00050000
0101
0102 /* SLC: Queue Offset */
0103 #define IO_SLC_QUEUE_OFFSET     0x00010008
0104 #define IO_SLC_VF_QUEUE_OFFSET      0x00050008
0105
0106 /* SLC: Queue Configuration */
0107 #define IO_SLC_QUEUE_CONFIG     0x00010010
0108 #define IO_SLC_VF_QUEUE_CONFIG      0x00050010
0109
0110 /* SLC: Job Timout/Only accessible for the PF */
0111 #define IO_SLC_APPJOB_TIMEOUT       0x00010018
0112 #define IO_SLC_VF_APPJOB_TIMEOUT    0x00050018
0113 #define TIMEOUT_250MS           0x0000000f
0114 #define HEARTBEAT_DISABLE       0x0000ff00
0115
0116 /* SLC: Queue InitSequence Register */
0117 #define IO_SLC_QUEUE_INITSQN        0x00010020
0118 #define IO_SLC_VF_QUEUE_INITSQN     0x00050020
0119
0120 /* SLC: Queue Wrap */
0121 #define IO_SLC_QUEUE_WRAP       0x00010028
0122 #define IO_SLC_VF_QUEUE_WRAP        0x00050028
0123
0124 /* SLC: Queue Status */
0125 #define IO_SLC_QUEUE_STATUS     0x00010100
0126 #define IO_SLC_VF_QUEUE_STATUS      0x00050100
0127
0128 /* SLC: Queue Working Time */
0129 #define IO_SLC_QUEUE_WTIME      0x00010030
0130 #define IO_SLC_VF_QUEUE_WTIME       0x00050030
0131
0132 /* SLC: Queue Error Counts */
0133 #define IO_SLC_QUEUE_ERRCNTS        0x00010038
0134 #define IO_SLC_VF_QUEUE_ERRCNTS     0x00050038
0135
0136 /* SLC: Queue Loast Response Word */
0137 #define IO_SLC_QUEUE_LRW        0x00010040
0138 #define IO_SLC_VF_QUEUE_LRW     0x00050040
0139
0140 /* SLC: Freerunning Timer */
0141 #define IO_SLC_FREE_RUNNING_TIMER   0x00010108
0142 #define IO_SLC_VF_FREE_RUNNING_TIMER    0x00050108
0143
0144 /* SLC: Queue Virtual Access Region */
0145 #define IO_PF_SLC_VIRTUAL_REGION    0x00050000
0146
0147 /* SLC: Queue Virtual Window */
0148 #define IO_PF_SLC_VIRTUAL_WINDOW    0x00060000
0149
0150 /* SLC: DDCB Application Job Pending [n] (n=0:63) */
0151 #define IO_PF_SLC_JOBPEND(n)        (0x00061000 + 8*(n))
0152 #define IO_SLC_JOBPEND(n)       IO_PF_SLC_JOBPEND(n)
0153
0154 /* SLC: Parser Trap RAM [n] (n=0:31) */
0155 #define IO_SLU_SLC_PARSE_TRAP(n)    (0x00011000 + 8*(n))
0156
0157 /* SLC: Dispatcher Trap RAM [n] (n=0:31) */
0158 #define IO_SLU_SLC_DISP_TRAP(n) (0x00011200 + 8*(n))
0159
0160 /* Global Fault Isolation Register (GFIR) */
0161 #define IO_SLC_CFGREG_GFIR      0x00020000
0162 #define GFIR_ERR_TRIGGER        0x0000ffff
0163
0164 /* SLU: Soft Reset Register */
0165 #define IO_SLC_CFGREG_SOFTRESET     0x00020018
0166
0167 /* SLU: Misc Debug Register */
0168 #define IO_SLC_MISC_DEBUG       0x00020060
0169 #define IO_SLC_MISC_DEBUG_CLR       0x00020068
0170 #define IO_SLC_MISC_DEBUG_SET       0x00020070
0171
0172 /* Temperature Sensor Reading */
0173 #define IO_SLU_TEMPERATURE_SENSOR   0x00030000
0174 #define IO_SLU_TEMPERATURE_CONFIG   0x00030008
0175
0176 /* Voltage Margining Control */
0177 #define IO_SLU_VOLTAGE_CONTROL      0x00030080
0178 #define IO_SLU_VOLTAGE_NOMINAL      0x00000000
0179 #define IO_SLU_VOLTAGE_DOWN5        0x00000006
0180 #define IO_SLU_VOLTAGE_UP5      0x00000007
0181
0182 /* Direct LED Control Register */
0183 #define IO_SLU_LEDCONTROL       0x00030100
0184
0185 /* SLU: Flashbus Direct Access -A5 */
0186 #define IO_SLU_FLASH_DIRECTACCESS   0x00040010
0187
0188 /* SLU: Flashbus Direct Access2 -A5 */
0189 #define IO_SLU_FLASH_DIRECTACCESS2  0x00040020
0190
0191 /* SLU: Flashbus Command Interface -A5 */
0192 #define IO_SLU_FLASH_CMDINTF        0x00040030
0193
0194 /* SLU: BitStream Loaded */
0195 #define IO_SLU_BITSTREAM        0x00040040
0196
0197 /* This Register has a switch which will change the CAs to UR */
0198 #define IO_HSU_ERR_BEHAVIOR     0x01001010
0199
0200 #define IO_SLC2_SQB_TRAP        0x00062000
0201 #define IO_SLC2_QUEUE_MANAGER_TRAP  0x00062008
0202 #define IO_SLC2_FLS_MASTER_TRAP     0x00062010
0203
0204 /* UnitID 1: HSU Registers */
0205 #define IO_HSU_UNITCFG          0x01000000
0206 #define IO_HSU_FIR          0x01000008
0207 #define IO_HSU_FIR_CLR          0x01000010
0208 #define IO_HSU_FEC          0x01000018
0209 #define IO_HSU_ERR_ACT_MASK     0x01000020
0210 #define IO_HSU_ERR_ATTN_MASK        0x01000028
0211 #define IO_HSU_FIRX1_ACT_MASK       0x01000030
0212 #define IO_HSU_FIRX0_ACT_MASK       0x01000038
0213 #define IO_HSU_SEC_LEM_DEBUG_OVR    0x01000040
0214 #define IO_HSU_EXTENDED_ERR_PTR     0x01000048
0215 #define IO_HSU_COMMON_CONFIG        0x01000060
0216
0217 /* UnitID 2: Application Unit (APP) */
0218 #define IO_APP_UNITCFG          0x02000000
0219 #define IO_APP_FIR          0x02000008
0220 #define IO_APP_FIR_CLR          0x02000010
0221 #define IO_APP_FEC          0x02000018
0222 #define IO_APP_ERR_ACT_MASK     0x02000020
0223 #define IO_APP_ERR_ATTN_MASK        0x02000028
0224 #define IO_APP_FIRX1_ACT_MASK       0x02000030
0225 #define IO_APP_FIRX0_ACT_MASK       0x02000038
0226 #define IO_APP_SEC_LEM_DEBUG_OVR    0x02000040
0227 #define IO_APP_EXTENDED_ERR_PTR     0x02000048
0228 #define IO_APP_COMMON_CONFIG        0x02000060
0229
0230 #define IO_APP_DEBUG_REG_01     0x02010000
0231 #define IO_APP_DEBUG_REG_02     0x02010008
0232 #define IO_APP_DEBUG_REG_03     0x02010010
0233 #define IO_APP_DEBUG_REG_04     0x02010018
0234 #define IO_APP_DEBUG_REG_05     0x02010020
0235 #define IO_APP_DEBUG_REG_06     0x02010028
0236 #define IO_APP_DEBUG_REG_07     0x02010030
0237 #define IO_APP_DEBUG_REG_08     0x02010038
0238 #define IO_APP_DEBUG_REG_09     0x02010040
0239 #define IO_APP_DEBUG_REG_10     0x02010048
0240 #define IO_APP_DEBUG_REG_11     0x02010050
0241 #define IO_APP_DEBUG_REG_12     0x02010058
0242 #define IO_APP_DEBUG_REG_13     0x02010060
0243 #define IO_APP_DEBUG_REG_14     0x02010068
0244 #define IO_APP_DEBUG_REG_15     0x02010070
0245 #define IO_APP_DEBUG_REG_16     0x02010078
0246 #define IO_APP_DEBUG_REG_17     0x02010080
0247 #define IO_APP_DEBUG_REG_18     0x02010088
0248
0249 /* Read/write from/to registers */
0250 struct genwqe_reg_io {
0251     __u64 num;      /* register offset/address */
0252     __u64 val64;
0253 };
0254
0255 /*
0256  * All registers of our card will return values not equal this values.
0257  * If we see IO_ILLEGAL_VALUE on any of our MMIO register reads, the
0258  * card can be considered as unusable. It will need recovery.
0259  */
0260 #define IO_ILLEGAL_VALUE        0xffffffffffffffffull
0261
0262 /*
0263  * Generic DDCB execution interface.
0264  *
0265  * This interface is a first prototype resulting from discussions we
0266  * had with other teams which wanted to use the Genwqe card. It allows
0267  * to issue a DDCB request in a generic way. The request will block
0268  * until it finishes or time out with error.
0269  *
0270  * Some DDCBs require DMA addresses to be specified in the ASIV
0271  * block. The interface provies the capability to let the kernel
0272  * driver know where those addresses are by specifying the ATS field,
0273  * such that it can replace the user-space addresses with appropriate
0274  * DMA addresses or DMA addresses of a scatter gather list which is
0275  * dynamically created.
0276  *
0277  * Our hardware will refuse DDCB execution if the ATS field is not as
0278  * expected. That means the DDCB execution engine in the chip knows
0279  * where it expects DMA addresses within the ASIV part of the DDCB and
0280  * will check that against the ATS field definition. Any invalid or
0281  * unknown ATS content will lead to DDCB refusal.
0282  */
0283
0284 /* Genwqe chip Units */
0285 #define DDCB_ACFUNC_SLU         0x00  /* chip service layer unit */
0286 #define DDCB_ACFUNC_APP         0x01  /* chip application */
0287
0288 /* DDCB return codes (RETC) */
0289 #define DDCB_RETC_IDLE          0x0000 /* Unexecuted/DDCB created */
0290 #define DDCB_RETC_PENDING       0x0101 /* Pending Execution */
0291 #define DDCB_RETC_COMPLETE      0x0102 /* Cmd complete. No error */
0292 #define DDCB_RETC_FAULT         0x0104 /* App Err, recoverable */
0293 #define DDCB_RETC_ERROR         0x0108 /* App Err, non-recoverable */
0294 #define DDCB_RETC_FORCED_ERROR      0x01ff /* overwritten by driver  */
0295
0296 #define DDCB_RETC_UNEXEC        0x0110 /* Unexe/Removed from queue */
0297 #define DDCB_RETC_TERM          0x0120 /* Terminated */
0298 #define DDCB_RETC_RES0          0x0140 /* Reserved */
0299 #define DDCB_RETC_RES1          0x0180 /* Reserved */
0300
0301 /* DDCB Command Options (CMDOPT) */
0302 #define DDCB_OPT_ECHO_FORCE_NO      0x0000 /* ECHO DDCB */
0303 #define DDCB_OPT_ECHO_FORCE_102     0x0001 /* force return code */
0304 #define DDCB_OPT_ECHO_FORCE_104     0x0002
0305 #define DDCB_OPT_ECHO_FORCE_108     0x0003
0306
0307 #define DDCB_OPT_ECHO_FORCE_110     0x0004 /* only on PF ! */
0308 #define DDCB_OPT_ECHO_FORCE_120     0x0005
0309 #define DDCB_OPT_ECHO_FORCE_140     0x0006
0310 #define DDCB_OPT_ECHO_FORCE_180     0x0007
0311
0312 #define DDCB_OPT_ECHO_COPY_NONE     (0 << 5)
0313 #define DDCB_OPT_ECHO_COPY_ALL      (1 << 5)
0314
0315 /* Definitions of Service Layer Commands */
0316 #define SLCMD_ECHO_SYNC         0x00 /* PF/VF */
0317 #define SLCMD_MOVE_FLASH        0x06 /* PF only */
0318 #define SLCMD_MOVE_FLASH_FLAGS_MODE 0x03 /* bit 0 and 1 used for mode */
0319 #define SLCMD_MOVE_FLASH_FLAGS_DLOAD    0   /* mode: download  */
0320 #define SLCMD_MOVE_FLASH_FLAGS_EMUL 1   /* mode: emulation */
0321 #define SLCMD_MOVE_FLASH_FLAGS_UPLOAD   2   /* mode: upload    */
0322 #define SLCMD_MOVE_FLASH_FLAGS_VERIFY   3   /* mode: verify    */
0323 #define SLCMD_MOVE_FLASH_FLAG_NOTAP (1 << 2)/* just dump DDCB and exit */
0324 #define SLCMD_MOVE_FLASH_FLAG_POLL  (1 << 3)/* wait for RETC >= 0102   */
0325 #define SLCMD_MOVE_FLASH_FLAG_PARTITION (1 << 4)
0326 #define SLCMD_MOVE_FLASH_FLAG_ERASE (1 << 5)
0327
0328 enum genwqe_card_state {
0329     GENWQE_CARD_UNUSED = 0,
0330     GENWQE_CARD_USED = 1,
0331     GENWQE_CARD_FATAL_ERROR = 2,
0332     GENWQE_CARD_RELOAD_BITSTREAM = 3,
0333     GENWQE_CARD_STATE_MAX,
0334 };
0335
0336 /* common struct for chip image exchange */
0337 struct genwqe_bitstream {
0338     __u64 data_addr;        /* pointer to image data */
0339     __u32 size;         /* size of image file */
0340     __u32 crc;          /* crc of this image */
0341     __u64 target_addr;      /* starting address in Flash */
0342     __u32 partition;        /* '0', '1', or 'v' */
0343     __u32 uid;          /* 1=host/x=dram */
0344
0345     __u64 slu_id;           /* informational/sim: SluID */
0346     __u64 app_id;           /* informational/sim: AppID */
0347
0348     __u16 retc;         /* returned from processing */
0349     __u16 attn;         /* attention code from processing */
0350     __u32 progress;         /* progress code from processing */
0351 };
0352
0353 /* Issuing a specific DDCB command */
0354 #define DDCB_LENGTH         256 /* for debug data */
0355 #define DDCB_ASIV_LENGTH        104 /* len of the DDCB ASIV array */
0356 #define DDCB_ASIV_LENGTH_ATS        96  /* ASIV in ATS architecture */
0357 #define DDCB_ASV_LENGTH         64  /* len of the DDCB ASV array  */
0358 #define DDCB_FIXUPS         12  /* maximum number of fixups */
0359
0360 struct genwqe_debug_data {
0361     char driver_version[64];
0362     __u64 slu_unitcfg;
0363     __u64 app_unitcfg;
0364
0365     __u8  ddcb_before[DDCB_LENGTH];
0366     __u8  ddcb_prev[DDCB_LENGTH];
0367     __u8  ddcb_finished[DDCB_LENGTH];
0368 };
0369
0370 /*
0371  * Address Translation Specification (ATS) definitions
0372  *
0373  * Each 4 bit within the ATS 64-bit word specify the required address
0374  * translation at the defined offset.
0375  *
0376  * 63 LSB
0377  *         6666.5555.5555.5544.4444.4443.3333.3333 ... 11
0378  *         3210.9876.5432.1098.7654.3210.9876.5432 ... 1098.7654.3210
0379  *
0380  * offset: 0x00 0x08 0x10 0x18 0x20 0x28 0x30 0x38 ... 0x68 0x70 0x78
0381  *         res  res  res  res  ASIV ...
0382  * The first 4 entries in the ATS word are reserved. The following nibbles
0383  * each describe at an 8 byte offset the format of the required data.
0384  */
0385 #define ATS_TYPE_DATA           0x0ull /* data  */
0386 #define ATS_TYPE_FLAT_RD        0x4ull /* flat buffer read only */
0387 #define ATS_TYPE_FLAT_RDWR      0x5ull /* flat buffer read/write */
0388 #define ATS_TYPE_SGL_RD         0x6ull /* sgl read only */
0389 #define ATS_TYPE_SGL_RDWR       0x7ull /* sgl read/write */
0390
0391 #define ATS_SET_FLAGS(_struct, _field, _flags)              \
0392     (((_flags) & 0xf) << (44 - (4 * (offsetof(_struct, _field) / 8))))
0393
0394 #define ATS_GET_FLAGS(_ats, _byte_offs)                 \
0395     (((_ats)      >> (44 - (4 * ((_byte_offs) / 8)))) & 0xf)
0396
0397 /**
0398  * struct genwqe_ddcb_cmd - User parameter for generic DDCB commands
0399  *
0400  * On the way into the kernel the driver will read the whole data
0401  * structure. On the way out the driver will not copy the ASIV data
0402  * back to user-space.
0403  */
0404 struct genwqe_ddcb_cmd {
0405     /* START of data copied to/from driver */
0406     __u64 next_addr;        /* chaining genwqe_ddcb_cmd */
0407     __u64 flags;            /* reserved */
0408
0409     __u8  acfunc;           /* accelerators functional unit */
0410     __u8  cmd;          /* command to execute */
0411     __u8  asiv_length;      /* used parameter length */
0412     __u8  asv_length;       /* length of valid return values  */
0413     __u16 cmdopts;          /* command options */
0414     __u16 retc;         /* return code from processing    */
0415
0416     __u16 attn;         /* attention code from processing */
0417     __u16 vcrc;         /* variant crc16 */
0418     __u32 progress;         /* progress code from processing  */
0419
0420     __u64 deque_ts;         /* dequeue time stamp */
0421     __u64 cmplt_ts;         /* completion time stamp */
0422     __u64 disp_ts;          /* SW processing start */
0423
0424     /* move to end and avoid copy-back */
0425     __u64 ddata_addr;       /* collect debug data */
0426
0427     /* command specific values */
0428     __u8  asv[DDCB_ASV_LENGTH];
0429
0430     /* END of data copied from driver */
0431     union {
0432         struct {
0433             __u64 ats;
0434             __u8  asiv[DDCB_ASIV_LENGTH_ATS];
0435         };
0436         /* used for flash update to keep it backward compatible */
0437         __u8 __asiv[DDCB_ASIV_LENGTH];
0438     };
0439     /* END of data copied to driver */
0440 };
0441
0442 #define GENWQE_IOC_CODE     0xa5
0443
0444 /* Access functions */
0445 #define GENWQE_READ_REG64   _IOR(GENWQE_IOC_CODE, 30, struct genwqe_reg_io)
0446 #define GENWQE_WRITE_REG64  _IOW(GENWQE_IOC_CODE, 31, struct genwqe_reg_io)
0447 #define GENWQE_READ_REG32   _IOR(GENWQE_IOC_CODE, 32, struct genwqe_reg_io)
0448 #define GENWQE_WRITE_REG32  _IOW(GENWQE_IOC_CODE, 33, struct genwqe_reg_io)
0449 #define GENWQE_READ_REG16   _IOR(GENWQE_IOC_CODE, 34, struct genwqe_reg_io)
0450 #define GENWQE_WRITE_REG16  _IOW(GENWQE_IOC_CODE, 35, struct genwqe_reg_io)
0451
0452 #define GENWQE_GET_CARD_STATE _IOR(GENWQE_IOC_CODE, 36, enum genwqe_card_state)
0453
0454 /**
0455  * struct genwqe_mem - Memory pinning/unpinning information
0456  * @addr:          virtual user space address
0457  * @size:          size of the area pin/dma-map/unmap
0458  * direction:      0: read/1: read and write
0459  *
0460  * Avoid pinning and unpinning of memory pages dynamically. Instead
0461  * the idea is to pin the whole buffer space required for DDCB
0462  * opertionas in advance. The driver will reuse this pinning and the
0463  * memory associated with it to setup the sglists for the DDCB
0464  * requests without the need to allocate and free memory or map and
0465  * unmap to get the DMA addresses.
0466  *
0467  * The inverse operation needs to be called after the pinning is not
0468  * needed anymore. The pinnings else the pinnings will get removed
0469  * after the device is closed. Note that pinnings will required
0470  * memory.
0471  */
0472 struct genwqe_mem {
0473     __u64 addr;
0474     __u64 size;
0475     __u64 direction;
0476     __u64 flags;
0477 };
0478
0479 #define GENWQE_PIN_MEM        _IOWR(GENWQE_IOC_CODE, 40, struct genwqe_mem)
0480 #define GENWQE_UNPIN_MEM      _IOWR(GENWQE_IOC_CODE, 41, struct genwqe_mem)
0481
0482 /*
0483  * Generic synchronous DDCB execution interface.
0484  * Synchronously execute a DDCB.
0485  *
0486  * Return: 0 on success or negative error code.
0487  *         -EINVAL: Invalid parameters (ASIV_LEN, ASV_LEN, illegal fixups
0488  *                  no mappings found/could not create mappings
0489  *         -EFAULT: illegal addresses in fixups, purging failed
0490  *         -EBADMSG: enqueing failed, retc != DDCB_RETC_COMPLETE
0491  */
0492 #define GENWQE_EXECUTE_DDCB                 \
0493     _IOWR(GENWQE_IOC_CODE, 50, struct genwqe_ddcb_cmd)
0494
0495 #define GENWQE_EXECUTE_RAW_DDCB                 \
0496     _IOWR(GENWQE_IOC_CODE, 51, struct genwqe_ddcb_cmd)
0497
0498 /* Service Layer functions (PF only) */
0499 #define GENWQE_SLU_UPDATE  _IOWR(GENWQE_IOC_CODE, 80, struct genwqe_bitstream)
0500 #define GENWQE_SLU_READ    _IOWR(GENWQE_IOC_CODE, 81, struct genwqe_bitstream)
0501
0502 #endif  /* __GENWQE_CARD_H__ */