uapi/linux/fpga-dfl.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * Header File for FPGA DFL User API
0004  *
0005  * Copyright (C) 2017-2018 Intel Corporation, Inc.
0006  *
0007  * Authors:
0008  *   Kang Luwei <luwei.kang@intel.com>
0009  *   Zhang Yi <yi.z.zhang@intel.com>
0010  *   Wu Hao <hao.wu@intel.com>
0011  *   Xiao Guangrong <guangrong.xiao@linux.intel.com>
0012  */
0013
0014 #ifndef _UAPI_LINUX_FPGA_DFL_H
0015 #define _UAPI_LINUX_FPGA_DFL_H
0016
0017 #include <linux/types.h>
0018 #include <linux/ioctl.h>
0019
0020 #define DFL_FPGA_API_VERSION 0
0021
0022 /*
0023  * The IOCTL interface for DFL based FPGA is designed for extensibility by
0024  * embedding the structure length (argsz) and flags into structures passed
0025  * between kernel and userspace. This design referenced the VFIO IOCTL
0026  * interface (include/uapi/linux/vfio.h).
0027  */
0028
0029 #define DFL_FPGA_MAGIC 0xB6
0030
0031 #define DFL_FPGA_BASE 0
0032 #define DFL_PORT_BASE 0x40
0033 #define DFL_FME_BASE 0x80
0034
0035 /* Common IOCTLs for both FME and AFU file descriptor */
0036
0037 /**
0038  * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
0039  *
0040  * Report the version of the driver API.
0041  * Return: Driver API Version.
0042  */
0043
0044 #define DFL_FPGA_GET_API_VERSION    _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
0045
0046 /**
0047  * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
0048  *
0049  * Check whether an extension is supported.
0050  * Return: 0 if not supported, otherwise the extension is supported.
0051  */
0052
0053 #define DFL_FPGA_CHECK_EXTENSION    _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
0054
0055 /* IOCTLs for AFU file descriptor */
0056
0057 /**
0058  * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
0059  *
0060  * Reset the FPGA Port and its AFU. No parameters are supported.
0061  * Userspace can do Port reset at any time, e.g. during DMA or PR. But
0062  * it should never cause any system level issue, only functional failure
0063  * (e.g. DMA or PR operation failure) and be recoverable from the failure.
0064  * Return: 0 on success, -errno of failure
0065  */
0066
0067 #define DFL_FPGA_PORT_RESET     _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
0068
0069 /**
0070  * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
0071  *                      struct dfl_fpga_port_info)
0072  *
0073  * Retrieve information about the fpga port.
0074  * Driver fills the info in provided struct dfl_fpga_port_info.
0075  * Return: 0 on success, -errno on failure.
0076  */
0077 struct dfl_fpga_port_info {
0078     /* Input */
0079     __u32 argsz;        /* Structure length */
0080     /* Output */
0081     __u32 flags;        /* Zero for now */
0082     __u32 num_regions;  /* The number of supported regions */
0083     __u32 num_umsgs;    /* The number of allocated umsgs */
0084 };
0085
0086 #define DFL_FPGA_PORT_GET_INFO      _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)
0087
0088 /**
0089  * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2,
0090  *                  struct dfl_fpga_port_region_info)
0091  *
0092  * Retrieve information about a device memory region.
0093  * Caller provides struct dfl_fpga_port_region_info with index value set.
0094  * Driver returns the region info in other fields.
0095  * Return: 0 on success, -errno on failure.
0096  */
0097 struct dfl_fpga_port_region_info {
0098     /* input */
0099     __u32 argsz;        /* Structure length */
0100     /* Output */
0101     __u32 flags;        /* Access permission */
0102 #define DFL_PORT_REGION_READ    (1 << 0)    /* Region is readable */
0103 #define DFL_PORT_REGION_WRITE   (1 << 1)    /* Region is writable */
0104 #define DFL_PORT_REGION_MMAP    (1 << 2)    /* Can be mmaped to userspace */
0105     /* Input */
0106     __u32 index;        /* Region index */
0107 #define DFL_PORT_REGION_INDEX_AFU   0   /* AFU */
0108 #define DFL_PORT_REGION_INDEX_STP   1   /* Signal Tap */
0109     __u32 padding;
0110     /* Output */
0111     __u64 size;     /* Region size (bytes) */
0112     __u64 offset;       /* Region offset from start of device fd */
0113 };
0114
0115 #define DFL_FPGA_PORT_GET_REGION_INFO   _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
0116
0117 /**
0118  * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3,
0119  *                      struct dfl_fpga_port_dma_map)
0120  *
0121  * Map the dma memory per user_addr and length which are provided by caller.
0122  * Driver fills the iova in provided struct afu_port_dma_map.
0123  * This interface only accepts page-size aligned user memory for dma mapping.
0124  * Return: 0 on success, -errno on failure.
0125  */
0126 struct dfl_fpga_port_dma_map {
0127     /* Input */
0128     __u32 argsz;        /* Structure length */
0129     __u32 flags;        /* Zero for now */
0130     __u64 user_addr;        /* Process virtual address */
0131     __u64 length;           /* Length of mapping (bytes)*/
0132     /* Output */
0133     __u64 iova;             /* IO virtual address */
0134 };
0135
0136 #define DFL_FPGA_PORT_DMA_MAP       _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)
0137
0138 /**
0139  * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4,
0140  *                      struct dfl_fpga_port_dma_unmap)
0141  *
0142  * Unmap the dma memory per iova provided by caller.
0143  * Return: 0 on success, -errno on failure.
0144  */
0145 struct dfl_fpga_port_dma_unmap {
0146     /* Input */
0147     __u32 argsz;        /* Structure length */
0148     __u32 flags;        /* Zero for now */
0149     __u64 iova;     /* IO virtual address */
0150 };
0151
0152 #define DFL_FPGA_PORT_DMA_UNMAP     _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)
0153
0154 /**
0155  * struct dfl_fpga_irq_set - the argument for DFL_FPGA_XXX_SET_IRQ ioctl.
0156  *
0157  * @start: Index of the first irq.
0158  * @count: The number of eventfd handler.
0159  * @evtfds: Eventfd handlers.
0160  */
0161 struct dfl_fpga_irq_set {
0162     __u32 start;
0163     __u32 count;
0164     __s32 evtfds[];
0165 };
0166
0167 /**
0168  * DFL_FPGA_PORT_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5,
0169  *                              __u32 num_irqs)
0170  *
0171  * Get the number of irqs supported by the fpga port error reporting private
0172  * feature. Currently hardware supports up to 1 irq.
0173  * Return: 0 on success, -errno on failure.
0174  */
0175 #define DFL_FPGA_PORT_ERR_GET_IRQ_NUM   _IOR(DFL_FPGA_MAGIC,    \
0176                          DFL_PORT_BASE + 5, __u32)
0177
0178 /**
0179  * DFL_FPGA_PORT_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6,
0180  *                      struct dfl_fpga_irq_set)
0181  *
0182  * Set fpga port error reporting interrupt trigger if evtfds[n] is valid.
0183  * Unset related interrupt trigger if evtfds[n] is a negative value.
0184  * Return: 0 on success, -errno on failure.
0185  */
0186 #define DFL_FPGA_PORT_ERR_SET_IRQ   _IOW(DFL_FPGA_MAGIC,    \
0187                          DFL_PORT_BASE + 6, \
0188                          struct dfl_fpga_irq_set)
0189
0190 /**
0191  * DFL_FPGA_PORT_UINT_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7,
0192  *                              __u32 num_irqs)
0193  *
0194  * Get the number of irqs supported by the fpga AFU interrupt private
0195  * feature.
0196  * Return: 0 on success, -errno on failure.
0197  */
0198 #define DFL_FPGA_PORT_UINT_GET_IRQ_NUM  _IOR(DFL_FPGA_MAGIC,    \
0199                          DFL_PORT_BASE + 7, __u32)
0200
0201 /**
0202  * DFL_FPGA_PORT_UINT_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8,
0203  *                      struct dfl_fpga_irq_set)
0204  *
0205  * Set fpga AFU interrupt trigger if evtfds[n] is valid.
0206  * Unset related interrupt trigger if evtfds[n] is a negative value.
0207  * Return: 0 on success, -errno on failure.
0208  */
0209 #define DFL_FPGA_PORT_UINT_SET_IRQ  _IOW(DFL_FPGA_MAGIC,    \
0210                          DFL_PORT_BASE + 8, \
0211                          struct dfl_fpga_irq_set)
0212
0213 /* IOCTLs for FME file descriptor */
0214
0215 /**
0216  * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0,
0217  *                      struct dfl_fpga_fme_port_pr)
0218  *
0219  * Driver does Partial Reconfiguration based on Port ID and Buffer (Image)
0220  * provided by caller.
0221  * Return: 0 on success, -errno on failure.
0222  * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
0223  * some errors during PR, under this case, the user can fetch HW error info
0224  * from the status of FME's fpga manager.
0225  */
0226
0227 struct dfl_fpga_fme_port_pr {
0228     /* Input */
0229     __u32 argsz;        /* Structure length */
0230     __u32 flags;        /* Zero for now */
0231     __u32 port_id;
0232     __u32 buffer_size;
0233     __u64 buffer_address;   /* Userspace address to the buffer for PR */
0234 };
0235
0236 #define DFL_FPGA_FME_PORT_PR    _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
0237
0238 /**
0239  * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1,
0240  *                      int port_id)
0241  *
0242  * Driver releases the port per Port ID provided by caller.
0243  * Return: 0 on success, -errno on failure.
0244  */
0245 #define DFL_FPGA_FME_PORT_RELEASE   _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int)
0246
0247 /**
0248  * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2,
0249  *                      int port_id)
0250  *
0251  * Driver assigns the port back per Port ID provided by caller.
0252  * Return: 0 on success, -errno on failure.
0253  */
0254 #define DFL_FPGA_FME_PORT_ASSIGN     _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int)
0255
0256 /**
0257  * DFL_FPGA_FME_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3,
0258  *                          __u32 num_irqs)
0259  *
0260  * Get the number of irqs supported by the fpga fme error reporting private
0261  * feature. Currently hardware supports up to 1 irq.
0262  * Return: 0 on success, -errno on failure.
0263  */
0264 #define DFL_FPGA_FME_ERR_GET_IRQ_NUM    _IOR(DFL_FPGA_MAGIC,    \
0265                          DFL_FME_BASE + 3, __u32)
0266
0267 /**
0268  * DFL_FPGA_FME_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4,
0269  *                      struct dfl_fpga_irq_set)
0270  *
0271  * Set fpga fme error reporting interrupt trigger if evtfds[n] is valid.
0272  * Unset related interrupt trigger if evtfds[n] is a negative value.
0273  * Return: 0 on success, -errno on failure.
0274  */
0275 #define DFL_FPGA_FME_ERR_SET_IRQ    _IOW(DFL_FPGA_MAGIC,    \
0276                          DFL_FME_BASE + 4,  \
0277                          struct dfl_fpga_irq_set)
0278
0279 #endif /* _UAPI_LINUX_FPGA_DFL_H */