uapi/drm/via_drm.h

0001 /*
0002  * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
0003  * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
0004  *
0005  * Permission is hereby granted, free of charge, to any person obtaining a
0006  * copy of this software and associated documentation files (the "Software"),
0007  * to deal in the Software without restriction, including without limitation
0008  * the rights to use, copy, modify, merge, publish, distribute, sub license,
0009  * and/or sell copies of the Software, and to permit persons to whom the
0010  * Software is furnished to do so, subject to the following conditions:
0011  *
0012  * The above copyright notice and this permission notice (including the
0013  * next paragraph) shall be included in all copies or substantial portions
0014  * of the Software.
0015  *
0016  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0017  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0018  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0019  * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0020  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0021  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
0022  * DEALINGS IN THE SOFTWARE.
0023  */
0024 #ifndef _VIA_DRM_H_
0025 #define _VIA_DRM_H_
0026
0027 #include "drm.h"
0028
0029 #if defined(__cplusplus)
0030 extern "C" {
0031 #endif
0032
0033 /* WARNING: These defines must be the same as what the Xserver uses.
0034  * if you change them, you must change the defines in the Xserver.
0035  */
0036
0037 #ifndef _VIA_DEFINES_
0038 #define _VIA_DEFINES_
0039
0040
0041 #define VIA_NR_SAREA_CLIPRECTS      8
0042 #define VIA_NR_XVMC_PORTS               10
0043 #define VIA_NR_XVMC_LOCKS               5
0044 #define VIA_MAX_CACHELINE_SIZE          64
0045 #define XVMCLOCKPTR(saPriv,lockNo)                  \
0046     ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
0047                       (VIA_MAX_CACHELINE_SIZE - 1)) &   \
0048                      ~(VIA_MAX_CACHELINE_SIZE - 1)) +   \
0049                     VIA_MAX_CACHELINE_SIZE*(lockNo)))
0050
0051 /* Each region is a minimum of 64k, and there are at most 64 of them.
0052  */
0053 #define VIA_NR_TEX_REGIONS 64
0054 #define VIA_LOG_MIN_TEX_REGION_SIZE 16
0055 #endif
0056
0057 #define VIA_UPLOAD_TEX0IMAGE  0x1   /* handled clientside */
0058 #define VIA_UPLOAD_TEX1IMAGE  0x2   /* handled clientside */
0059 #define VIA_UPLOAD_CTX        0x4
0060 #define VIA_UPLOAD_BUFFERS    0x8
0061 #define VIA_UPLOAD_TEX0       0x10
0062 #define VIA_UPLOAD_TEX1       0x20
0063 #define VIA_UPLOAD_CLIPRECTS  0x40
0064 #define VIA_UPLOAD_ALL        0xff
0065
0066 /* VIA specific ioctls */
0067 #define DRM_VIA_ALLOCMEM    0x00
0068 #define DRM_VIA_FREEMEM         0x01
0069 #define DRM_VIA_AGP_INIT    0x02
0070 #define DRM_VIA_FB_INIT         0x03
0071 #define DRM_VIA_MAP_INIT    0x04
0072 #define DRM_VIA_DEC_FUTEX       0x05
0073 #define NOT_USED
0074 #define DRM_VIA_DMA_INIT    0x07
0075 #define DRM_VIA_CMDBUFFER   0x08
0076 #define DRM_VIA_FLUSH           0x09
0077 #define DRM_VIA_PCICMD          0x0a
0078 #define DRM_VIA_CMDBUF_SIZE 0x0b
0079 #define NOT_USED
0080 #define DRM_VIA_WAIT_IRQ        0x0d
0081 #define DRM_VIA_DMA_BLIT        0x0e
0082 #define DRM_VIA_BLIT_SYNC       0x0f
0083
0084 #define DRM_IOCTL_VIA_ALLOCMEM    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
0085 #define DRM_IOCTL_VIA_FREEMEM     DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
0086 #define DRM_IOCTL_VIA_AGP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
0087 #define DRM_IOCTL_VIA_FB_INIT     DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
0088 #define DRM_IOCTL_VIA_MAP_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
0089 #define DRM_IOCTL_VIA_DEC_FUTEX   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
0090 #define DRM_IOCTL_VIA_DMA_INIT    DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
0091 #define DRM_IOCTL_VIA_CMDBUFFER   DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
0092 #define DRM_IOCTL_VIA_FLUSH   DRM_IO(  DRM_COMMAND_BASE + DRM_VIA_FLUSH)
0093 #define DRM_IOCTL_VIA_PCICMD      DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
0094 #define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
0095                         drm_via_cmdbuf_size_t)
0096 #define DRM_IOCTL_VIA_WAIT_IRQ    DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
0097 #define DRM_IOCTL_VIA_DMA_BLIT    DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
0098 #define DRM_IOCTL_VIA_BLIT_SYNC   DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
0099
0100 /* Indices into buf.Setup where various bits of state are mirrored per
0101  * context and per buffer.  These can be fired at the card as a unit,
0102  * or in a piecewise fashion as required.
0103  */
0104
0105 #define VIA_TEX_SETUP_SIZE 8
0106
0107 /* Flags for clear ioctl
0108  */
0109 #define VIA_FRONT   0x1
0110 #define VIA_BACK    0x2
0111 #define VIA_DEPTH   0x4
0112 #define VIA_STENCIL 0x8
0113 #define VIA_MEM_VIDEO   0   /* matches drm constant */
0114 #define VIA_MEM_AGP     1   /* matches drm constant */
0115 #define VIA_MEM_SYSTEM  2
0116 #define VIA_MEM_MIXED   3
0117 #define VIA_MEM_UNKNOWN 4
0118
0119 typedef struct {
0120     __u32 offset;
0121     __u32 size;
0122 } drm_via_agp_t;
0123
0124 typedef struct {
0125     __u32 offset;
0126     __u32 size;
0127 } drm_via_fb_t;
0128
0129 typedef struct {
0130     __u32 context;
0131     __u32 type;
0132     __u32 size;
0133     unsigned long index;
0134     unsigned long offset;
0135 } drm_via_mem_t;
0136
0137 typedef struct _drm_via_init {
0138     enum {
0139         VIA_INIT_MAP = 0x01,
0140         VIA_CLEANUP_MAP = 0x02
0141     } func;
0142
0143     unsigned long sarea_priv_offset;
0144     unsigned long fb_offset;
0145     unsigned long mmio_offset;
0146     unsigned long agpAddr;
0147 } drm_via_init_t;
0148
0149 typedef struct _drm_via_futex {
0150     enum {
0151         VIA_FUTEX_WAIT = 0x00,
0152         VIA_FUTEX_WAKE = 0X01
0153     } func;
0154     __u32 ms;
0155     __u32 lock;
0156     __u32 val;
0157 } drm_via_futex_t;
0158
0159 typedef struct _drm_via_dma_init {
0160     enum {
0161         VIA_INIT_DMA = 0x01,
0162         VIA_CLEANUP_DMA = 0x02,
0163         VIA_DMA_INITIALIZED = 0x03
0164     } func;
0165
0166     unsigned long offset;
0167     unsigned long size;
0168     unsigned long reg_pause_addr;
0169 } drm_via_dma_init_t;
0170
0171 typedef struct _drm_via_cmdbuffer {
0172     char __user *buf;
0173     unsigned long size;
0174 } drm_via_cmdbuffer_t;
0175
0176 /* Warning: If you change the SAREA structure you must change the Xserver
0177  * structure as well */
0178
0179 typedef struct _drm_via_tex_region {
0180     unsigned char next, prev;   /* indices to form a circular LRU  */
0181     unsigned char inUse;    /* owned by a client, or free? */
0182     int age;        /* tracked by clients to update local LRU's */
0183 } drm_via_tex_region_t;
0184
0185 typedef struct _drm_via_sarea {
0186     unsigned int dirty;
0187     unsigned int nbox;
0188     struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
0189     drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
0190     int texAge;     /* last time texture was uploaded */
0191     int ctxOwner;       /* last context to upload state */
0192     int vertexPrim;
0193
0194     /*
0195      * Below is for XvMC.
0196      * We want the lock integers alone on, and aligned to, a cache line.
0197      * Therefore this somewhat strange construct.
0198      */
0199
0200     char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
0201
0202     unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
0203     unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
0204     unsigned int XvMCCtxNoGrabbed;  /* Last context to hold decoder */
0205
0206     /* Used by the 3d driver only at this point, for pageflipping:
0207      */
0208     unsigned int pfCurrentOffset;
0209 } drm_via_sarea_t;
0210
0211 typedef struct _drm_via_cmdbuf_size {
0212     enum {
0213         VIA_CMDBUF_SPACE = 0x01,
0214         VIA_CMDBUF_LAG = 0x02
0215     } func;
0216     int wait;
0217     __u32 size;
0218 } drm_via_cmdbuf_size_t;
0219
0220 typedef enum {
0221     VIA_IRQ_ABSOLUTE = 0x0,
0222     VIA_IRQ_RELATIVE = 0x1,
0223     VIA_IRQ_SIGNAL = 0x10000000,
0224     VIA_IRQ_FORCE_SEQUENCE = 0x20000000
0225 } via_irq_seq_type_t;
0226
0227 #define VIA_IRQ_FLAGS_MASK 0xF0000000
0228
0229 enum drm_via_irqs {
0230     drm_via_irq_hqv0 = 0,
0231     drm_via_irq_hqv1,
0232     drm_via_irq_dma0_dd,
0233     drm_via_irq_dma0_td,
0234     drm_via_irq_dma1_dd,
0235     drm_via_irq_dma1_td,
0236     drm_via_irq_num
0237 };
0238
0239 struct drm_via_wait_irq_request {
0240     unsigned irq;
0241     via_irq_seq_type_t type;
0242     __u32 sequence;
0243     __u32 signal;
0244 };
0245
0246 typedef union drm_via_irqwait {
0247     struct drm_via_wait_irq_request request;
0248     struct drm_wait_vblank_reply reply;
0249 } drm_via_irqwait_t;
0250
0251 typedef struct drm_via_blitsync {
0252     __u32 sync_handle;
0253     unsigned engine;
0254 } drm_via_blitsync_t;
0255
0256 /* - * Below,"flags" is currently unused but will be used for possible future
0257  * extensions like kernel space bounce buffers for bad alignments and
0258  * blit engine busy-wait polling for better latency in the absence of
0259  * interrupts.
0260  */
0261
0262 typedef struct drm_via_dmablit {
0263     __u32 num_lines;
0264     __u32 line_length;
0265
0266     __u32 fb_addr;
0267     __u32 fb_stride;
0268
0269     unsigned char *mem_addr;
0270     __u32 mem_stride;
0271
0272     __u32 flags;
0273     int to_fb;
0274
0275     drm_via_blitsync_t sync;
0276 } drm_via_dmablit_t;
0277
0278 #if defined(__cplusplus)
0279 }
0280 #endif
0281
0282 #endif              /* _VIA_DRM_H_ */