uapi/drm/v3d_drm.h

0001 /*
0002  * Copyright © 2014-2018 Broadcom
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  */
0023
0024 #ifndef _V3D_DRM_H_
0025 #define _V3D_DRM_H_
0026
0027 #include "drm.h"
0028
0029 #if defined(__cplusplus)
0030 extern "C" {
0031 #endif
0032
0033 #define DRM_V3D_SUBMIT_CL                         0x00
0034 #define DRM_V3D_WAIT_BO                           0x01
0035 #define DRM_V3D_CREATE_BO                         0x02
0036 #define DRM_V3D_MMAP_BO                           0x03
0037 #define DRM_V3D_GET_PARAM                         0x04
0038 #define DRM_V3D_GET_BO_OFFSET                     0x05
0039 #define DRM_V3D_SUBMIT_TFU                        0x06
0040 #define DRM_V3D_SUBMIT_CSD                        0x07
0041 #define DRM_V3D_PERFMON_CREATE                    0x08
0042 #define DRM_V3D_PERFMON_DESTROY                   0x09
0043 #define DRM_V3D_PERFMON_GET_VALUES                0x0a
0044
0045 #define DRM_IOCTL_V3D_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
0046 #define DRM_IOCTL_V3D_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
0047 #define DRM_IOCTL_V3D_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
0048 #define DRM_IOCTL_V3D_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
0049 #define DRM_IOCTL_V3D_GET_PARAM           DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
0050 #define DRM_IOCTL_V3D_GET_BO_OFFSET       DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
0051 #define DRM_IOCTL_V3D_SUBMIT_TFU          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
0052 #define DRM_IOCTL_V3D_SUBMIT_CSD          DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
0053 #define DRM_IOCTL_V3D_PERFMON_CREATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_CREATE, \
0054                            struct drm_v3d_perfmon_create)
0055 #define DRM_IOCTL_V3D_PERFMON_DESTROY     DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_DESTROY, \
0056                            struct drm_v3d_perfmon_destroy)
0057 #define DRM_IOCTL_V3D_PERFMON_GET_VALUES  DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_PERFMON_GET_VALUES, \
0058                            struct drm_v3d_perfmon_get_values)
0059
0060 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE             0x01
0061 #define DRM_V3D_SUBMIT_EXTENSION          0x02
0062
0063 /* struct drm_v3d_extension - ioctl extensions
0064  *
0065  * Linked-list of generic extensions where the id identify which struct is
0066  * pointed by ext_data. Therefore, DRM_V3D_EXT_ID_* is used on id to identify
0067  * the extension type.
0068  */
0069 struct drm_v3d_extension {
0070     __u64 next;
0071     __u32 id;
0072 #define DRM_V3D_EXT_ID_MULTI_SYNC       0x01
0073     __u32 flags; /* mbz */
0074 };
0075
0076 /* struct drm_v3d_sem - wait/signal semaphore
0077  *
0078  * If binary semaphore, it only takes syncobj handle and ignores flags and
0079  * point fields. Point is defined for timeline syncobj feature.
0080  */
0081 struct drm_v3d_sem {
0082     __u32 handle; /* syncobj */
0083     /* rsv below, for future uses */
0084     __u32 flags;
0085     __u64 point;  /* for timeline sem support */
0086     __u64 mbz[2]; /* must be zero, rsv */
0087 };
0088
0089 /* Enum for each of the V3D queues. */
0090 enum v3d_queue {
0091     V3D_BIN,
0092     V3D_RENDER,
0093     V3D_TFU,
0094     V3D_CSD,
0095     V3D_CACHE_CLEAN,
0096 };
0097
0098 /**
0099  * struct drm_v3d_multi_sync - ioctl extension to add support multiples
0100  * syncobjs for commands submission.
0101  *
0102  * When an extension of DRM_V3D_EXT_ID_MULTI_SYNC id is defined, it points to
0103  * this extension to define wait and signal dependencies, instead of single
0104  * in/out sync entries on submitting commands. The field flags is used to
0105  * determine the stage to set wait dependencies.
0106  */
0107 struct drm_v3d_multi_sync {
0108     struct drm_v3d_extension base;
0109     /* Array of wait and signal semaphores */
0110     __u64 in_syncs;
0111     __u64 out_syncs;
0112
0113     /* Number of entries */
0114     __u32 in_sync_count;
0115     __u32 out_sync_count;
0116
0117     /* set the stage (v3d_queue) to sync */
0118     __u32 wait_stage;
0119
0120     __u32 pad; /* mbz */
0121 };
0122
0123 /**
0124  * struct drm_v3d_submit_cl - ioctl argument for submitting commands to the 3D
0125  * engine.
0126  *
0127  * This asks the kernel to have the GPU execute an optional binner
0128  * command list, and a render command list.
0129  *
0130  * The L1T, slice, L2C, L2T, and GCA caches will be flushed before
0131  * each CL executes.  The VCD cache should be flushed (if necessary)
0132  * by the submitted CLs.  The TLB writes are guaranteed to have been
0133  * flushed by the time the render done IRQ happens, which is the
0134  * trigger for out_sync.  Any dirtying of cachelines by the job (only
0135  * possible using TMU writes) must be flushed by the caller using the
0136  * DRM_V3D_SUBMIT_CL_FLUSH_CACHE_FLAG flag.
0137  */
0138 struct drm_v3d_submit_cl {
0139     /* Pointer to the binner command list.
0140      *
0141      * This is the first set of commands executed, which runs the
0142      * coordinate shader to determine where primitives land on the screen,
0143      * then writes out the state updates and draw calls necessary per tile
0144      * to the tile allocation BO.
0145      *
0146      * This BCL will block on any previous BCL submitted on the
0147      * same FD, but not on any RCL or BCLs submitted by other
0148      * clients -- that is left up to the submitter to control
0149      * using in_sync_bcl if necessary.
0150      */
0151     __u32 bcl_start;
0152
0153     /** End address of the BCL (first byte after the BCL) */
0154     __u32 bcl_end;
0155
0156     /* Offset of the render command list.
0157      *
0158      * This is the second set of commands executed, which will either
0159      * execute the tiles that have been set up by the BCL, or a fixed set
0160      * of tiles (in the case of RCL-only blits).
0161      *
0162      * This RCL will block on this submit's BCL, and any previous
0163      * RCL submitted on the same FD, but not on any RCL or BCLs
0164      * submitted by other clients -- that is left up to the
0165      * submitter to control using in_sync_rcl if necessary.
0166      */
0167     __u32 rcl_start;
0168
0169     /** End address of the RCL (first byte after the RCL) */
0170     __u32 rcl_end;
0171
0172     /** An optional sync object to wait on before starting the BCL. */
0173     __u32 in_sync_bcl;
0174     /** An optional sync object to wait on before starting the RCL. */
0175     __u32 in_sync_rcl;
0176     /** An optional sync object to place the completion fence in. */
0177     __u32 out_sync;
0178
0179     /* Offset of the tile alloc memory
0180      *
0181      * This is optional on V3D 3.3 (where the CL can set the value) but
0182      * required on V3D 4.1.
0183      */
0184     __u32 qma;
0185
0186     /** Size of the tile alloc memory. */
0187     __u32 qms;
0188
0189     /** Offset of the tile state data array. */
0190     __u32 qts;
0191
0192     /* Pointer to a u32 array of the BOs that are referenced by the job.
0193      */
0194     __u64 bo_handles;
0195
0196     /* Number of BO handles passed in (size is that times 4). */
0197     __u32 bo_handle_count;
0198
0199     /* DRM_V3D_SUBMIT_* properties */
0200     __u32 flags;
0201
0202     /* ID of the perfmon to attach to this job. 0 means no perfmon. */
0203     __u32 perfmon_id;
0204
0205     __u32 pad;
0206
0207     /* Pointer to an array of ioctl extensions*/
0208     __u64 extensions;
0209 };
0210
0211 /**
0212  * struct drm_v3d_wait_bo - ioctl argument for waiting for
0213  * completion of the last DRM_V3D_SUBMIT_CL on a BO.
0214  *
0215  * This is useful for cases where multiple processes might be
0216  * rendering to a BO and you want to wait for all rendering to be
0217  * completed.
0218  */
0219 struct drm_v3d_wait_bo {
0220     __u32 handle;
0221     __u32 pad;
0222     __u64 timeout_ns;
0223 };
0224
0225 /**
0226  * struct drm_v3d_create_bo - ioctl argument for creating V3D BOs.
0227  *
0228  * There are currently no values for the flags argument, but it may be
0229  * used in a future extension.
0230  */
0231 struct drm_v3d_create_bo {
0232     __u32 size;
0233     __u32 flags;
0234     /** Returned GEM handle for the BO. */
0235     __u32 handle;
0236     /**
0237      * Returned offset for the BO in the V3D address space.  This offset
0238      * is private to the DRM fd and is valid for the lifetime of the GEM
0239      * handle.
0240      *
0241      * This offset value will always be nonzero, since various HW
0242      * units treat 0 specially.
0243      */
0244     __u32 offset;
0245 };
0246
0247 /**
0248  * struct drm_v3d_mmap_bo - ioctl argument for mapping V3D BOs.
0249  *
0250  * This doesn't actually perform an mmap.  Instead, it returns the
0251  * offset you need to use in an mmap on the DRM device node.  This
0252  * means that tools like valgrind end up knowing about the mapped
0253  * memory.
0254  *
0255  * There are currently no values for the flags argument, but it may be
0256  * used in a future extension.
0257  */
0258 struct drm_v3d_mmap_bo {
0259     /** Handle for the object being mapped. */
0260     __u32 handle;
0261     __u32 flags;
0262     /** offset into the drm node to use for subsequent mmap call. */
0263     __u64 offset;
0264 };
0265
0266 enum drm_v3d_param {
0267     DRM_V3D_PARAM_V3D_UIFCFG,
0268     DRM_V3D_PARAM_V3D_HUB_IDENT1,
0269     DRM_V3D_PARAM_V3D_HUB_IDENT2,
0270     DRM_V3D_PARAM_V3D_HUB_IDENT3,
0271     DRM_V3D_PARAM_V3D_CORE0_IDENT0,
0272     DRM_V3D_PARAM_V3D_CORE0_IDENT1,
0273     DRM_V3D_PARAM_V3D_CORE0_IDENT2,
0274     DRM_V3D_PARAM_SUPPORTS_TFU,
0275     DRM_V3D_PARAM_SUPPORTS_CSD,
0276     DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
0277     DRM_V3D_PARAM_SUPPORTS_PERFMON,
0278     DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT,
0279 };
0280
0281 struct drm_v3d_get_param {
0282     __u32 param;
0283     __u32 pad;
0284     __u64 value;
0285 };
0286
0287 /**
0288  * Returns the offset for the BO in the V3D address space for this DRM fd.
0289  * This is the same value returned by drm_v3d_create_bo, if that was called
0290  * from this DRM fd.
0291  */
0292 struct drm_v3d_get_bo_offset {
0293     __u32 handle;
0294     __u32 offset;
0295 };
0296
0297 struct drm_v3d_submit_tfu {
0298     __u32 icfg;
0299     __u32 iia;
0300     __u32 iis;
0301     __u32 ica;
0302     __u32 iua;
0303     __u32 ioa;
0304     __u32 ios;
0305     __u32 coef[4];
0306     /* First handle is the output BO, following are other inputs.
0307      * 0 for unused.
0308      */
0309     __u32 bo_handles[4];
0310     /* sync object to block on before running the TFU job.  Each TFU
0311      * job will execute in the order submitted to its FD.  Synchronization
0312      * against rendering jobs requires using sync objects.
0313      */
0314     __u32 in_sync;
0315     /* Sync object to signal when the TFU job is done. */
0316     __u32 out_sync;
0317
0318     __u32 flags;
0319
0320     /* Pointer to an array of ioctl extensions*/
0321     __u64 extensions;
0322 };
0323
0324 /* Submits a compute shader for dispatch.  This job will block on any
0325  * previous compute shaders submitted on this fd, and any other
0326  * synchronization must be performed with in_sync/out_sync.
0327  */
0328 struct drm_v3d_submit_csd {
0329     __u32 cfg[7];
0330     __u32 coef[4];
0331
0332     /* Pointer to a u32 array of the BOs that are referenced by the job.
0333      */
0334     __u64 bo_handles;
0335
0336     /* Number of BO handles passed in (size is that times 4). */
0337     __u32 bo_handle_count;
0338
0339     /* sync object to block on before running the CSD job.  Each
0340      * CSD job will execute in the order submitted to its FD.
0341      * Synchronization against rendering/TFU jobs or CSD from
0342      * other fds requires using sync objects.
0343      */
0344     __u32 in_sync;
0345     /* Sync object to signal when the CSD job is done. */
0346     __u32 out_sync;
0347
0348     /* ID of the perfmon to attach to this job. 0 means no perfmon. */
0349     __u32 perfmon_id;
0350
0351     /* Pointer to an array of ioctl extensions*/
0352     __u64 extensions;
0353
0354     __u32 flags;
0355
0356     __u32 pad;
0357 };
0358
0359 enum {
0360     V3D_PERFCNT_FEP_VALID_PRIMTS_NO_PIXELS,
0361     V3D_PERFCNT_FEP_VALID_PRIMS,
0362     V3D_PERFCNT_FEP_EZ_NFCLIP_QUADS,
0363     V3D_PERFCNT_FEP_VALID_QUADS,
0364     V3D_PERFCNT_TLB_QUADS_STENCIL_FAIL,
0365     V3D_PERFCNT_TLB_QUADS_STENCILZ_FAIL,
0366     V3D_PERFCNT_TLB_QUADS_STENCILZ_PASS,
0367     V3D_PERFCNT_TLB_QUADS_ZERO_COV,
0368     V3D_PERFCNT_TLB_QUADS_NONZERO_COV,
0369     V3D_PERFCNT_TLB_QUADS_WRITTEN,
0370     V3D_PERFCNT_PTB_PRIM_VIEWPOINT_DISCARD,
0371     V3D_PERFCNT_PTB_PRIM_CLIP,
0372     V3D_PERFCNT_PTB_PRIM_REV,
0373     V3D_PERFCNT_QPU_IDLE_CYCLES,
0374     V3D_PERFCNT_QPU_ACTIVE_CYCLES_VERTEX_COORD_USER,
0375     V3D_PERFCNT_QPU_ACTIVE_CYCLES_FRAG,
0376     V3D_PERFCNT_QPU_CYCLES_VALID_INSTR,
0377     V3D_PERFCNT_QPU_CYCLES_TMU_STALL,
0378     V3D_PERFCNT_QPU_CYCLES_SCOREBOARD_STALL,
0379     V3D_PERFCNT_QPU_CYCLES_VARYINGS_STALL,
0380     V3D_PERFCNT_QPU_IC_HIT,
0381     V3D_PERFCNT_QPU_IC_MISS,
0382     V3D_PERFCNT_QPU_UC_HIT,
0383     V3D_PERFCNT_QPU_UC_MISS,
0384     V3D_PERFCNT_TMU_TCACHE_ACCESS,
0385     V3D_PERFCNT_TMU_TCACHE_MISS,
0386     V3D_PERFCNT_VPM_VDW_STALL,
0387     V3D_PERFCNT_VPM_VCD_STALL,
0388     V3D_PERFCNT_BIN_ACTIVE,
0389     V3D_PERFCNT_RDR_ACTIVE,
0390     V3D_PERFCNT_L2T_HITS,
0391     V3D_PERFCNT_L2T_MISSES,
0392     V3D_PERFCNT_CYCLE_COUNT,
0393     V3D_PERFCNT_QPU_CYCLES_STALLED_VERTEX_COORD_USER,
0394     V3D_PERFCNT_QPU_CYCLES_STALLED_FRAGMENT,
0395     V3D_PERFCNT_PTB_PRIMS_BINNED,
0396     V3D_PERFCNT_AXI_WRITES_WATCH_0,
0397     V3D_PERFCNT_AXI_READS_WATCH_0,
0398     V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_0,
0399     V3D_PERFCNT_AXI_READ_STALLS_WATCH_0,
0400     V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_0,
0401     V3D_PERFCNT_AXI_READ_BYTES_WATCH_0,
0402     V3D_PERFCNT_AXI_WRITES_WATCH_1,
0403     V3D_PERFCNT_AXI_READS_WATCH_1,
0404     V3D_PERFCNT_AXI_WRITE_STALLS_WATCH_1,
0405     V3D_PERFCNT_AXI_READ_STALLS_WATCH_1,
0406     V3D_PERFCNT_AXI_WRITE_BYTES_WATCH_1,
0407     V3D_PERFCNT_AXI_READ_BYTES_WATCH_1,
0408     V3D_PERFCNT_TLB_PARTIAL_QUADS,
0409     V3D_PERFCNT_TMU_CONFIG_ACCESSES,
0410     V3D_PERFCNT_L2T_NO_ID_STALL,
0411     V3D_PERFCNT_L2T_COM_QUE_STALL,
0412     V3D_PERFCNT_L2T_TMU_WRITES,
0413     V3D_PERFCNT_TMU_ACTIVE_CYCLES,
0414     V3D_PERFCNT_TMU_STALLED_CYCLES,
0415     V3D_PERFCNT_CLE_ACTIVE,
0416     V3D_PERFCNT_L2T_TMU_READS,
0417     V3D_PERFCNT_L2T_CLE_READS,
0418     V3D_PERFCNT_L2T_VCD_READS,
0419     V3D_PERFCNT_L2T_TMUCFG_READS,
0420     V3D_PERFCNT_L2T_SLC0_READS,
0421     V3D_PERFCNT_L2T_SLC1_READS,
0422     V3D_PERFCNT_L2T_SLC2_READS,
0423     V3D_PERFCNT_L2T_TMU_W_MISSES,
0424     V3D_PERFCNT_L2T_TMU_R_MISSES,
0425     V3D_PERFCNT_L2T_CLE_MISSES,
0426     V3D_PERFCNT_L2T_VCD_MISSES,
0427     V3D_PERFCNT_L2T_TMUCFG_MISSES,
0428     V3D_PERFCNT_L2T_SLC0_MISSES,
0429     V3D_PERFCNT_L2T_SLC1_MISSES,
0430     V3D_PERFCNT_L2T_SLC2_MISSES,
0431     V3D_PERFCNT_CORE_MEM_WRITES,
0432     V3D_PERFCNT_L2T_MEM_WRITES,
0433     V3D_PERFCNT_PTB_MEM_WRITES,
0434     V3D_PERFCNT_TLB_MEM_WRITES,
0435     V3D_PERFCNT_CORE_MEM_READS,
0436     V3D_PERFCNT_L2T_MEM_READS,
0437     V3D_PERFCNT_PTB_MEM_READS,
0438     V3D_PERFCNT_PSE_MEM_READS,
0439     V3D_PERFCNT_TLB_MEM_READS,
0440     V3D_PERFCNT_GMP_MEM_READS,
0441     V3D_PERFCNT_PTB_W_MEM_WORDS,
0442     V3D_PERFCNT_TLB_W_MEM_WORDS,
0443     V3D_PERFCNT_PSE_R_MEM_WORDS,
0444     V3D_PERFCNT_TLB_R_MEM_WORDS,
0445     V3D_PERFCNT_TMU_MRU_HITS,
0446     V3D_PERFCNT_COMPUTE_ACTIVE,
0447     V3D_PERFCNT_NUM,
0448 };
0449
0450 #define DRM_V3D_MAX_PERF_COUNTERS                 32
0451
0452 struct drm_v3d_perfmon_create {
0453     __u32 id;
0454     __u32 ncounters;
0455     __u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
0456 };
0457
0458 struct drm_v3d_perfmon_destroy {
0459     __u32 id;
0460 };
0461
0462 /*
0463  * Returns the values of the performance counters tracked by this
0464  * perfmon (as an array of ncounters u64 values).
0465  *
0466  * No implicit synchronization is performed, so the user has to
0467  * guarantee that any jobs using this perfmon have already been
0468  * completed  (probably by blocking on the seqno returned by the
0469  * last exec that used the perfmon).
0470  */
0471 struct drm_v3d_perfmon_get_values {
0472     __u32 id;
0473     __u32 pad;
0474     __u64 values_ptr;
0475 };
0476
0477 #if defined(__cplusplus)
0478 }
0479 #endif
0480
0481 #endif /* _V3D_DRM_H_ */