uapi/drm/i810_drm.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 #ifndef _I810_DRM_H_
0003 #define _I810_DRM_H_
0004
0005 #include "drm.h"
0006
0007 #if defined(__cplusplus)
0008 extern "C" {
0009 #endif
0010
0011 /* WARNING: These defines must be the same as what the Xserver uses.
0012  * if you change them, you must change the defines in the Xserver.
0013  */
0014
0015 #ifndef _I810_DEFINES_
0016 #define _I810_DEFINES_
0017
0018 #define I810_DMA_BUF_ORDER      12
0019 #define I810_DMA_BUF_SZ         (1<<I810_DMA_BUF_ORDER)
0020 #define I810_DMA_BUF_NR         256
0021 #define I810_NR_SAREA_CLIPRECTS     8
0022
0023 /* Each region is a minimum of 64k, and there are at most 64 of them.
0024  */
0025 #define I810_NR_TEX_REGIONS 64
0026 #define I810_LOG_MIN_TEX_REGION_SIZE 16
0027 #endif
0028
0029 #define I810_UPLOAD_TEX0IMAGE  0x1  /* handled clientside */
0030 #define I810_UPLOAD_TEX1IMAGE  0x2  /* handled clientside */
0031 #define I810_UPLOAD_CTX        0x4
0032 #define I810_UPLOAD_BUFFERS    0x8
0033 #define I810_UPLOAD_TEX0       0x10
0034 #define I810_UPLOAD_TEX1       0x20
0035 #define I810_UPLOAD_CLIPRECTS  0x40
0036
0037 /* Indices into buf.Setup where various bits of state are mirrored per
0038  * context and per buffer.  These can be fired at the card as a unit,
0039  * or in a piecewise fashion as required.
0040  */
0041
0042 /* Destbuffer state
0043  *    - backbuffer linear offset and pitch -- invarient in the current dri
0044  *    - zbuffer linear offset and pitch -- also invarient
0045  *    - drawing origin in back and depth buffers.
0046  *
0047  * Keep the depth/back buffer state here to accommodate private buffers
0048  * in the future.
0049  */
0050 #define I810_DESTREG_DI0  0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
0051 #define I810_DESTREG_DI1  1
0052 #define I810_DESTREG_DV0  2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
0053 #define I810_DESTREG_DV1  3
0054 #define I810_DESTREG_DR0  4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */
0055 #define I810_DESTREG_DR1  5
0056 #define I810_DESTREG_DR2  6
0057 #define I810_DESTREG_DR3  7
0058 #define I810_DESTREG_DR4  8
0059 #define I810_DEST_SETUP_SIZE 10
0060
0061 /* Context state
0062  */
0063 #define I810_CTXREG_CF0   0 /* GFX_OP_COLOR_FACTOR */
0064 #define I810_CTXREG_CF1   1
0065 #define I810_CTXREG_ST0   2 /* GFX_OP_STIPPLE */
0066 #define I810_CTXREG_ST1   3
0067 #define I810_CTXREG_VF    4 /* GFX_OP_VERTEX_FMT */
0068 #define I810_CTXREG_MT    5 /* GFX_OP_MAP_TEXELS */
0069 #define I810_CTXREG_MC0   6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
0070 #define I810_CTXREG_MC1   7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
0071 #define I810_CTXREG_MC2   8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
0072 #define I810_CTXREG_MA0   9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
0073 #define I810_CTXREG_MA1   10    /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
0074 #define I810_CTXREG_MA2   11    /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
0075 #define I810_CTXREG_SDM   12    /* GFX_OP_SRC_DEST_MONO */
0076 #define I810_CTXREG_FOG   13    /* GFX_OP_FOG_COLOR */
0077 #define I810_CTXREG_B1    14    /* GFX_OP_BOOL_1 */
0078 #define I810_CTXREG_B2    15    /* GFX_OP_BOOL_2 */
0079 #define I810_CTXREG_LCS   16    /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
0080 #define I810_CTXREG_PV    17    /* GFX_OP_PV_RULE -- Invarient! */
0081 #define I810_CTXREG_ZA    18    /* GFX_OP_ZBIAS_ALPHAFUNC */
0082 #define I810_CTXREG_AA    19    /* GFX_OP_ANTIALIAS */
0083 #define I810_CTX_SETUP_SIZE 20
0084
0085 /* Texture state (per tex unit)
0086  */
0087 #define I810_TEXREG_MI0  0  /* GFX_OP_MAP_INFO (4 dwords) */
0088 #define I810_TEXREG_MI1  1
0089 #define I810_TEXREG_MI2  2
0090 #define I810_TEXREG_MI3  3
0091 #define I810_TEXREG_MF   4  /* GFX_OP_MAP_FILTER */
0092 #define I810_TEXREG_MLC  5  /* GFX_OP_MAP_LOD_CTL */
0093 #define I810_TEXREG_MLL  6  /* GFX_OP_MAP_LOD_LIMITS */
0094 #define I810_TEXREG_MCS  7  /* GFX_OP_MAP_COORD_SETS ??? */
0095 #define I810_TEX_SETUP_SIZE 8
0096
0097 /* Flags for clear ioctl
0098  */
0099 #define I810_FRONT   0x1
0100 #define I810_BACK    0x2
0101 #define I810_DEPTH   0x4
0102
0103 typedef enum _drm_i810_init_func {
0104     I810_INIT_DMA = 0x01,
0105     I810_CLEANUP_DMA = 0x02,
0106     I810_INIT_DMA_1_4 = 0x03
0107 } drm_i810_init_func_t;
0108
0109 /* This is the init structure after v1.2 */
0110 typedef struct _drm_i810_init {
0111     drm_i810_init_func_t func;
0112     unsigned int mmio_offset;
0113     unsigned int buffers_offset;
0114     int sarea_priv_offset;
0115     unsigned int ring_start;
0116     unsigned int ring_end;
0117     unsigned int ring_size;
0118     unsigned int front_offset;
0119     unsigned int back_offset;
0120     unsigned int depth_offset;
0121     unsigned int overlay_offset;
0122     unsigned int overlay_physical;
0123     unsigned int w;
0124     unsigned int h;
0125     unsigned int pitch;
0126     unsigned int pitch_bits;
0127 } drm_i810_init_t;
0128
0129 /* This is the init structure prior to v1.2 */
0130 typedef struct _drm_i810_pre12_init {
0131     drm_i810_init_func_t func;
0132     unsigned int mmio_offset;
0133     unsigned int buffers_offset;
0134     int sarea_priv_offset;
0135     unsigned int ring_start;
0136     unsigned int ring_end;
0137     unsigned int ring_size;
0138     unsigned int front_offset;
0139     unsigned int back_offset;
0140     unsigned int depth_offset;
0141     unsigned int w;
0142     unsigned int h;
0143     unsigned int pitch;
0144     unsigned int pitch_bits;
0145 } drm_i810_pre12_init_t;
0146
0147 /* Warning: If you change the SAREA structure you must change the Xserver
0148  * structure as well */
0149
0150 typedef struct _drm_i810_tex_region {
0151     unsigned char next, prev;   /* indices to form a circular LRU  */
0152     unsigned char in_use;   /* owned by a client, or free? */
0153     int age;        /* tracked by clients to update local LRU's */
0154 } drm_i810_tex_region_t;
0155
0156 typedef struct _drm_i810_sarea {
0157     unsigned int ContextState[I810_CTX_SETUP_SIZE];
0158     unsigned int BufferState[I810_DEST_SETUP_SIZE];
0159     unsigned int TexState[2][I810_TEX_SETUP_SIZE];
0160     unsigned int dirty;
0161
0162     unsigned int nbox;
0163     struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
0164
0165     /* Maintain an LRU of contiguous regions of texture space.  If
0166      * you think you own a region of texture memory, and it has an
0167      * age different to the one you set, then you are mistaken and
0168      * it has been stolen by another client.  If global texAge
0169      * hasn't changed, there is no need to walk the list.
0170      *
0171      * These regions can be used as a proxy for the fine-grained
0172      * texture information of other clients - by maintaining them
0173      * in the same lru which is used to age their own textures,
0174      * clients have an approximate lru for the whole of global
0175      * texture space, and can make informed decisions as to which
0176      * areas to kick out.  There is no need to choose whether to
0177      * kick out your own texture or someone else's - simply eject
0178      * them all in LRU order.
0179      */
0180
0181     drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
0182     /* Last elt is sentinal */
0183     int texAge;     /* last time texture was uploaded */
0184     int last_enqueue;   /* last time a buffer was enqueued */
0185     int last_dispatch;  /* age of the most recently dispatched buffer */
0186     int last_quiescent; /*  */
0187     int ctxOwner;       /* last context to upload state */
0188
0189     int vertex_prim;
0190
0191     int pf_enabled;     /* is pageflipping allowed? */
0192     int pf_active;
0193     int pf_current_page;    /* which buffer is being displayed? */
0194 } drm_i810_sarea_t;
0195
0196 /* WARNING: If you change any of these defines, make sure to change the
0197  * defines in the Xserver file (xf86drmMga.h)
0198  */
0199
0200 /* i810 specific ioctls
0201  * The device specific ioctl range is 0x40 to 0x79.
0202  */
0203 #define DRM_I810_INIT       0x00
0204 #define DRM_I810_VERTEX     0x01
0205 #define DRM_I810_CLEAR      0x02
0206 #define DRM_I810_FLUSH      0x03
0207 #define DRM_I810_GETAGE     0x04
0208 #define DRM_I810_GETBUF     0x05
0209 #define DRM_I810_SWAP       0x06
0210 #define DRM_I810_COPY       0x07
0211 #define DRM_I810_DOCOPY     0x08
0212 #define DRM_I810_OV0INFO    0x09
0213 #define DRM_I810_FSTATUS    0x0a
0214 #define DRM_I810_OV0FLIP    0x0b
0215 #define DRM_I810_MC     0x0c
0216 #define DRM_I810_RSTATUS    0x0d
0217 #define DRM_I810_FLIP       0x0e
0218
0219 #define DRM_IOCTL_I810_INIT     DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
0220 #define DRM_IOCTL_I810_VERTEX       DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
0221 #define DRM_IOCTL_I810_CLEAR        DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
0222 #define DRM_IOCTL_I810_FLUSH        DRM_IO(  DRM_COMMAND_BASE + DRM_I810_FLUSH)
0223 #define DRM_IOCTL_I810_GETAGE       DRM_IO(  DRM_COMMAND_BASE + DRM_I810_GETAGE)
0224 #define DRM_IOCTL_I810_GETBUF       DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
0225 #define DRM_IOCTL_I810_SWAP     DRM_IO(  DRM_COMMAND_BASE + DRM_I810_SWAP)
0226 #define DRM_IOCTL_I810_COPY     DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
0227 #define DRM_IOCTL_I810_DOCOPY       DRM_IO(  DRM_COMMAND_BASE + DRM_I810_DOCOPY)
0228 #define DRM_IOCTL_I810_OV0INFO      DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
0229 #define DRM_IOCTL_I810_FSTATUS      DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
0230 #define DRM_IOCTL_I810_OV0FLIP      DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
0231 #define DRM_IOCTL_I810_MC       DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
0232 #define DRM_IOCTL_I810_RSTATUS      DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
0233 #define DRM_IOCTL_I810_FLIP             DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
0234
0235 typedef struct _drm_i810_clear {
0236     int clear_color;
0237     int clear_depth;
0238     int flags;
0239 } drm_i810_clear_t;
0240
0241 /* These may be placeholders if we have more cliprects than
0242  * I810_NR_SAREA_CLIPRECTS.  In that case, the client sets discard to
0243  * false, indicating that the buffer will be dispatched again with a
0244  * new set of cliprects.
0245  */
0246 typedef struct _drm_i810_vertex {
0247     int idx;        /* buffer index */
0248     int used;       /* nr bytes in use */
0249     int discard;        /* client is finished with the buffer? */
0250 } drm_i810_vertex_t;
0251
0252 typedef struct _drm_i810_copy_t {
0253     int idx;        /* buffer index */
0254     int used;       /* nr bytes in use */
0255     void *address;      /* Address to copy from */
0256 } drm_i810_copy_t;
0257
0258 #define PR_TRIANGLES         (0x0<<18)
0259 #define PR_TRISTRIP_0        (0x1<<18)
0260 #define PR_TRISTRIP_1        (0x2<<18)
0261 #define PR_TRIFAN            (0x3<<18)
0262 #define PR_POLYGON           (0x4<<18)
0263 #define PR_LINES             (0x5<<18)
0264 #define PR_LINESTRIP         (0x6<<18)
0265 #define PR_RECTS             (0x7<<18)
0266 #define PR_MASK              (0x7<<18)
0267
0268 typedef struct drm_i810_dma {
0269     void *virtual;
0270     int request_idx;
0271     int request_size;
0272     int granted;
0273 } drm_i810_dma_t;
0274
0275 typedef struct _drm_i810_overlay_t {
0276     unsigned int offset;    /* Address of the Overlay Regs */
0277     unsigned int physical;
0278 } drm_i810_overlay_t;
0279
0280 typedef struct _drm_i810_mc {
0281     int idx;        /* buffer index */
0282     int used;       /* nr bytes in use */
0283     int num_blocks;     /* number of GFXBlocks */
0284     int *length;        /* List of lengths for GFXBlocks (FUTURE) */
0285     unsigned int last_render;   /* Last Render Request */
0286 } drm_i810_mc_t;
0287
0288 #if defined(__cplusplus)
0289 }
0290 #endif
0291
0292 #endif              /* _I810_DRM_H_ */