uapi/drm/exynos_drm.h

0001 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
0002 /* exynos_drm.h
0003  *
0004  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0005  * Authors:
0006  *  Inki Dae <inki.dae@samsung.com>
0007  *  Joonyoung Shim <jy0922.shim@samsung.com>
0008  *  Seung-Woo Kim <sw0312.kim@samsung.com>
0009  *
0010  * This program is free software; you can redistribute  it and/or modify it
0011  * under  the terms of  the GNU General  Public License as published by the
0012  * Free Software Foundation;  either version 2 of the  License, or (at your
0013  * option) any later version.
0014  */
0015
0016 #ifndef _UAPI_EXYNOS_DRM_H_
0017 #define _UAPI_EXYNOS_DRM_H_
0018
0019 #include "drm.h"
0020
0021 #if defined(__cplusplus)
0022 extern "C" {
0023 #endif
0024
0025 /**
0026  * User-desired buffer creation information structure.
0027  *
0028  * @size: user-desired memory allocation size.
0029  *  - this size value would be page-aligned internally.
0030  * @flags: user request for setting memory type or cache attributes.
0031  * @handle: returned a handle to created gem object.
0032  *  - this handle will be set by gem module of kernel side.
0033  */
0034 struct drm_exynos_gem_create {
0035     __u64 size;
0036     __u32 flags;
0037     __u32 handle;
0038 };
0039
0040 /**
0041  * A structure for getting a fake-offset that can be used with mmap.
0042  *
0043  * @handle: handle of gem object.
0044  * @reserved: just padding to be 64-bit aligned.
0045  * @offset: a fake-offset of gem object.
0046  */
0047 struct drm_exynos_gem_map {
0048     __u32 handle;
0049     __u32 reserved;
0050     __u64 offset;
0051 };
0052
0053 /**
0054  * A structure to gem information.
0055  *
0056  * @handle: a handle to gem object created.
0057  * @flags: flag value including memory type and cache attribute and
0058  *  this value would be set by driver.
0059  * @size: size to memory region allocated by gem and this size would
0060  *  be set by driver.
0061  */
0062 struct drm_exynos_gem_info {
0063     __u32 handle;
0064     __u32 flags;
0065     __u64 size;
0066 };
0067
0068 /**
0069  * A structure for user connection request of virtual display.
0070  *
0071  * @connection: indicate whether doing connection or not by user.
0072  * @extensions: if this value is 1 then the vidi driver would need additional
0073  *  128bytes edid data.
0074  * @edid: the edid data pointer from user side.
0075  */
0076 struct drm_exynos_vidi_connection {
0077     __u32 connection;
0078     __u32 extensions;
0079     __u64 edid;
0080 };
0081
0082 /* memory type definitions. */
0083 enum e_drm_exynos_gem_mem_type {
0084     /* Physically Continuous memory and used as default. */
0085     EXYNOS_BO_CONTIG    = 0 << 0,
0086     /* Physically Non-Continuous memory. */
0087     EXYNOS_BO_NONCONTIG = 1 << 0,
0088     /* non-cachable mapping and used as default. */
0089     EXYNOS_BO_NONCACHABLE   = 0 << 1,
0090     /* cachable mapping. */
0091     EXYNOS_BO_CACHABLE  = 1 << 1,
0092     /* write-combine mapping. */
0093     EXYNOS_BO_WC        = 1 << 2,
0094     EXYNOS_BO_MASK      = EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
0095                     EXYNOS_BO_WC
0096 };
0097
0098 struct drm_exynos_g2d_get_ver {
0099     __u32   major;
0100     __u32   minor;
0101 };
0102
0103 struct drm_exynos_g2d_cmd {
0104     __u32   offset;
0105     __u32   data;
0106 };
0107
0108 enum drm_exynos_g2d_buf_type {
0109     G2D_BUF_USERPTR = 1 << 31,
0110 };
0111
0112 enum drm_exynos_g2d_event_type {
0113     G2D_EVENT_NOT,
0114     G2D_EVENT_NONSTOP,
0115     G2D_EVENT_STOP,     /* not yet */
0116 };
0117
0118 struct drm_exynos_g2d_userptr {
0119     unsigned long userptr;
0120     unsigned long size;
0121 };
0122
0123 struct drm_exynos_g2d_set_cmdlist {
0124     __u64                   cmd;
0125     __u64                   cmd_buf;
0126     __u32                   cmd_nr;
0127     __u32                   cmd_buf_nr;
0128
0129     /* for g2d event */
0130     __u64                   event_type;
0131     __u64                   user_data;
0132 };
0133
0134 struct drm_exynos_g2d_exec {
0135     __u64                   async;
0136 };
0137
0138 /* Exynos DRM IPP v2 API */
0139
0140 /**
0141  * Enumerate available IPP hardware modules.
0142  *
0143  * @count_ipps: size of ipp_id array / number of ipp modules (set by driver)
0144  * @reserved: padding
0145  * @ipp_id_ptr: pointer to ipp_id array or NULL
0146  */
0147 struct drm_exynos_ioctl_ipp_get_res {
0148     __u32 count_ipps;
0149     __u32 reserved;
0150     __u64 ipp_id_ptr;
0151 };
0152
0153 enum drm_exynos_ipp_format_type {
0154     DRM_EXYNOS_IPP_FORMAT_SOURCE        = 0x01,
0155     DRM_EXYNOS_IPP_FORMAT_DESTINATION   = 0x02,
0156 };
0157
0158 struct drm_exynos_ipp_format {
0159     __u32 fourcc;
0160     __u32 type;
0161     __u64 modifier;
0162 };
0163
0164 enum drm_exynos_ipp_capability {
0165     DRM_EXYNOS_IPP_CAP_CROP     = 0x01,
0166     DRM_EXYNOS_IPP_CAP_ROTATE   = 0x02,
0167     DRM_EXYNOS_IPP_CAP_SCALE    = 0x04,
0168     DRM_EXYNOS_IPP_CAP_CONVERT  = 0x08,
0169 };
0170
0171 /**
0172  * Get IPP hardware capabilities and supported image formats.
0173  *
0174  * @ipp_id: id of IPP module to query
0175  * @capabilities: bitmask of drm_exynos_ipp_capability (set by driver)
0176  * @reserved: padding
0177  * @formats_count: size of formats array (in entries) / number of filled
0178  *         formats (set by driver)
0179  * @formats_ptr: pointer to formats array or NULL
0180  */
0181 struct drm_exynos_ioctl_ipp_get_caps {
0182     __u32 ipp_id;
0183     __u32 capabilities;
0184     __u32 reserved;
0185     __u32 formats_count;
0186     __u64 formats_ptr;
0187 };
0188
0189 enum drm_exynos_ipp_limit_type {
0190     /* size (horizontal/vertial) limits, in pixels (min, max, alignment) */
0191     DRM_EXYNOS_IPP_LIMIT_TYPE_SIZE      = 0x0001,
0192     /* scale ratio (horizonta/vertial), 16.16 fixed point (min, max) */
0193     DRM_EXYNOS_IPP_LIMIT_TYPE_SCALE     = 0x0002,
0194
0195     /* image buffer area */
0196     DRM_EXYNOS_IPP_LIMIT_SIZE_BUFFER    = 0x0001 << 16,
0197     /* src/dst rectangle area */
0198     DRM_EXYNOS_IPP_LIMIT_SIZE_AREA      = 0x0002 << 16,
0199     /* src/dst rectangle area when rotation enabled */
0200     DRM_EXYNOS_IPP_LIMIT_SIZE_ROTATED   = 0x0003 << 16,
0201
0202     DRM_EXYNOS_IPP_LIMIT_TYPE_MASK      = 0x000f,
0203     DRM_EXYNOS_IPP_LIMIT_SIZE_MASK      = 0x000f << 16,
0204 };
0205
0206 struct drm_exynos_ipp_limit_val {
0207     __u32 min;
0208     __u32 max;
0209     __u32 align;
0210     __u32 reserved;
0211 };
0212
0213 /**
0214  * IPP module limitation.
0215  *
0216  * @type: limit type (see drm_exynos_ipp_limit_type enum)
0217  * @reserved: padding
0218  * @h: horizontal limits
0219  * @v: vertical limits
0220  */
0221 struct drm_exynos_ipp_limit {
0222     __u32 type;
0223     __u32 reserved;
0224     struct drm_exynos_ipp_limit_val h;
0225     struct drm_exynos_ipp_limit_val v;
0226 };
0227
0228 /**
0229  * Get IPP limits for given image format.
0230  *
0231  * @ipp_id: id of IPP module to query
0232  * @fourcc: image format code (see DRM_FORMAT_* in drm_fourcc.h)
0233  * @modifier: image format modifier (see DRM_FORMAT_MOD_* in drm_fourcc.h)
0234  * @type: source/destination identifier (drm_exynos_ipp_format_flag enum)
0235  * @limits_count: size of limits array (in entries) / number of filled entries
0236  *       (set by driver)
0237  * @limits_ptr: pointer to limits array or NULL
0238  */
0239 struct drm_exynos_ioctl_ipp_get_limits {
0240     __u32 ipp_id;
0241     __u32 fourcc;
0242     __u64 modifier;
0243     __u32 type;
0244     __u32 limits_count;
0245     __u64 limits_ptr;
0246 };
0247
0248 enum drm_exynos_ipp_task_id {
0249     /* buffer described by struct drm_exynos_ipp_task_buffer */
0250     DRM_EXYNOS_IPP_TASK_BUFFER      = 0x0001,
0251     /* rectangle described by struct drm_exynos_ipp_task_rect */
0252     DRM_EXYNOS_IPP_TASK_RECTANGLE       = 0x0002,
0253     /* transformation described by struct drm_exynos_ipp_task_transform */
0254     DRM_EXYNOS_IPP_TASK_TRANSFORM       = 0x0003,
0255     /* alpha configuration described by struct drm_exynos_ipp_task_alpha */
0256     DRM_EXYNOS_IPP_TASK_ALPHA       = 0x0004,
0257
0258     /* source image data (for buffer and rectangle chunks) */
0259     DRM_EXYNOS_IPP_TASK_TYPE_SOURCE     = 0x0001 << 16,
0260     /* destination image data (for buffer and rectangle chunks) */
0261     DRM_EXYNOS_IPP_TASK_TYPE_DESTINATION    = 0x0002 << 16,
0262 };
0263
0264 /**
0265  * Memory buffer with image data.
0266  *
0267  * @id: must be DRM_EXYNOS_IPP_TASK_BUFFER
0268  * other parameters are same as for AddFB2 generic DRM ioctl
0269  */
0270 struct drm_exynos_ipp_task_buffer {
0271     __u32   id;
0272     __u32   fourcc;
0273     __u32   width, height;
0274     __u32   gem_id[4];
0275     __u32   offset[4];
0276     __u32   pitch[4];
0277     __u64   modifier;
0278 };
0279
0280 /**
0281  * Rectangle for processing.
0282  *
0283  * @id: must be DRM_EXYNOS_IPP_TASK_RECTANGLE
0284  * @reserved: padding
0285  * @x,@y: left corner in pixels
0286  * @w,@h: width/height in pixels
0287  */
0288 struct drm_exynos_ipp_task_rect {
0289     __u32   id;
0290     __u32   reserved;
0291     __u32   x;
0292     __u32   y;
0293     __u32   w;
0294     __u32   h;
0295 };
0296
0297 /**
0298  * Image tranformation description.
0299  *
0300  * @id: must be DRM_EXYNOS_IPP_TASK_TRANSFORM
0301  * @rotation: DRM_MODE_ROTATE_* and DRM_MODE_REFLECT_* values
0302  */
0303 struct drm_exynos_ipp_task_transform {
0304     __u32   id;
0305     __u32   rotation;
0306 };
0307
0308 /**
0309  * Image global alpha configuration for formats without alpha values.
0310  *
0311  * @id: must be DRM_EXYNOS_IPP_TASK_ALPHA
0312  * @value: global alpha value (0-255)
0313  */
0314 struct drm_exynos_ipp_task_alpha {
0315     __u32   id;
0316     __u32   value;
0317 };
0318
0319 enum drm_exynos_ipp_flag {
0320     /* generate DRM event after processing */
0321     DRM_EXYNOS_IPP_FLAG_EVENT   = 0x01,
0322     /* dry run, only check task parameters */
0323     DRM_EXYNOS_IPP_FLAG_TEST_ONLY   = 0x02,
0324     /* non-blocking processing */
0325     DRM_EXYNOS_IPP_FLAG_NONBLOCK    = 0x04,
0326 };
0327
0328 #define DRM_EXYNOS_IPP_FLAGS (DRM_EXYNOS_IPP_FLAG_EVENT |\
0329         DRM_EXYNOS_IPP_FLAG_TEST_ONLY | DRM_EXYNOS_IPP_FLAG_NONBLOCK)
0330
0331 /**
0332  * Perform image processing described by array of drm_exynos_ipp_task_*
0333  * structures (parameters array).
0334  *
0335  * @ipp_id: id of IPP module to run the task
0336  * @flags: bitmask of drm_exynos_ipp_flag values
0337  * @reserved: padding
0338  * @params_size: size of parameters array (in bytes)
0339  * @params_ptr: pointer to parameters array or NULL
0340  * @user_data: (optional) data for drm event
0341  */
0342 struct drm_exynos_ioctl_ipp_commit {
0343     __u32 ipp_id;
0344     __u32 flags;
0345     __u32 reserved;
0346     __u32 params_size;
0347     __u64 params_ptr;
0348     __u64 user_data;
0349 };
0350
0351 #define DRM_EXYNOS_GEM_CREATE       0x00
0352 #define DRM_EXYNOS_GEM_MAP      0x01
0353 /* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
0354 #define DRM_EXYNOS_GEM_GET      0x04
0355 #define DRM_EXYNOS_VIDI_CONNECTION  0x07
0356
0357 /* G2D */
0358 #define DRM_EXYNOS_G2D_GET_VER      0x20
0359 #define DRM_EXYNOS_G2D_SET_CMDLIST  0x21
0360 #define DRM_EXYNOS_G2D_EXEC     0x22
0361
0362 /* Reserved 0x30 ~ 0x33 for obsolete Exynos IPP ioctls */
0363 /* IPP - Image Post Processing */
0364 #define DRM_EXYNOS_IPP_GET_RESOURCES    0x40
0365 #define DRM_EXYNOS_IPP_GET_CAPS     0x41
0366 #define DRM_EXYNOS_IPP_GET_LIMITS   0x42
0367 #define DRM_EXYNOS_IPP_COMMIT       0x43
0368
0369 #define DRM_IOCTL_EXYNOS_GEM_CREATE     DRM_IOWR(DRM_COMMAND_BASE + \
0370         DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
0371 #define DRM_IOCTL_EXYNOS_GEM_MAP        DRM_IOWR(DRM_COMMAND_BASE + \
0372         DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
0373 #define DRM_IOCTL_EXYNOS_GEM_GET    DRM_IOWR(DRM_COMMAND_BASE + \
0374         DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
0375
0376 #define DRM_IOCTL_EXYNOS_VIDI_CONNECTION    DRM_IOWR(DRM_COMMAND_BASE + \
0377         DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
0378
0379 #define DRM_IOCTL_EXYNOS_G2D_GET_VER        DRM_IOWR(DRM_COMMAND_BASE + \
0380         DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
0381 #define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST    DRM_IOWR(DRM_COMMAND_BASE + \
0382         DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
0383 #define DRM_IOCTL_EXYNOS_G2D_EXEC       DRM_IOWR(DRM_COMMAND_BASE + \
0384         DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
0385
0386 #define DRM_IOCTL_EXYNOS_IPP_GET_RESOURCES  DRM_IOWR(DRM_COMMAND_BASE + \
0387         DRM_EXYNOS_IPP_GET_RESOURCES, \
0388         struct drm_exynos_ioctl_ipp_get_res)
0389 #define DRM_IOCTL_EXYNOS_IPP_GET_CAPS       DRM_IOWR(DRM_COMMAND_BASE + \
0390         DRM_EXYNOS_IPP_GET_CAPS, struct drm_exynos_ioctl_ipp_get_caps)
0391 #define DRM_IOCTL_EXYNOS_IPP_GET_LIMITS     DRM_IOWR(DRM_COMMAND_BASE + \
0392         DRM_EXYNOS_IPP_GET_LIMITS, \
0393         struct drm_exynos_ioctl_ipp_get_limits)
0394 #define DRM_IOCTL_EXYNOS_IPP_COMMIT     DRM_IOWR(DRM_COMMAND_BASE + \
0395         DRM_EXYNOS_IPP_COMMIT, struct drm_exynos_ioctl_ipp_commit)
0396
0397 /* Exynos specific events */
0398 #define DRM_EXYNOS_G2D_EVENT        0x80000000
0399 #define DRM_EXYNOS_IPP_EVENT        0x80000002
0400
0401 struct drm_exynos_g2d_event {
0402     struct drm_event    base;
0403     __u64           user_data;
0404     __u32           tv_sec;
0405     __u32           tv_usec;
0406     __u32           cmdlist_no;
0407     __u32           reserved;
0408 };
0409
0410 struct drm_exynos_ipp_event {
0411     struct drm_event    base;
0412     __u64           user_data;
0413     __u32           tv_sec;
0414     __u32           tv_usec;
0415     __u32           ipp_id;
0416     __u32           sequence;
0417     __u64           reserved;
0418 };
0419
0420 #if defined(__cplusplus)
0421 }
0422 #endif
0423
0424 #endif /* _UAPI_EXYNOS_DRM_H_ */