uapi/drm/etnaviv_drm.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * Copyright (C) 2015 Etnaviv Project
0004  *
0005  * This program is free software; you can redistribute it and/or modify it
0006  * under the terms of the GNU General Public License version 2 as published by
0007  * the Free Software Foundation.
0008  *
0009  * This program is distributed in the hope that it will be useful, but WITHOUT
0010  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
0011  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
0012  * more details.
0013  *
0014  * You should have received a copy of the GNU General Public License along with
0015  * this program.  If not, see <http://www.gnu.org/licenses/>.
0016  */
0017
0018 #ifndef __ETNAVIV_DRM_H__
0019 #define __ETNAVIV_DRM_H__
0020
0021 #include "drm.h"
0022
0023 #if defined(__cplusplus)
0024 extern "C" {
0025 #endif
0026
0027 /* Please note that modifications to all structs defined here are
0028  * subject to backwards-compatibility constraints:
0029  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
0030  *     user/kernel compatibility
0031  *  2) Keep fields aligned to their size
0032  *  3) Because of how drm_ioctl() works, we can add new fields at
0033  *     the end of an ioctl if some care is taken: drm_ioctl() will
0034  *     zero out the new fields at the tail of the ioctl, so a zero
0035  *     value should have a backwards compatible meaning.  And for
0036  *     output params, userspace won't see the newly added output
0037  *     fields.. so that has to be somehow ok.
0038  */
0039
0040 /* timeouts are specified in clock-monotonic absolute times (to simplify
0041  * restarting interrupted ioctls).  The following struct is logically the
0042  * same as 'struct timespec' but 32/64b ABI safe.
0043  */
0044 struct drm_etnaviv_timespec {
0045     __s64 tv_sec;          /* seconds */
0046     __s64 tv_nsec;         /* nanoseconds */
0047 };
0048
0049 #define ETNAVIV_PARAM_GPU_MODEL                     0x01
0050 #define ETNAVIV_PARAM_GPU_REVISION                  0x02
0051 #define ETNAVIV_PARAM_GPU_FEATURES_0                0x03
0052 #define ETNAVIV_PARAM_GPU_FEATURES_1                0x04
0053 #define ETNAVIV_PARAM_GPU_FEATURES_2                0x05
0054 #define ETNAVIV_PARAM_GPU_FEATURES_3                0x06
0055 #define ETNAVIV_PARAM_GPU_FEATURES_4                0x07
0056 #define ETNAVIV_PARAM_GPU_FEATURES_5                0x08
0057 #define ETNAVIV_PARAM_GPU_FEATURES_6                0x09
0058 #define ETNAVIV_PARAM_GPU_FEATURES_7                0x0a
0059 #define ETNAVIV_PARAM_GPU_FEATURES_8                0x0b
0060 #define ETNAVIV_PARAM_GPU_FEATURES_9                0x0c
0061 #define ETNAVIV_PARAM_GPU_FEATURES_10               0x0d
0062 #define ETNAVIV_PARAM_GPU_FEATURES_11               0x0e
0063 #define ETNAVIV_PARAM_GPU_FEATURES_12               0x0f
0064
0065 #define ETNAVIV_PARAM_GPU_STREAM_COUNT              0x10
0066 #define ETNAVIV_PARAM_GPU_REGISTER_MAX              0x11
0067 #define ETNAVIV_PARAM_GPU_THREAD_COUNT              0x12
0068 #define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE         0x13
0069 #define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT         0x14
0070 #define ETNAVIV_PARAM_GPU_PIXEL_PIPES               0x15
0071 #define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
0072 #define ETNAVIV_PARAM_GPU_BUFFER_SIZE               0x17
0073 #define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT         0x18
0074 #define ETNAVIV_PARAM_GPU_NUM_CONSTANTS             0x19
0075 #define ETNAVIV_PARAM_GPU_NUM_VARYINGS              0x1a
0076 #define ETNAVIV_PARAM_SOFTPIN_START_ADDR            0x1b
0077 #define ETNAVIV_PARAM_GPU_PRODUCT_ID                0x1c
0078 #define ETNAVIV_PARAM_GPU_CUSTOMER_ID               0x1d
0079 #define ETNAVIV_PARAM_GPU_ECO_ID                    0x1e
0080
0081 #define ETNA_MAX_PIPES 4
0082
0083 struct drm_etnaviv_param {
0084     __u32 pipe;           /* in */
0085     __u32 param;          /* in, ETNAVIV_PARAM_x */
0086     __u64 value;          /* out (get_param) or in (set_param) */
0087 };
0088
0089 /*
0090  * GEM buffers:
0091  */
0092
0093 #define ETNA_BO_CACHE_MASK   0x000f0000
0094 /* cache modes */
0095 #define ETNA_BO_CACHED       0x00010000
0096 #define ETNA_BO_WC           0x00020000
0097 #define ETNA_BO_UNCACHED     0x00040000
0098 /* map flags */
0099 #define ETNA_BO_FORCE_MMU    0x00100000
0100
0101 struct drm_etnaviv_gem_new {
0102     __u64 size;           /* in */
0103     __u32 flags;          /* in, mask of ETNA_BO_x */
0104     __u32 handle;         /* out */
0105 };
0106
0107 struct drm_etnaviv_gem_info {
0108     __u32 handle;         /* in */
0109     __u32 pad;
0110     __u64 offset;         /* out, offset to pass to mmap() */
0111 };
0112
0113 #define ETNA_PREP_READ        0x01
0114 #define ETNA_PREP_WRITE       0x02
0115 #define ETNA_PREP_NOSYNC      0x04
0116
0117 struct drm_etnaviv_gem_cpu_prep {
0118     __u32 handle;         /* in */
0119     __u32 op;             /* in, mask of ETNA_PREP_x */
0120     struct drm_etnaviv_timespec timeout;   /* in */
0121 };
0122
0123 struct drm_etnaviv_gem_cpu_fini {
0124     __u32 handle;         /* in */
0125     __u32 flags;          /* in, placeholder for now, no defined values */
0126 };
0127
0128 /*
0129  * Cmdstream Submission:
0130  */
0131
0132 /* The value written into the cmdstream is logically:
0133  * relocbuf->gpuaddr + reloc_offset
0134  *
0135  * NOTE that reloc's must be sorted by order of increasing submit_offset,
0136  * otherwise EINVAL.
0137  */
0138 struct drm_etnaviv_gem_submit_reloc {
0139     __u32 submit_offset;  /* in, offset from submit_bo */
0140     __u32 reloc_idx;      /* in, index of reloc_bo buffer */
0141     __u64 reloc_offset;   /* in, offset from start of reloc_bo */
0142     __u32 flags;          /* in, placeholder for now, no defined values */
0143 };
0144
0145 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
0146  * cmdstream buffer(s) themselves or reloc entries) has one (and only
0147  * one) entry in the submit->bos[] table.
0148  *
0149  * As a optimization, the current buffer (gpu virtual address) can be
0150  * passed back through the 'presumed' field.  If on a subsequent reloc,
0151  * userspace passes back a 'presumed' address that is still valid,
0152  * then patching the cmdstream for this entry is skipped.  This can
0153  * avoid kernel needing to map/access the cmdstream bo in the common
0154  * case.
0155  * If the submit is a softpin submit (ETNA_SUBMIT_SOFTPIN) the 'presumed'
0156  * field is interpreted as the fixed location to map the bo into the gpu
0157  * virtual address space. If the kernel is unable to map the buffer at
0158  * this location the submit will fail. This means userspace is responsible
0159  * for the whole gpu virtual address management.
0160  */
0161 #define ETNA_SUBMIT_BO_READ             0x0001
0162 #define ETNA_SUBMIT_BO_WRITE            0x0002
0163 struct drm_etnaviv_gem_submit_bo {
0164     __u32 flags;          /* in, mask of ETNA_SUBMIT_BO_x */
0165     __u32 handle;         /* in, GEM handle */
0166     __u64 presumed;       /* in/out, presumed buffer address */
0167 };
0168
0169 /* performance monitor request (pmr) */
0170 #define ETNA_PM_PROCESS_PRE             0x0001
0171 #define ETNA_PM_PROCESS_POST            0x0002
0172 struct drm_etnaviv_gem_submit_pmr {
0173     __u32 flags;          /* in, when to process request (ETNA_PM_PROCESS_x) */
0174     __u8  domain;         /* in, pm domain */
0175     __u8  pad;
0176     __u16 signal;         /* in, pm signal */
0177     __u32 sequence;       /* in, sequence number */
0178     __u32 read_offset;    /* in, offset from read_bo */
0179     __u32 read_idx;       /* in, index of read_bo buffer */
0180 };
0181
0182 /* Each cmdstream submit consists of a table of buffers involved, and
0183  * one or more cmdstream buffers.  This allows for conditional execution
0184  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
0185  */
0186 #define ETNA_SUBMIT_NO_IMPLICIT         0x0001
0187 #define ETNA_SUBMIT_FENCE_FD_IN         0x0002
0188 #define ETNA_SUBMIT_FENCE_FD_OUT        0x0004
0189 #define ETNA_SUBMIT_SOFTPIN             0x0008
0190 #define ETNA_SUBMIT_FLAGS       (ETNA_SUBMIT_NO_IMPLICIT | \
0191                      ETNA_SUBMIT_FENCE_FD_IN | \
0192                      ETNA_SUBMIT_FENCE_FD_OUT| \
0193                      ETNA_SUBMIT_SOFTPIN)
0194 #define ETNA_PIPE_3D      0x00
0195 #define ETNA_PIPE_2D      0x01
0196 #define ETNA_PIPE_VG      0x02
0197 struct drm_etnaviv_gem_submit {
0198     __u32 fence;          /* out */
0199     __u32 pipe;           /* in */
0200     __u32 exec_state;     /* in, initial execution state (ETNA_PIPE_x) */
0201     __u32 nr_bos;         /* in, number of submit_bo's */
0202     __u32 nr_relocs;      /* in, number of submit_reloc's */
0203     __u32 stream_size;    /* in, cmdstream size */
0204     __u64 bos;            /* in, ptr to array of submit_bo's */
0205     __u64 relocs;         /* in, ptr to array of submit_reloc's */
0206     __u64 stream;         /* in, ptr to cmdstream */
0207     __u32 flags;          /* in, mask of ETNA_SUBMIT_x */
0208     __s32 fence_fd;       /* in/out, fence fd (see ETNA_SUBMIT_FENCE_FD_x) */
0209     __u64 pmrs;           /* in, ptr to array of submit_pmr's */
0210     __u32 nr_pmrs;        /* in, number of submit_pmr's */
0211     __u32 pad;
0212 };
0213
0214 /* The normal way to synchronize with the GPU is just to CPU_PREP on
0215  * a buffer if you need to access it from the CPU (other cmdstream
0216  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
0217  * handle the required synchronization under the hood).  This ioctl
0218  * mainly just exists as a way to implement the gallium pipe_fence
0219  * APIs without requiring a dummy bo to synchronize on.
0220  */
0221 #define ETNA_WAIT_NONBLOCK      0x01
0222 struct drm_etnaviv_wait_fence {
0223     __u32 pipe;           /* in */
0224     __u32 fence;          /* in */
0225     __u32 flags;          /* in, mask of ETNA_WAIT_x */
0226     __u32 pad;
0227     struct drm_etnaviv_timespec timeout;   /* in */
0228 };
0229
0230 #define ETNA_USERPTR_READ   0x01
0231 #define ETNA_USERPTR_WRITE  0x02
0232 struct drm_etnaviv_gem_userptr {
0233     __u64 user_ptr; /* in, page aligned user pointer */
0234     __u64 user_size;    /* in, page aligned user size */
0235     __u32 flags;        /* in, flags */
0236     __u32 handle;   /* out, non-zero handle */
0237 };
0238
0239 struct drm_etnaviv_gem_wait {
0240     __u32 pipe;             /* in */
0241     __u32 handle;               /* in, bo to be waited for */
0242     __u32 flags;                /* in, mask of ETNA_WAIT_x  */
0243     __u32 pad;
0244     struct drm_etnaviv_timespec timeout;    /* in */
0245 };
0246
0247 /*
0248  * Performance Monitor (PM):
0249  */
0250
0251 struct drm_etnaviv_pm_domain {
0252     __u32 pipe;       /* in */
0253     __u8  iter;       /* in/out, select pm domain at index iter */
0254     __u8  id;         /* out, id of domain */
0255     __u16 nr_signals; /* out, how many signals does this domain provide */
0256     char  name[64];   /* out, name of domain */
0257 };
0258
0259 struct drm_etnaviv_pm_signal {
0260     __u32 pipe;       /* in */
0261     __u8  domain;     /* in, pm domain index */
0262     __u8  pad;
0263     __u16 iter;       /* in/out, select pm source at index iter */
0264     __u16 id;         /* out, id of signal */
0265     char  name[64];   /* out, name of domain */
0266 };
0267
0268 #define DRM_ETNAVIV_GET_PARAM          0x00
0269 /* placeholder:
0270 #define DRM_ETNAVIV_SET_PARAM          0x01
0271  */
0272 #define DRM_ETNAVIV_GEM_NEW            0x02
0273 #define DRM_ETNAVIV_GEM_INFO           0x03
0274 #define DRM_ETNAVIV_GEM_CPU_PREP       0x04
0275 #define DRM_ETNAVIV_GEM_CPU_FINI       0x05
0276 #define DRM_ETNAVIV_GEM_SUBMIT         0x06
0277 #define DRM_ETNAVIV_WAIT_FENCE         0x07
0278 #define DRM_ETNAVIV_GEM_USERPTR        0x08
0279 #define DRM_ETNAVIV_GEM_WAIT           0x09
0280 #define DRM_ETNAVIV_PM_QUERY_DOM       0x0a
0281 #define DRM_ETNAVIV_PM_QUERY_SIG       0x0b
0282 #define DRM_ETNAVIV_NUM_IOCTLS         0x0c
0283
0284 #define DRM_IOCTL_ETNAVIV_GET_PARAM    DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
0285 #define DRM_IOCTL_ETNAVIV_GEM_NEW      DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
0286 #define DRM_IOCTL_ETNAVIV_GEM_INFO     DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
0287 #define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
0288 #define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
0289 #define DRM_IOCTL_ETNAVIV_GEM_SUBMIT   DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
0290 #define DRM_IOCTL_ETNAVIV_WAIT_FENCE   DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
0291 #define DRM_IOCTL_ETNAVIV_GEM_USERPTR  DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
0292 #define DRM_IOCTL_ETNAVIV_GEM_WAIT     DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
0293 #define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
0294 #define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
0295
0296 #if defined(__cplusplus)
0297 }
0298 #endif
0299
0300 #endif /* __ETNAVIV_DRM_H__ */