uapi/drm/drm.h

0001 /*
0002  * Header for the Direct Rendering Manager
0003  *
0004  * Author: Rickard E. (Rik) Faith <faith@valinux.com>
0005  *
0006  * Acknowledgments:
0007  * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic cmpxchg.
0008  */
0009
0010 /*
0011  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
0012  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
0013  * All rights reserved.
0014  *
0015  * Permission is hereby granted, free of charge, to any person obtaining a
0016  * copy of this software and associated documentation files (the "Software"),
0017  * to deal in the Software without restriction, including without limitation
0018  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0019  * and/or sell copies of the Software, and to permit persons to whom the
0020  * Software is furnished to do so, subject to the following conditions:
0021  *
0022  * The above copyright notice and this permission notice (including the next
0023  * paragraph) shall be included in all copies or substantial portions of the
0024  * Software.
0025  *
0026  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0027  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0028  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0029  * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
0030  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
0031  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
0032  * OTHER DEALINGS IN THE SOFTWARE.
0033  */
0034
0035 #ifndef _DRM_H_
0036 #define _DRM_H_
0037
0038 #if defined(__KERNEL__)
0039
0040 #include <linux/types.h>
0041 #include <asm/ioctl.h>
0042 typedef unsigned int drm_handle_t;
0043
0044 #elif defined(__linux__)
0045
0046 #include <linux/types.h>
0047 #include <asm/ioctl.h>
0048 typedef unsigned int drm_handle_t;
0049
0050 #else /* One of the BSDs */
0051
0052 #include <stdint.h>
0053 #include <sys/ioccom.h>
0054 #include <sys/types.h>
0055 typedef int8_t   __s8;
0056 typedef uint8_t  __u8;
0057 typedef int16_t  __s16;
0058 typedef uint16_t __u16;
0059 typedef int32_t  __s32;
0060 typedef uint32_t __u32;
0061 typedef int64_t  __s64;
0062 typedef uint64_t __u64;
0063 typedef size_t   __kernel_size_t;
0064 typedef unsigned long drm_handle_t;
0065
0066 #endif
0067
0068 #if defined(__cplusplus)
0069 extern "C" {
0070 #endif
0071
0072 #define DRM_NAME    "drm"     /**< Name in kernel, /dev, and /proc */
0073 #define DRM_MIN_ORDER   5     /**< At least 2^5 bytes = 32 bytes */
0074 #define DRM_MAX_ORDER   22    /**< Up to 2^22 bytes = 4MB */
0075 #define DRM_RAM_PERCENT 10    /**< How much system ram can we lock? */
0076
0077 #define _DRM_LOCK_HELD  0x80000000U /**< Hardware lock is held */
0078 #define _DRM_LOCK_CONT  0x40000000U /**< Hardware lock is contended */
0079 #define _DRM_LOCK_IS_HELD(lock)    ((lock) & _DRM_LOCK_HELD)
0080 #define _DRM_LOCK_IS_CONT(lock)    ((lock) & _DRM_LOCK_CONT)
0081 #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
0082
0083 typedef unsigned int drm_context_t;
0084 typedef unsigned int drm_drawable_t;
0085 typedef unsigned int drm_magic_t;
0086
0087 /*
0088  * Cliprect.
0089  *
0090  * \warning: If you change this structure, make sure you change
0091  * XF86DRIClipRectRec in the server as well
0092  *
0093  * \note KW: Actually it's illegal to change either for
0094  * backwards-compatibility reasons.
0095  */
0096 struct drm_clip_rect {
0097     unsigned short x1;
0098     unsigned short y1;
0099     unsigned short x2;
0100     unsigned short y2;
0101 };
0102
0103 /*
0104  * Drawable information.
0105  */
0106 struct drm_drawable_info {
0107     unsigned int num_rects;
0108     struct drm_clip_rect *rects;
0109 };
0110
0111 /*
0112  * Texture region,
0113  */
0114 struct drm_tex_region {
0115     unsigned char next;
0116     unsigned char prev;
0117     unsigned char in_use;
0118     unsigned char padding;
0119     unsigned int age;
0120 };
0121
0122 /*
0123  * Hardware lock.
0124  *
0125  * The lock structure is a simple cache-line aligned integer.  To avoid
0126  * processor bus contention on a multiprocessor system, there should not be any
0127  * other data stored in the same cache line.
0128  */
0129 struct drm_hw_lock {
0130     __volatile__ unsigned int lock;     /**< lock variable */
0131     char padding[60];           /**< Pad to cache line */
0132 };
0133
0134 /*
0135  * DRM_IOCTL_VERSION ioctl argument type.
0136  *
0137  * \sa drmGetVersion().
0138  */
0139 struct drm_version {
0140     int version_major;    /**< Major version */
0141     int version_minor;    /**< Minor version */
0142     int version_patchlevel;   /**< Patch level */
0143     __kernel_size_t name_len;     /**< Length of name buffer */
0144     char __user *name;    /**< Name of driver */
0145     __kernel_size_t date_len;     /**< Length of date buffer */
0146     char __user *date;    /**< User-space buffer to hold date */
0147     __kernel_size_t desc_len;     /**< Length of desc buffer */
0148     char __user *desc;    /**< User-space buffer to hold desc */
0149 };
0150
0151 /*
0152  * DRM_IOCTL_GET_UNIQUE ioctl argument type.
0153  *
0154  * \sa drmGetBusid() and drmSetBusId().
0155  */
0156 struct drm_unique {
0157     __kernel_size_t unique_len;   /**< Length of unique */
0158     char __user *unique;      /**< Unique name for driver instantiation */
0159 };
0160
0161 struct drm_list {
0162     int count;        /**< Length of user-space structures */
0163     struct drm_version __user *version;
0164 };
0165
0166 struct drm_block {
0167     int unused;
0168 };
0169
0170 /*
0171  * DRM_IOCTL_CONTROL ioctl argument type.
0172  *
0173  * \sa drmCtlInstHandler() and drmCtlUninstHandler().
0174  */
0175 struct drm_control {
0176     enum {
0177         DRM_ADD_COMMAND,
0178         DRM_RM_COMMAND,
0179         DRM_INST_HANDLER,
0180         DRM_UNINST_HANDLER
0181     } func;
0182     int irq;
0183 };
0184
0185 /*
0186  * Type of memory to map.
0187  */
0188 enum drm_map_type {
0189     _DRM_FRAME_BUFFER = 0,    /**< WC (no caching), no core dump */
0190     _DRM_REGISTERS = 1,   /**< no caching, no core dump */
0191     _DRM_SHM = 2,         /**< shared, cached */
0192     _DRM_AGP = 3,         /**< AGP/GART */
0193     _DRM_SCATTER_GATHER = 4,  /**< Scatter/gather memory for PCI DMA */
0194     _DRM_CONSISTENT = 5   /**< Consistent memory for PCI DMA */
0195 };
0196
0197 /*
0198  * Memory mapping flags.
0199  */
0200 enum drm_map_flags {
0201     _DRM_RESTRICTED = 0x01,      /**< Cannot be mapped to user-virtual */
0202     _DRM_READ_ONLY = 0x02,
0203     _DRM_LOCKED = 0x04,      /**< shared, cached, locked */
0204     _DRM_KERNEL = 0x08,      /**< kernel requires access */
0205     _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
0206     _DRM_CONTAINS_LOCK = 0x20,   /**< SHM page that contains lock */
0207     _DRM_REMOVABLE = 0x40,       /**< Removable mapping */
0208     _DRM_DRIVER = 0x80       /**< Managed by driver */
0209 };
0210
0211 struct drm_ctx_priv_map {
0212     unsigned int ctx_id;     /**< Context requesting private mapping */
0213     void *handle;        /**< Handle of map */
0214 };
0215
0216 /*
0217  * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
0218  * argument type.
0219  *
0220  * \sa drmAddMap().
0221  */
0222 struct drm_map {
0223     unsigned long offset;    /**< Requested physical address (0 for SAREA)*/
0224     unsigned long size;  /**< Requested physical size (bytes) */
0225     enum drm_map_type type;  /**< Type of memory to map */
0226     enum drm_map_flags flags;    /**< Flags */
0227     void *handle;        /**< User-space: "Handle" to pass to mmap() */
0228                  /**< Kernel-space: kernel-virtual address */
0229     int mtrr;        /**< MTRR slot used */
0230     /*   Private data */
0231 };
0232
0233 /*
0234  * DRM_IOCTL_GET_CLIENT ioctl argument type.
0235  */
0236 struct drm_client {
0237     int idx;        /**< Which client desired? */
0238     int auth;       /**< Is client authenticated? */
0239     unsigned long pid;  /**< Process ID */
0240     unsigned long uid;  /**< User ID */
0241     unsigned long magic;    /**< Magic */
0242     unsigned long iocs; /**< Ioctl count */
0243 };
0244
0245 enum drm_stat_type {
0246     _DRM_STAT_LOCK,
0247     _DRM_STAT_OPENS,
0248     _DRM_STAT_CLOSES,
0249     _DRM_STAT_IOCTLS,
0250     _DRM_STAT_LOCKS,
0251     _DRM_STAT_UNLOCKS,
0252     _DRM_STAT_VALUE,    /**< Generic value */
0253     _DRM_STAT_BYTE,     /**< Generic byte counter (1024bytes/K) */
0254     _DRM_STAT_COUNT,    /**< Generic non-byte counter (1000/k) */
0255
0256     _DRM_STAT_IRQ,      /**< IRQ */
0257     _DRM_STAT_PRIMARY,  /**< Primary DMA bytes */
0258     _DRM_STAT_SECONDARY,    /**< Secondary DMA bytes */
0259     _DRM_STAT_DMA,      /**< DMA */
0260     _DRM_STAT_SPECIAL,  /**< Special DMA (e.g., priority or polled) */
0261     _DRM_STAT_MISSED    /**< Missed DMA opportunity */
0262         /* Add to the *END* of the list */
0263 };
0264
0265 /*
0266  * DRM_IOCTL_GET_STATS ioctl argument type.
0267  */
0268 struct drm_stats {
0269     unsigned long count;
0270     struct {
0271         unsigned long value;
0272         enum drm_stat_type type;
0273     } data[15];
0274 };
0275
0276 /*
0277  * Hardware locking flags.
0278  */
0279 enum drm_lock_flags {
0280     _DRM_LOCK_READY = 0x01,      /**< Wait until hardware is ready for DMA */
0281     _DRM_LOCK_QUIESCENT = 0x02,  /**< Wait until hardware quiescent */
0282     _DRM_LOCK_FLUSH = 0x04,      /**< Flush this context's DMA queue first */
0283     _DRM_LOCK_FLUSH_ALL = 0x08,  /**< Flush all DMA queues first */
0284     /* These *HALT* flags aren't supported yet
0285        -- they will be used to support the
0286        full-screen DGA-like mode. */
0287     _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
0288     _DRM_HALT_CUR_QUEUES = 0x20  /**< Halt all current queues */
0289 };
0290
0291 /*
0292  * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
0293  *
0294  * \sa drmGetLock() and drmUnlock().
0295  */
0296 struct drm_lock {
0297     int context;
0298     enum drm_lock_flags flags;
0299 };
0300
0301 /*
0302  * DMA flags
0303  *
0304  * \warning
0305  * These values \e must match xf86drm.h.
0306  *
0307  * \sa drm_dma.
0308  */
0309 enum drm_dma_flags {
0310     /* Flags for DMA buffer dispatch */
0311     _DRM_DMA_BLOCK = 0x01,        /**<
0312                        * Block until buffer dispatched.
0313                        *
0314                        * \note The buffer may not yet have
0315                        * been processed by the hardware --
0316                        * getting a hardware lock with the
0317                        * hardware quiescent will ensure
0318                        * that the buffer has been
0319                        * processed.
0320                        */
0321     _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
0322     _DRM_DMA_PRIORITY = 0x04,     /**< High priority dispatch */
0323
0324     /* Flags for DMA buffer request */
0325     _DRM_DMA_WAIT = 0x10,         /**< Wait for free buffers */
0326     _DRM_DMA_SMALLER_OK = 0x20,   /**< Smaller-than-requested buffers OK */
0327     _DRM_DMA_LARGER_OK = 0x40     /**< Larger-than-requested buffers OK */
0328 };
0329
0330 /*
0331  * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
0332  *
0333  * \sa drmAddBufs().
0334  */
0335 struct drm_buf_desc {
0336     int count;       /**< Number of buffers of this size */
0337     int size;        /**< Size in bytes */
0338     int low_mark;        /**< Low water mark */
0339     int high_mark;       /**< High water mark */
0340     enum {
0341         _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
0342         _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
0343         _DRM_SG_BUFFER = 0x04,  /**< Scatter/gather memory buffer */
0344         _DRM_FB_BUFFER = 0x08,  /**< Buffer is in frame buffer */
0345         _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
0346     } flags;
0347     unsigned long agp_start; /**<
0348                   * Start address of where the AGP buffers are
0349                   * in the AGP aperture
0350                   */
0351 };
0352
0353 /*
0354  * DRM_IOCTL_INFO_BUFS ioctl argument type.
0355  */
0356 struct drm_buf_info {
0357     int count;      /**< Entries in list */
0358     struct drm_buf_desc __user *list;
0359 };
0360
0361 /*
0362  * DRM_IOCTL_FREE_BUFS ioctl argument type.
0363  */
0364 struct drm_buf_free {
0365     int count;
0366     int __user *list;
0367 };
0368
0369 /*
0370  * Buffer information
0371  *
0372  * \sa drm_buf_map.
0373  */
0374 struct drm_buf_pub {
0375     int idx;               /**< Index into the master buffer list */
0376     int total;             /**< Buffer size */
0377     int used;              /**< Amount of buffer in use (for DMA) */
0378     void __user *address;          /**< Address of buffer */
0379 };
0380
0381 /*
0382  * DRM_IOCTL_MAP_BUFS ioctl argument type.
0383  */
0384 struct drm_buf_map {
0385     int count;      /**< Length of the buffer list */
0386 #ifdef __cplusplus
0387     void __user *virt;
0388 #else
0389     void __user *virtual;       /**< Mmap'd area in user-virtual */
0390 #endif
0391     struct drm_buf_pub __user *list;    /**< Buffer information */
0392 };
0393
0394 /*
0395  * DRM_IOCTL_DMA ioctl argument type.
0396  *
0397  * Indices here refer to the offset into the buffer list in drm_buf_get.
0398  *
0399  * \sa drmDMA().
0400  */
0401 struct drm_dma {
0402     int context;              /**< Context handle */
0403     int send_count;           /**< Number of buffers to send */
0404     int __user *send_indices;     /**< List of handles to buffers */
0405     int __user *send_sizes;       /**< Lengths of data to send */
0406     enum drm_dma_flags flags;     /**< Flags */
0407     int request_count;        /**< Number of buffers requested */
0408     int request_size;         /**< Desired size for buffers */
0409     int __user *request_indices;      /**< Buffer information */
0410     int __user *request_sizes;
0411     int granted_count;        /**< Number of buffers granted */
0412 };
0413
0414 enum drm_ctx_flags {
0415     _DRM_CONTEXT_PRESERVED = 0x01,
0416     _DRM_CONTEXT_2DONLY = 0x02
0417 };
0418
0419 /*
0420  * DRM_IOCTL_ADD_CTX ioctl argument type.
0421  *
0422  * \sa drmCreateContext() and drmDestroyContext().
0423  */
0424 struct drm_ctx {
0425     drm_context_t handle;
0426     enum drm_ctx_flags flags;
0427 };
0428
0429 /*
0430  * DRM_IOCTL_RES_CTX ioctl argument type.
0431  */
0432 struct drm_ctx_res {
0433     int count;
0434     struct drm_ctx __user *contexts;
0435 };
0436
0437 /*
0438  * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
0439  */
0440 struct drm_draw {
0441     drm_drawable_t handle;
0442 };
0443
0444 /*
0445  * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
0446  */
0447 typedef enum {
0448     DRM_DRAWABLE_CLIPRECTS
0449 } drm_drawable_info_type_t;
0450
0451 struct drm_update_draw {
0452     drm_drawable_t handle;
0453     unsigned int type;
0454     unsigned int num;
0455     unsigned long long data;
0456 };
0457
0458 /*
0459  * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
0460  */
0461 struct drm_auth {
0462     drm_magic_t magic;
0463 };
0464
0465 /*
0466  * DRM_IOCTL_IRQ_BUSID ioctl argument type.
0467  *
0468  * \sa drmGetInterruptFromBusID().
0469  */
0470 struct drm_irq_busid {
0471     int irq;    /**< IRQ number */
0472     int busnum; /**< bus number */
0473     int devnum; /**< device number */
0474     int funcnum;    /**< function number */
0475 };
0476
0477 enum drm_vblank_seq_type {
0478     _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
0479     _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
0480     /* bits 1-6 are reserved for high crtcs */
0481     _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
0482     _DRM_VBLANK_EVENT = 0x4000000,   /**< Send event instead of blocking */
0483     _DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
0484     _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
0485     _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
0486     _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */
0487 };
0488 #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
0489
0490 #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
0491 #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \
0492                 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)
0493
0494 struct drm_wait_vblank_request {
0495     enum drm_vblank_seq_type type;
0496     unsigned int sequence;
0497     unsigned long signal;
0498 };
0499
0500 struct drm_wait_vblank_reply {
0501     enum drm_vblank_seq_type type;
0502     unsigned int sequence;
0503     long tval_sec;
0504     long tval_usec;
0505 };
0506
0507 /*
0508  * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
0509  *
0510  * \sa drmWaitVBlank().
0511  */
0512 union drm_wait_vblank {
0513     struct drm_wait_vblank_request request;
0514     struct drm_wait_vblank_reply reply;
0515 };
0516
0517 #define _DRM_PRE_MODESET 1
0518 #define _DRM_POST_MODESET 2
0519
0520 /*
0521  * DRM_IOCTL_MODESET_CTL ioctl argument type
0522  *
0523  * \sa drmModesetCtl().
0524  */
0525 struct drm_modeset_ctl {
0526     __u32 crtc;
0527     __u32 cmd;
0528 };
0529
0530 /*
0531  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
0532  *
0533  * \sa drmAgpEnable().
0534  */
0535 struct drm_agp_mode {
0536     unsigned long mode; /**< AGP mode */
0537 };
0538
0539 /*
0540  * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
0541  *
0542  * \sa drmAgpAlloc() and drmAgpFree().
0543  */
0544 struct drm_agp_buffer {
0545     unsigned long size; /**< In bytes -- will round to page boundary */
0546     unsigned long handle;   /**< Used for binding / unbinding */
0547     unsigned long type; /**< Type of memory to allocate */
0548     unsigned long physical; /**< Physical used by i810 */
0549 };
0550
0551 /*
0552  * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
0553  *
0554  * \sa drmAgpBind() and drmAgpUnbind().
0555  */
0556 struct drm_agp_binding {
0557     unsigned long handle;   /**< From drm_agp_buffer */
0558     unsigned long offset;   /**< In bytes -- will round to page boundary */
0559 };
0560
0561 /*
0562  * DRM_IOCTL_AGP_INFO ioctl argument type.
0563  *
0564  * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
0565  * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
0566  * drmAgpVendorId() and drmAgpDeviceId().
0567  */
0568 struct drm_agp_info {
0569     int agp_version_major;
0570     int agp_version_minor;
0571     unsigned long mode;
0572     unsigned long aperture_base;    /* physical address */
0573     unsigned long aperture_size;    /* bytes */
0574     unsigned long memory_allowed;   /* bytes */
0575     unsigned long memory_used;
0576
0577     /* PCI information */
0578     unsigned short id_vendor;
0579     unsigned short id_device;
0580 };
0581
0582 /*
0583  * DRM_IOCTL_SG_ALLOC ioctl argument type.
0584  */
0585 struct drm_scatter_gather {
0586     unsigned long size; /**< In bytes -- will round to page boundary */
0587     unsigned long handle;   /**< Used for mapping / unmapping */
0588 };
0589
0590 /*
0591  * DRM_IOCTL_SET_VERSION ioctl argument type.
0592  */
0593 struct drm_set_version {
0594     int drm_di_major;
0595     int drm_di_minor;
0596     int drm_dd_major;
0597     int drm_dd_minor;
0598 };
0599
0600 /* DRM_IOCTL_GEM_CLOSE ioctl argument type */
0601 struct drm_gem_close {
0602     /** Handle of the object to be closed. */
0603     __u32 handle;
0604     __u32 pad;
0605 };
0606
0607 /* DRM_IOCTL_GEM_FLINK ioctl argument type */
0608 struct drm_gem_flink {
0609     /** Handle for the object being named */
0610     __u32 handle;
0611
0612     /** Returned global name */
0613     __u32 name;
0614 };
0615
0616 /* DRM_IOCTL_GEM_OPEN ioctl argument type */
0617 struct drm_gem_open {
0618     /** Name of object being opened */
0619     __u32 name;
0620
0621     /** Returned handle for the object */
0622     __u32 handle;
0623
0624     /** Returned size of the object */
0625     __u64 size;
0626 };
0627
0628 /**
0629  * DRM_CAP_DUMB_BUFFER
0630  *
0631  * If set to 1, the driver supports creating dumb buffers via the
0632  * &DRM_IOCTL_MODE_CREATE_DUMB ioctl.
0633  */
0634 #define DRM_CAP_DUMB_BUFFER     0x1
0635 /**
0636  * DRM_CAP_VBLANK_HIGH_CRTC
0637  *
0638  * If set to 1, the kernel supports specifying a :ref:`CRTC index<crtc_index>`
0639  * in the high bits of &drm_wait_vblank_request.type.
0640  *
0641  * Starting kernel version 2.6.39, this capability is always set to 1.
0642  */
0643 #define DRM_CAP_VBLANK_HIGH_CRTC    0x2
0644 /**
0645  * DRM_CAP_DUMB_PREFERRED_DEPTH
0646  *
0647  * The preferred bit depth for dumb buffers.
0648  *
0649  * The bit depth is the number of bits used to indicate the color of a single
0650  * pixel excluding any padding. This is different from the number of bits per
0651  * pixel. For instance, XRGB8888 has a bit depth of 24 but has 32 bits per
0652  * pixel.
0653  *
0654  * Note that this preference only applies to dumb buffers, it's irrelevant for
0655  * other types of buffers.
0656  */
0657 #define DRM_CAP_DUMB_PREFERRED_DEPTH    0x3
0658 /**
0659  * DRM_CAP_DUMB_PREFER_SHADOW
0660  *
0661  * If set to 1, the driver prefers userspace to render to a shadow buffer
0662  * instead of directly rendering to a dumb buffer. For best speed, userspace
0663  * should do streaming ordered memory copies into the dumb buffer and never
0664  * read from it.
0665  *
0666  * Note that this preference only applies to dumb buffers, it's irrelevant for
0667  * other types of buffers.
0668  */
0669 #define DRM_CAP_DUMB_PREFER_SHADOW  0x4
0670 /**
0671  * DRM_CAP_PRIME
0672  *
0673  * Bitfield of supported PRIME sharing capabilities. See &DRM_PRIME_CAP_IMPORT
0674  * and &DRM_PRIME_CAP_EXPORT.
0675  *
0676  * PRIME buffers are exposed as dma-buf file descriptors. See
0677  * Documentation/gpu/drm-mm.rst, section "PRIME Buffer Sharing".
0678  */
0679 #define DRM_CAP_PRIME           0x5
0680 /**
0681  * DRM_PRIME_CAP_IMPORT
0682  *
0683  * If this bit is set in &DRM_CAP_PRIME, the driver supports importing PRIME
0684  * buffers via the &DRM_IOCTL_PRIME_FD_TO_HANDLE ioctl.
0685  */
0686 #define  DRM_PRIME_CAP_IMPORT       0x1
0687 /**
0688  * DRM_PRIME_CAP_EXPORT
0689  *
0690  * If this bit is set in &DRM_CAP_PRIME, the driver supports exporting PRIME
0691  * buffers via the &DRM_IOCTL_PRIME_HANDLE_TO_FD ioctl.
0692  */
0693 #define  DRM_PRIME_CAP_EXPORT       0x2
0694 /**
0695  * DRM_CAP_TIMESTAMP_MONOTONIC
0696  *
0697  * If set to 0, the kernel will report timestamps with ``CLOCK_REALTIME`` in
0698  * struct drm_event_vblank. If set to 1, the kernel will report timestamps with
0699  * ``CLOCK_MONOTONIC``. See ``clock_gettime(2)`` for the definition of these
0700  * clocks.
0701  *
0702  * Starting from kernel version 2.6.39, the default value for this capability
0703  * is 1. Starting kernel version 4.15, this capability is always set to 1.
0704  */
0705 #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
0706 /**
0707  * DRM_CAP_ASYNC_PAGE_FLIP
0708  *
0709  * If set to 1, the driver supports &DRM_MODE_PAGE_FLIP_ASYNC.
0710  */
0711 #define DRM_CAP_ASYNC_PAGE_FLIP     0x7
0712 /**
0713  * DRM_CAP_CURSOR_WIDTH
0714  *
0715  * The ``CURSOR_WIDTH`` and ``CURSOR_HEIGHT`` capabilities return a valid
0716  * width x height combination for the hardware cursor. The intention is that a
0717  * hardware agnostic userspace can query a cursor plane size to use.
0718  *
0719  * Note that the cross-driver contract is to merely return a valid size;
0720  * drivers are free to attach another meaning on top, eg. i915 returns the
0721  * maximum plane size.
0722  */
0723 #define DRM_CAP_CURSOR_WIDTH        0x8
0724 /**
0725  * DRM_CAP_CURSOR_HEIGHT
0726  *
0727  * See &DRM_CAP_CURSOR_WIDTH.
0728  */
0729 #define DRM_CAP_CURSOR_HEIGHT       0x9
0730 /**
0731  * DRM_CAP_ADDFB2_MODIFIERS
0732  *
0733  * If set to 1, the driver supports supplying modifiers in the
0734  * &DRM_IOCTL_MODE_ADDFB2 ioctl.
0735  */
0736 #define DRM_CAP_ADDFB2_MODIFIERS    0x10
0737 /**
0738  * DRM_CAP_PAGE_FLIP_TARGET
0739  *
0740  * If set to 1, the driver supports the &DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE and
0741  * &DRM_MODE_PAGE_FLIP_TARGET_RELATIVE flags in
0742  * &drm_mode_crtc_page_flip_target.flags for the &DRM_IOCTL_MODE_PAGE_FLIP
0743  * ioctl.
0744  */
0745 #define DRM_CAP_PAGE_FLIP_TARGET    0x11
0746 /**
0747  * DRM_CAP_CRTC_IN_VBLANK_EVENT
0748  *
0749  * If set to 1, the kernel supports reporting the CRTC ID in
0750  * &drm_event_vblank.crtc_id for the &DRM_EVENT_VBLANK and
0751  * &DRM_EVENT_FLIP_COMPLETE events.
0752  *
0753  * Starting kernel version 4.12, this capability is always set to 1.
0754  */
0755 #define DRM_CAP_CRTC_IN_VBLANK_EVENT    0x12
0756 /**
0757  * DRM_CAP_SYNCOBJ
0758  *
0759  * If set to 1, the driver supports sync objects. See
0760  * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
0761  */
0762 #define DRM_CAP_SYNCOBJ     0x13
0763 /**
0764  * DRM_CAP_SYNCOBJ_TIMELINE
0765  *
0766  * If set to 1, the driver supports timeline operations on sync objects. See
0767  * Documentation/gpu/drm-mm.rst, section "DRM Sync Objects".
0768  */
0769 #define DRM_CAP_SYNCOBJ_TIMELINE    0x14
0770
0771 /* DRM_IOCTL_GET_CAP ioctl argument type */
0772 struct drm_get_cap {
0773     __u64 capability;
0774     __u64 value;
0775 };
0776
0777 /**
0778  * DRM_CLIENT_CAP_STEREO_3D
0779  *
0780  * If set to 1, the DRM core will expose the stereo 3D capabilities of the
0781  * monitor by advertising the supported 3D layouts in the flags of struct
0782  * drm_mode_modeinfo. See ``DRM_MODE_FLAG_3D_*``.
0783  *
0784  * This capability is always supported for all drivers starting from kernel
0785  * version 3.13.
0786  */
0787 #define DRM_CLIENT_CAP_STEREO_3D    1
0788
0789 /**
0790  * DRM_CLIENT_CAP_UNIVERSAL_PLANES
0791  *
0792  * If set to 1, the DRM core will expose all planes (overlay, primary, and
0793  * cursor) to userspace.
0794  *
0795  * This capability has been introduced in kernel version 3.15. Starting from
0796  * kernel version 3.17, this capability is always supported for all drivers.
0797  */
0798 #define DRM_CLIENT_CAP_UNIVERSAL_PLANES  2
0799
0800 /**
0801  * DRM_CLIENT_CAP_ATOMIC
0802  *
0803  * If set to 1, the DRM core will expose atomic properties to userspace. This
0804  * implicitly enables &DRM_CLIENT_CAP_UNIVERSAL_PLANES and
0805  * &DRM_CLIENT_CAP_ASPECT_RATIO.
0806  *
0807  * If the driver doesn't support atomic mode-setting, enabling this capability
0808  * will fail with -EOPNOTSUPP.
0809  *
0810  * This capability has been introduced in kernel version 4.0. Starting from
0811  * kernel version 4.2, this capability is always supported for atomic-capable
0812  * drivers.
0813  */
0814 #define DRM_CLIENT_CAP_ATOMIC   3
0815
0816 /**
0817  * DRM_CLIENT_CAP_ASPECT_RATIO
0818  *
0819  * If set to 1, the DRM core will provide aspect ratio information in modes.
0820  * See ``DRM_MODE_FLAG_PIC_AR_*``.
0821  *
0822  * This capability is always supported for all drivers starting from kernel
0823  * version 4.18.
0824  */
0825 #define DRM_CLIENT_CAP_ASPECT_RATIO    4
0826
0827 /**
0828  * DRM_CLIENT_CAP_WRITEBACK_CONNECTORS
0829  *
0830  * If set to 1, the DRM core will expose special connectors to be used for
0831  * writing back to memory the scene setup in the commit. The client must enable
0832  * &DRM_CLIENT_CAP_ATOMIC first.
0833  *
0834  * This capability is always supported for atomic-capable drivers starting from
0835  * kernel version 4.19.
0836  */
0837 #define DRM_CLIENT_CAP_WRITEBACK_CONNECTORS 5
0838
0839 /* DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
0840 struct drm_set_client_cap {
0841     __u64 capability;
0842     __u64 value;
0843 };
0844
0845 #define DRM_RDWR O_RDWR
0846 #define DRM_CLOEXEC O_CLOEXEC
0847 struct drm_prime_handle {
0848     __u32 handle;
0849
0850     /** Flags.. only applicable for handle->fd */
0851     __u32 flags;
0852
0853     /** Returned dmabuf file descriptor */
0854     __s32 fd;
0855 };
0856
0857 struct drm_syncobj_create {
0858     __u32 handle;
0859 #define DRM_SYNCOBJ_CREATE_SIGNALED (1 << 0)
0860     __u32 flags;
0861 };
0862
0863 struct drm_syncobj_destroy {
0864     __u32 handle;
0865     __u32 pad;
0866 };
0867
0868 #define DRM_SYNCOBJ_FD_TO_HANDLE_FLAGS_IMPORT_SYNC_FILE (1 << 0)
0869 #define DRM_SYNCOBJ_HANDLE_TO_FD_FLAGS_EXPORT_SYNC_FILE (1 << 0)
0870 struct drm_syncobj_handle {
0871     __u32 handle;
0872     __u32 flags;
0873
0874     __s32 fd;
0875     __u32 pad;
0876 };
0877
0878 struct drm_syncobj_transfer {
0879     __u32 src_handle;
0880     __u32 dst_handle;
0881     __u64 src_point;
0882     __u64 dst_point;
0883     __u32 flags;
0884     __u32 pad;
0885 };
0886
0887 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_ALL (1 << 0)
0888 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_FOR_SUBMIT (1 << 1)
0889 #define DRM_SYNCOBJ_WAIT_FLAGS_WAIT_AVAILABLE (1 << 2) /* wait for time point to become available */
0890 struct drm_syncobj_wait {
0891     __u64 handles;
0892     /* absolute timeout */
0893     __s64 timeout_nsec;
0894     __u32 count_handles;
0895     __u32 flags;
0896     __u32 first_signaled; /* only valid when not waiting all */
0897     __u32 pad;
0898 };
0899
0900 struct drm_syncobj_timeline_wait {
0901     __u64 handles;
0902     /* wait on specific timeline point for every handles*/
0903     __u64 points;
0904     /* absolute timeout */
0905     __s64 timeout_nsec;
0906     __u32 count_handles;
0907     __u32 flags;
0908     __u32 first_signaled; /* only valid when not waiting all */
0909     __u32 pad;
0910 };
0911
0912
0913 struct drm_syncobj_array {
0914     __u64 handles;
0915     __u32 count_handles;
0916     __u32 pad;
0917 };
0918
0919 #define DRM_SYNCOBJ_QUERY_FLAGS_LAST_SUBMITTED (1 << 0) /* last available point on timeline syncobj */
0920 struct drm_syncobj_timeline_array {
0921     __u64 handles;
0922     __u64 points;
0923     __u32 count_handles;
0924     __u32 flags;
0925 };
0926
0927
0928 /* Query current scanout sequence number */
0929 struct drm_crtc_get_sequence {
0930     __u32 crtc_id;      /* requested crtc_id */
0931     __u32 active;       /* return: crtc output is active */
0932     __u64 sequence;     /* return: most recent vblank sequence */
0933     __s64 sequence_ns;  /* return: most recent time of first pixel out */
0934 };
0935
0936 /* Queue event to be delivered at specified sequence. Time stamp marks
0937  * when the first pixel of the refresh cycle leaves the display engine
0938  * for the display
0939  */
0940 #define DRM_CRTC_SEQUENCE_RELATIVE      0x00000001  /* sequence is relative to current */
0941 #define DRM_CRTC_SEQUENCE_NEXT_ON_MISS      0x00000002  /* Use next sequence if we've missed */
0942
0943 struct drm_crtc_queue_sequence {
0944     __u32 crtc_id;
0945     __u32 flags;
0946     __u64 sequence;     /* on input, target sequence. on output, actual sequence */
0947     __u64 user_data;    /* user data passed to event */
0948 };
0949
0950 #if defined(__cplusplus)
0951 }
0952 #endif
0953
0954 #include "drm_mode.h"
0955
0956 #if defined(__cplusplus)
0957 extern "C" {
0958 #endif
0959
0960 #define DRM_IOCTL_BASE          'd'
0961 #define DRM_IO(nr)          _IO(DRM_IOCTL_BASE,nr)
0962 #define DRM_IOR(nr,type)        _IOR(DRM_IOCTL_BASE,nr,type)
0963 #define DRM_IOW(nr,type)        _IOW(DRM_IOCTL_BASE,nr,type)
0964 #define DRM_IOWR(nr,type)       _IOWR(DRM_IOCTL_BASE,nr,type)
0965
0966 #define DRM_IOCTL_VERSION       DRM_IOWR(0x00, struct drm_version)
0967 #define DRM_IOCTL_GET_UNIQUE        DRM_IOWR(0x01, struct drm_unique)
0968 #define DRM_IOCTL_GET_MAGIC     DRM_IOR( 0x02, struct drm_auth)
0969 #define DRM_IOCTL_IRQ_BUSID     DRM_IOWR(0x03, struct drm_irq_busid)
0970 #define DRM_IOCTL_GET_MAP               DRM_IOWR(0x04, struct drm_map)
0971 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
0972 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
0973 #define DRM_IOCTL_SET_VERSION       DRM_IOWR(0x07, struct drm_set_version)
0974 #define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
0975 #define DRM_IOCTL_GEM_CLOSE     DRM_IOW (0x09, struct drm_gem_close)
0976 #define DRM_IOCTL_GEM_FLINK     DRM_IOWR(0x0a, struct drm_gem_flink)
0977 #define DRM_IOCTL_GEM_OPEN      DRM_IOWR(0x0b, struct drm_gem_open)
0978 #define DRM_IOCTL_GET_CAP       DRM_IOWR(0x0c, struct drm_get_cap)
0979 #define DRM_IOCTL_SET_CLIENT_CAP    DRM_IOW( 0x0d, struct drm_set_client_cap)
0980
0981 #define DRM_IOCTL_SET_UNIQUE        DRM_IOW( 0x10, struct drm_unique)
0982 #define DRM_IOCTL_AUTH_MAGIC        DRM_IOW( 0x11, struct drm_auth)
0983 #define DRM_IOCTL_BLOCK         DRM_IOWR(0x12, struct drm_block)
0984 #define DRM_IOCTL_UNBLOCK       DRM_IOWR(0x13, struct drm_block)
0985 #define DRM_IOCTL_CONTROL       DRM_IOW( 0x14, struct drm_control)
0986 #define DRM_IOCTL_ADD_MAP       DRM_IOWR(0x15, struct drm_map)
0987 #define DRM_IOCTL_ADD_BUFS      DRM_IOWR(0x16, struct drm_buf_desc)
0988 #define DRM_IOCTL_MARK_BUFS     DRM_IOW( 0x17, struct drm_buf_desc)
0989 #define DRM_IOCTL_INFO_BUFS     DRM_IOWR(0x18, struct drm_buf_info)
0990 #define DRM_IOCTL_MAP_BUFS      DRM_IOWR(0x19, struct drm_buf_map)
0991 #define DRM_IOCTL_FREE_BUFS     DRM_IOW( 0x1a, struct drm_buf_free)
0992
0993 #define DRM_IOCTL_RM_MAP        DRM_IOW( 0x1b, struct drm_map)
0994
0995 #define DRM_IOCTL_SET_SAREA_CTX     DRM_IOW( 0x1c, struct drm_ctx_priv_map)
0996 #define DRM_IOCTL_GET_SAREA_CTX     DRM_IOWR(0x1d, struct drm_ctx_priv_map)
0997
0998 #define DRM_IOCTL_SET_MASTER            DRM_IO(0x1e)
0999 #define DRM_IOCTL_DROP_MASTER           DRM_IO(0x1f)
1000
1001 #define DRM_IOCTL_ADD_CTX       DRM_IOWR(0x20, struct drm_ctx)
1002 #define DRM_IOCTL_RM_CTX        DRM_IOWR(0x21, struct drm_ctx)
1003 #define DRM_IOCTL_MOD_CTX       DRM_IOW( 0x22, struct drm_ctx)
1004 #define DRM_IOCTL_GET_CTX       DRM_IOWR(0x23, struct drm_ctx)
1005 #define DRM_IOCTL_SWITCH_CTX        DRM_IOW( 0x24, struct drm_ctx)
1006 #define DRM_IOCTL_NEW_CTX       DRM_IOW( 0x25, struct drm_ctx)
1007 #define DRM_IOCTL_RES_CTX       DRM_IOWR(0x26, struct drm_ctx_res)
1008 #define DRM_IOCTL_ADD_DRAW      DRM_IOWR(0x27, struct drm_draw)
1009 #define DRM_IOCTL_RM_DRAW       DRM_IOWR(0x28, struct drm_draw)
1010 #define DRM_IOCTL_DMA           DRM_IOWR(0x29, struct drm_dma)
1011 #define DRM_IOCTL_LOCK          DRM_IOW( 0x2a, struct drm_lock)
1012 #define DRM_IOCTL_UNLOCK        DRM_IOW( 0x2b, struct drm_lock)
1013 #define DRM_IOCTL_FINISH        DRM_IOW( 0x2c, struct drm_lock)
1014
1015 #define DRM_IOCTL_PRIME_HANDLE_TO_FD    DRM_IOWR(0x2d, struct drm_prime_handle)
1016 #define DRM_IOCTL_PRIME_FD_TO_HANDLE    DRM_IOWR(0x2e, struct drm_prime_handle)
1017
1018 #define DRM_IOCTL_AGP_ACQUIRE       DRM_IO(  0x30)
1019 #define DRM_IOCTL_AGP_RELEASE       DRM_IO(  0x31)
1020 #define DRM_IOCTL_AGP_ENABLE        DRM_IOW( 0x32, struct drm_agp_mode)
1021 #define DRM_IOCTL_AGP_INFO      DRM_IOR( 0x33, struct drm_agp_info)
1022 #define DRM_IOCTL_AGP_ALLOC     DRM_IOWR(0x34, struct drm_agp_buffer)
1023 #define DRM_IOCTL_AGP_FREE      DRM_IOW( 0x35, struct drm_agp_buffer)
1024 #define DRM_IOCTL_AGP_BIND      DRM_IOW( 0x36, struct drm_agp_binding)
1025 #define DRM_IOCTL_AGP_UNBIND        DRM_IOW( 0x37, struct drm_agp_binding)
1026
1027 #define DRM_IOCTL_SG_ALLOC      DRM_IOWR(0x38, struct drm_scatter_gather)
1028 #define DRM_IOCTL_SG_FREE       DRM_IOW( 0x39, struct drm_scatter_gather)
1029
1030 #define DRM_IOCTL_WAIT_VBLANK       DRM_IOWR(0x3a, union drm_wait_vblank)
1031
1032 #define DRM_IOCTL_CRTC_GET_SEQUENCE DRM_IOWR(0x3b, struct drm_crtc_get_sequence)
1033 #define DRM_IOCTL_CRTC_QUEUE_SEQUENCE   DRM_IOWR(0x3c, struct drm_crtc_queue_sequence)
1034
1035 #define DRM_IOCTL_UPDATE_DRAW       DRM_IOW(0x3f, struct drm_update_draw)
1036
1037 #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
1038 #define DRM_IOCTL_MODE_GETCRTC      DRM_IOWR(0xA1, struct drm_mode_crtc)
1039 #define DRM_IOCTL_MODE_SETCRTC      DRM_IOWR(0xA2, struct drm_mode_crtc)
1040 #define DRM_IOCTL_MODE_CURSOR       DRM_IOWR(0xA3, struct drm_mode_cursor)
1041 #define DRM_IOCTL_MODE_GETGAMMA     DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
1042 #define DRM_IOCTL_MODE_SETGAMMA     DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
1043 #define DRM_IOCTL_MODE_GETENCODER   DRM_IOWR(0xA6, struct drm_mode_get_encoder)
1044 #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
1045 #define DRM_IOCTL_MODE_ATTACHMODE   DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
1046 #define DRM_IOCTL_MODE_DETACHMODE   DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
1047
1048 #define DRM_IOCTL_MODE_GETPROPERTY  DRM_IOWR(0xAA, struct drm_mode_get_property)
1049 #define DRM_IOCTL_MODE_SETPROPERTY  DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
1050 #define DRM_IOCTL_MODE_GETPROPBLOB  DRM_IOWR(0xAC, struct drm_mode_get_blob)
1051 #define DRM_IOCTL_MODE_GETFB        DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
1052 #define DRM_IOCTL_MODE_ADDFB        DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
1053 /**
1054  * DRM_IOCTL_MODE_RMFB - Remove a framebuffer.
1055  *
1056  * This removes a framebuffer previously added via ADDFB/ADDFB2. The IOCTL
1057  * argument is a framebuffer object ID.
1058  *
1059  * Warning: removing a framebuffer currently in-use on an enabled plane will
1060  * disable that plane. The CRTC the plane is linked to may also be disabled
1061  * (depending on driver capabilities).
1062  */
1063 #define DRM_IOCTL_MODE_RMFB     DRM_IOWR(0xAF, unsigned int)
1064 #define DRM_IOCTL_MODE_PAGE_FLIP    DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
1065 #define DRM_IOCTL_MODE_DIRTYFB      DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
1066
1067 #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
1068 #define DRM_IOCTL_MODE_MAP_DUMB    DRM_IOWR(0xB3, struct drm_mode_map_dumb)
1069 #define DRM_IOCTL_MODE_DESTROY_DUMB    DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
1070 #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
1071 #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
1072 #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
1073 #define DRM_IOCTL_MODE_ADDFB2       DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
1074 #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES    DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
1075 #define DRM_IOCTL_MODE_OBJ_SETPROPERTY  DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
1076 #define DRM_IOCTL_MODE_CURSOR2      DRM_IOWR(0xBB, struct drm_mode_cursor2)
1077 #define DRM_IOCTL_MODE_ATOMIC       DRM_IOWR(0xBC, struct drm_mode_atomic)
1078 #define DRM_IOCTL_MODE_CREATEPROPBLOB   DRM_IOWR(0xBD, struct drm_mode_create_blob)
1079 #define DRM_IOCTL_MODE_DESTROYPROPBLOB  DRM_IOWR(0xBE, struct drm_mode_destroy_blob)
1080
1081 #define DRM_IOCTL_SYNCOBJ_CREATE    DRM_IOWR(0xBF, struct drm_syncobj_create)
1082 #define DRM_IOCTL_SYNCOBJ_DESTROY   DRM_IOWR(0xC0, struct drm_syncobj_destroy)
1083 #define DRM_IOCTL_SYNCOBJ_HANDLE_TO_FD  DRM_IOWR(0xC1, struct drm_syncobj_handle)
1084 #define DRM_IOCTL_SYNCOBJ_FD_TO_HANDLE  DRM_IOWR(0xC2, struct drm_syncobj_handle)
1085 #define DRM_IOCTL_SYNCOBJ_WAIT      DRM_IOWR(0xC3, struct drm_syncobj_wait)
1086 #define DRM_IOCTL_SYNCOBJ_RESET     DRM_IOWR(0xC4, struct drm_syncobj_array)
1087 #define DRM_IOCTL_SYNCOBJ_SIGNAL    DRM_IOWR(0xC5, struct drm_syncobj_array)
1088
1089 #define DRM_IOCTL_MODE_CREATE_LEASE DRM_IOWR(0xC6, struct drm_mode_create_lease)
1090 #define DRM_IOCTL_MODE_LIST_LESSEES DRM_IOWR(0xC7, struct drm_mode_list_lessees)
1091 #define DRM_IOCTL_MODE_GET_LEASE    DRM_IOWR(0xC8, struct drm_mode_get_lease)
1092 #define DRM_IOCTL_MODE_REVOKE_LEASE DRM_IOWR(0xC9, struct drm_mode_revoke_lease)
1093
1094 #define DRM_IOCTL_SYNCOBJ_TIMELINE_WAIT DRM_IOWR(0xCA, struct drm_syncobj_timeline_wait)
1095 #define DRM_IOCTL_SYNCOBJ_QUERY     DRM_IOWR(0xCB, struct drm_syncobj_timeline_array)
1096 #define DRM_IOCTL_SYNCOBJ_TRANSFER  DRM_IOWR(0xCC, struct drm_syncobj_transfer)
1097 #define DRM_IOCTL_SYNCOBJ_TIMELINE_SIGNAL   DRM_IOWR(0xCD, struct drm_syncobj_timeline_array)
1098
1099 /**
1100  * DRM_IOCTL_MODE_GETFB2 - Get framebuffer metadata.
1101  *
1102  * This queries metadata about a framebuffer. User-space fills
1103  * &drm_mode_fb_cmd2.fb_id as the input, and the kernels fills the rest of the
1104  * struct as the output.
1105  *
1106  * If the client is DRM master or has &CAP_SYS_ADMIN, &drm_mode_fb_cmd2.handles
1107  * will be filled with GEM buffer handles. Planes are valid until one has a
1108  * zero handle -- this can be used to compute the number of planes.
1109  *
1110  * Otherwise, &drm_mode_fb_cmd2.handles will be zeroed and planes are valid
1111  * until one has a zero &drm_mode_fb_cmd2.pitches.
1112  *
1113  * If the framebuffer has a format modifier, &DRM_MODE_FB_MODIFIERS will be set
1114  * in &drm_mode_fb_cmd2.flags and &drm_mode_fb_cmd2.modifier will contain the
1115  * modifier. Otherwise, user-space must ignore &drm_mode_fb_cmd2.modifier.
1116  */
1117 #define DRM_IOCTL_MODE_GETFB2       DRM_IOWR(0xCE, struct drm_mode_fb_cmd2)
1118
1119 /*
1120  * Device specific ioctls should only be in their respective headers
1121  * The device specific ioctl range is from 0x40 to 0x9f.
1122  * Generic IOCTLS restart at 0xA0.
1123  *
1124  * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
1125  * drmCommandReadWrite().
1126  */
1127 #define DRM_COMMAND_BASE                0x40
1128 #define DRM_COMMAND_END         0xA0
1129
1130 /*
1131  * Header for events written back to userspace on the drm fd.  The
1132  * type defines the type of event, the length specifies the total
1133  * length of the event (including the header), and user_data is
1134  * typically a 64 bit value passed with the ioctl that triggered the
1135  * event.  A read on the drm fd will always only return complete
1136  * events, that is, if for example the read buffer is 100 bytes, and
1137  * there are two 64 byte events pending, only one will be returned.
1138  *
1139  * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
1140  * up are chipset specific.
1141  */
1142 struct drm_event {
1143     __u32 type;
1144     __u32 length;
1145 };
1146
1147 #define DRM_EVENT_VBLANK 0x01
1148 #define DRM_EVENT_FLIP_COMPLETE 0x02
1149 #define DRM_EVENT_CRTC_SEQUENCE 0x03
1150
1151 struct drm_event_vblank {
1152     struct drm_event base;
1153     __u64 user_data;
1154     __u32 tv_sec;
1155     __u32 tv_usec;
1156     __u32 sequence;
1157     __u32 crtc_id; /* 0 on older kernels that do not support this */
1158 };
1159
1160 /* Event delivered at sequence. Time stamp marks when the first pixel
1161  * of the refresh cycle leaves the display engine for the display
1162  */
1163 struct drm_event_crtc_sequence {
1164     struct drm_event    base;
1165     __u64           user_data;
1166     __s64           time_ns;
1167     __u64           sequence;
1168 };
1169
1170 /* typedef area */
1171 #ifndef __KERNEL__
1172 typedef struct drm_clip_rect drm_clip_rect_t;
1173 typedef struct drm_drawable_info drm_drawable_info_t;
1174 typedef struct drm_tex_region drm_tex_region_t;
1175 typedef struct drm_hw_lock drm_hw_lock_t;
1176 typedef struct drm_version drm_version_t;
1177 typedef struct drm_unique drm_unique_t;
1178 typedef struct drm_list drm_list_t;
1179 typedef struct drm_block drm_block_t;
1180 typedef struct drm_control drm_control_t;
1181 typedef enum drm_map_type drm_map_type_t;
1182 typedef enum drm_map_flags drm_map_flags_t;
1183 typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
1184 typedef struct drm_map drm_map_t;
1185 typedef struct drm_client drm_client_t;
1186 typedef enum drm_stat_type drm_stat_type_t;
1187 typedef struct drm_stats drm_stats_t;
1188 typedef enum drm_lock_flags drm_lock_flags_t;
1189 typedef struct drm_lock drm_lock_t;
1190 typedef enum drm_dma_flags drm_dma_flags_t;
1191 typedef struct drm_buf_desc drm_buf_desc_t;
1192 typedef struct drm_buf_info drm_buf_info_t;
1193 typedef struct drm_buf_free drm_buf_free_t;
1194 typedef struct drm_buf_pub drm_buf_pub_t;
1195 typedef struct drm_buf_map drm_buf_map_t;
1196 typedef struct drm_dma drm_dma_t;
1197 typedef union drm_wait_vblank drm_wait_vblank_t;
1198 typedef struct drm_agp_mode drm_agp_mode_t;
1199 typedef enum drm_ctx_flags drm_ctx_flags_t;
1200 typedef struct drm_ctx drm_ctx_t;
1201 typedef struct drm_ctx_res drm_ctx_res_t;
1202 typedef struct drm_draw drm_draw_t;
1203 typedef struct drm_update_draw drm_update_draw_t;
1204 typedef struct drm_auth drm_auth_t;
1205 typedef struct drm_irq_busid drm_irq_busid_t;
1206 typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
1207
1208 typedef struct drm_agp_buffer drm_agp_buffer_t;
1209 typedef struct drm_agp_binding drm_agp_binding_t;
1210 typedef struct drm_agp_info drm_agp_info_t;
1211 typedef struct drm_scatter_gather drm_scatter_gather_t;
1212 typedef struct drm_set_version drm_set_version_t;
1213 #endif
1214
1215 #if defined(__cplusplus)
1216 }
1217 #endif
1218
1219 #endif