include/sound/wm8903.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * linux/sound/wm8903.h -- Platform data for WM8903
0004  *
0005  * Copyright 2010 Wolfson Microelectronics. PLC.
0006  */
0007
0008 #ifndef __LINUX_SND_WM8903_H
0009 #define __LINUX_SND_WM8903_H
0010
0011 /*
0012  * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of
0013  * zero in platform data means "don't touch this pin".
0014  */
0015 #define WM8903_GPIO_CONFIG_ZERO 0x8000
0016
0017 /*
0018  * R6 (0x06) - Mic Bias Control 0
0019  */
0020 #define WM8903_MICDET_THR_MASK                  0x0030  /* MICDET_THR - [5:4] */
0021 #define WM8903_MICDET_THR_SHIFT                      4  /* MICDET_THR - [5:4] */
0022 #define WM8903_MICDET_THR_WIDTH                      2  /* MICDET_THR - [5:4] */
0023 #define WM8903_MICSHORT_THR_MASK                0x000C  /* MICSHORT_THR - [3:2] */
0024 #define WM8903_MICSHORT_THR_SHIFT                    2  /* MICSHORT_THR - [3:2] */
0025 #define WM8903_MICSHORT_THR_WIDTH                    2  /* MICSHORT_THR - [3:2] */
0026 #define WM8903_MICDET_ENA                       0x0002  /* MICDET_ENA */
0027 #define WM8903_MICDET_ENA_MASK                  0x0002  /* MICDET_ENA */
0028 #define WM8903_MICDET_ENA_SHIFT                      1  /* MICDET_ENA */
0029 #define WM8903_MICDET_ENA_WIDTH                      1  /* MICDET_ENA */
0030 #define WM8903_MICBIAS_ENA                      0x0001  /* MICBIAS_ENA */
0031 #define WM8903_MICBIAS_ENA_MASK                 0x0001  /* MICBIAS_ENA */
0032 #define WM8903_MICBIAS_ENA_SHIFT                     0  /* MICBIAS_ENA */
0033 #define WM8903_MICBIAS_ENA_WIDTH                     1  /* MICBIAS_ENA */
0034
0035 /*
0036  * WM8903_GPn_FN values
0037  *
0038  * See datasheets for list of valid values per pin
0039  */
0040 #define WM8903_GPn_FN_GPIO_OUTPUT                    0
0041 #define WM8903_GPn_FN_BCLK                           1
0042 #define WM8903_GPn_FN_IRQ_OUTPT                      2
0043 #define WM8903_GPn_FN_GPIO_INPUT                     3
0044 #define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT         4
0045 #define WM8903_GPn_FN_MICBIAS_SHORT_DETECT           5
0046 #define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT             6
0047 #define WM8903_GPn_FN_FLL_LOCK_OUTPUT                8
0048 #define WM8903_GPn_FN_FLL_CLOCK_OUTPUT               9
0049
0050 /*
0051  * R116 (0x74) - GPIO Control 1
0052  */
0053 #define WM8903_GP1_FN_MASK                      0x1F00  /* GP1_FN - [12:8] */
0054 #define WM8903_GP1_FN_SHIFT                          8  /* GP1_FN - [12:8] */
0055 #define WM8903_GP1_FN_WIDTH                          5  /* GP1_FN - [12:8] */
0056 #define WM8903_GP1_DIR                          0x0080  /* GP1_DIR */
0057 #define WM8903_GP1_DIR_MASK                     0x0080  /* GP1_DIR */
0058 #define WM8903_GP1_DIR_SHIFT                         7  /* GP1_DIR */
0059 #define WM8903_GP1_DIR_WIDTH                         1  /* GP1_DIR */
0060 #define WM8903_GP1_OP_CFG                       0x0040  /* GP1_OP_CFG */
0061 #define WM8903_GP1_OP_CFG_MASK                  0x0040  /* GP1_OP_CFG */
0062 #define WM8903_GP1_OP_CFG_SHIFT                      6  /* GP1_OP_CFG */
0063 #define WM8903_GP1_OP_CFG_WIDTH                      1  /* GP1_OP_CFG */
0064 #define WM8903_GP1_IP_CFG                       0x0020  /* GP1_IP_CFG */
0065 #define WM8903_GP1_IP_CFG_MASK                  0x0020  /* GP1_IP_CFG */
0066 #define WM8903_GP1_IP_CFG_SHIFT                      5  /* GP1_IP_CFG */
0067 #define WM8903_GP1_IP_CFG_WIDTH                      1  /* GP1_IP_CFG */
0068 #define WM8903_GP1_LVL                          0x0010  /* GP1_LVL */
0069 #define WM8903_GP1_LVL_MASK                     0x0010  /* GP1_LVL */
0070 #define WM8903_GP1_LVL_SHIFT                         4  /* GP1_LVL */
0071 #define WM8903_GP1_LVL_WIDTH                         1  /* GP1_LVL */
0072 #define WM8903_GP1_PD                           0x0008  /* GP1_PD */
0073 #define WM8903_GP1_PD_MASK                      0x0008  /* GP1_PD */
0074 #define WM8903_GP1_PD_SHIFT                          3  /* GP1_PD */
0075 #define WM8903_GP1_PD_WIDTH                          1  /* GP1_PD */
0076 #define WM8903_GP1_PU                           0x0004  /* GP1_PU */
0077 #define WM8903_GP1_PU_MASK                      0x0004  /* GP1_PU */
0078 #define WM8903_GP1_PU_SHIFT                          2  /* GP1_PU */
0079 #define WM8903_GP1_PU_WIDTH                          1  /* GP1_PU */
0080 #define WM8903_GP1_INTMODE                      0x0002  /* GP1_INTMODE */
0081 #define WM8903_GP1_INTMODE_MASK                 0x0002  /* GP1_INTMODE */
0082 #define WM8903_GP1_INTMODE_SHIFT                     1  /* GP1_INTMODE */
0083 #define WM8903_GP1_INTMODE_WIDTH                     1  /* GP1_INTMODE */
0084 #define WM8903_GP1_DB                           0x0001  /* GP1_DB */
0085 #define WM8903_GP1_DB_MASK                      0x0001  /* GP1_DB */
0086 #define WM8903_GP1_DB_SHIFT                          0  /* GP1_DB */
0087 #define WM8903_GP1_DB_WIDTH                          1  /* GP1_DB */
0088
0089 /*
0090  * R117 (0x75) - GPIO Control 2
0091  */
0092 #define WM8903_GP2_FN_MASK                      0x1F00  /* GP2_FN - [12:8] */
0093 #define WM8903_GP2_FN_SHIFT                          8  /* GP2_FN - [12:8] */
0094 #define WM8903_GP2_FN_WIDTH                          5  /* GP2_FN - [12:8] */
0095 #define WM8903_GP2_DIR                          0x0080  /* GP2_DIR */
0096 #define WM8903_GP2_DIR_MASK                     0x0080  /* GP2_DIR */
0097 #define WM8903_GP2_DIR_SHIFT                         7  /* GP2_DIR */
0098 #define WM8903_GP2_DIR_WIDTH                         1  /* GP2_DIR */
0099 #define WM8903_GP2_OP_CFG                       0x0040  /* GP2_OP_CFG */
0100 #define WM8903_GP2_OP_CFG_MASK                  0x0040  /* GP2_OP_CFG */
0101 #define WM8903_GP2_OP_CFG_SHIFT                      6  /* GP2_OP_CFG */
0102 #define WM8903_GP2_OP_CFG_WIDTH                      1  /* GP2_OP_CFG */
0103 #define WM8903_GP2_IP_CFG                       0x0020  /* GP2_IP_CFG */
0104 #define WM8903_GP2_IP_CFG_MASK                  0x0020  /* GP2_IP_CFG */
0105 #define WM8903_GP2_IP_CFG_SHIFT                      5  /* GP2_IP_CFG */
0106 #define WM8903_GP2_IP_CFG_WIDTH                      1  /* GP2_IP_CFG */
0107 #define WM8903_GP2_LVL                          0x0010  /* GP2_LVL */
0108 #define WM8903_GP2_LVL_MASK                     0x0010  /* GP2_LVL */
0109 #define WM8903_GP2_LVL_SHIFT                         4  /* GP2_LVL */
0110 #define WM8903_GP2_LVL_WIDTH                         1  /* GP2_LVL */
0111 #define WM8903_GP2_PD                           0x0008  /* GP2_PD */
0112 #define WM8903_GP2_PD_MASK                      0x0008  /* GP2_PD */
0113 #define WM8903_GP2_PD_SHIFT                          3  /* GP2_PD */
0114 #define WM8903_GP2_PD_WIDTH                          1  /* GP2_PD */
0115 #define WM8903_GP2_PU                           0x0004  /* GP2_PU */
0116 #define WM8903_GP2_PU_MASK                      0x0004  /* GP2_PU */
0117 #define WM8903_GP2_PU_SHIFT                          2  /* GP2_PU */
0118 #define WM8903_GP2_PU_WIDTH                          1  /* GP2_PU */
0119 #define WM8903_GP2_INTMODE                      0x0002  /* GP2_INTMODE */
0120 #define WM8903_GP2_INTMODE_MASK                 0x0002  /* GP2_INTMODE */
0121 #define WM8903_GP2_INTMODE_SHIFT                     1  /* GP2_INTMODE */
0122 #define WM8903_GP2_INTMODE_WIDTH                     1  /* GP2_INTMODE */
0123 #define WM8903_GP2_DB                           0x0001  /* GP2_DB */
0124 #define WM8903_GP2_DB_MASK                      0x0001  /* GP2_DB */
0125 #define WM8903_GP2_DB_SHIFT                          0  /* GP2_DB */
0126 #define WM8903_GP2_DB_WIDTH                          1  /* GP2_DB */
0127
0128 /*
0129  * R118 (0x76) - GPIO Control 3
0130  */
0131 #define WM8903_GP3_FN_MASK                      0x1F00  /* GP3_FN - [12:8] */
0132 #define WM8903_GP3_FN_SHIFT                          8  /* GP3_FN - [12:8] */
0133 #define WM8903_GP3_FN_WIDTH                          5  /* GP3_FN - [12:8] */
0134 #define WM8903_GP3_DIR                          0x0080  /* GP3_DIR */
0135 #define WM8903_GP3_DIR_MASK                     0x0080  /* GP3_DIR */
0136 #define WM8903_GP3_DIR_SHIFT                         7  /* GP3_DIR */
0137 #define WM8903_GP3_DIR_WIDTH                         1  /* GP3_DIR */
0138 #define WM8903_GP3_OP_CFG                       0x0040  /* GP3_OP_CFG */
0139 #define WM8903_GP3_OP_CFG_MASK                  0x0040  /* GP3_OP_CFG */
0140 #define WM8903_GP3_OP_CFG_SHIFT                      6  /* GP3_OP_CFG */
0141 #define WM8903_GP3_OP_CFG_WIDTH                      1  /* GP3_OP_CFG */
0142 #define WM8903_GP3_IP_CFG                       0x0020  /* GP3_IP_CFG */
0143 #define WM8903_GP3_IP_CFG_MASK                  0x0020  /* GP3_IP_CFG */
0144 #define WM8903_GP3_IP_CFG_SHIFT                      5  /* GP3_IP_CFG */
0145 #define WM8903_GP3_IP_CFG_WIDTH                      1  /* GP3_IP_CFG */
0146 #define WM8903_GP3_LVL                          0x0010  /* GP3_LVL */
0147 #define WM8903_GP3_LVL_MASK                     0x0010  /* GP3_LVL */
0148 #define WM8903_GP3_LVL_SHIFT                         4  /* GP3_LVL */
0149 #define WM8903_GP3_LVL_WIDTH                         1  /* GP3_LVL */
0150 #define WM8903_GP3_PD                           0x0008  /* GP3_PD */
0151 #define WM8903_GP3_PD_MASK                      0x0008  /* GP3_PD */
0152 #define WM8903_GP3_PD_SHIFT                          3  /* GP3_PD */
0153 #define WM8903_GP3_PD_WIDTH                          1  /* GP3_PD */
0154 #define WM8903_GP3_PU                           0x0004  /* GP3_PU */
0155 #define WM8903_GP3_PU_MASK                      0x0004  /* GP3_PU */
0156 #define WM8903_GP3_PU_SHIFT                          2  /* GP3_PU */
0157 #define WM8903_GP3_PU_WIDTH                          1  /* GP3_PU */
0158 #define WM8903_GP3_INTMODE                      0x0002  /* GP3_INTMODE */
0159 #define WM8903_GP3_INTMODE_MASK                 0x0002  /* GP3_INTMODE */
0160 #define WM8903_GP3_INTMODE_SHIFT                     1  /* GP3_INTMODE */
0161 #define WM8903_GP3_INTMODE_WIDTH                     1  /* GP3_INTMODE */
0162 #define WM8903_GP3_DB                           0x0001  /* GP3_DB */
0163 #define WM8903_GP3_DB_MASK                      0x0001  /* GP3_DB */
0164 #define WM8903_GP3_DB_SHIFT                          0  /* GP3_DB */
0165 #define WM8903_GP3_DB_WIDTH                          1  /* GP3_DB */
0166
0167 /*
0168  * R119 (0x77) - GPIO Control 4
0169  */
0170 #define WM8903_GP4_FN_MASK                      0x1F00  /* GP4_FN - [12:8] */
0171 #define WM8903_GP4_FN_SHIFT                          8  /* GP4_FN - [12:8] */
0172 #define WM8903_GP4_FN_WIDTH                          5  /* GP4_FN - [12:8] */
0173 #define WM8903_GP4_DIR                          0x0080  /* GP4_DIR */
0174 #define WM8903_GP4_DIR_MASK                     0x0080  /* GP4_DIR */
0175 #define WM8903_GP4_DIR_SHIFT                         7  /* GP4_DIR */
0176 #define WM8903_GP4_DIR_WIDTH                         1  /* GP4_DIR */
0177 #define WM8903_GP4_OP_CFG                       0x0040  /* GP4_OP_CFG */
0178 #define WM8903_GP4_OP_CFG_MASK                  0x0040  /* GP4_OP_CFG */
0179 #define WM8903_GP4_OP_CFG_SHIFT                      6  /* GP4_OP_CFG */
0180 #define WM8903_GP4_OP_CFG_WIDTH                      1  /* GP4_OP_CFG */
0181 #define WM8903_GP4_IP_CFG                       0x0020  /* GP4_IP_CFG */
0182 #define WM8903_GP4_IP_CFG_MASK                  0x0020  /* GP4_IP_CFG */
0183 #define WM8903_GP4_IP_CFG_SHIFT                      5  /* GP4_IP_CFG */
0184 #define WM8903_GP4_IP_CFG_WIDTH                      1  /* GP4_IP_CFG */
0185 #define WM8903_GP4_LVL                          0x0010  /* GP4_LVL */
0186 #define WM8903_GP4_LVL_MASK                     0x0010  /* GP4_LVL */
0187 #define WM8903_GP4_LVL_SHIFT                         4  /* GP4_LVL */
0188 #define WM8903_GP4_LVL_WIDTH                         1  /* GP4_LVL */
0189 #define WM8903_GP4_PD                           0x0008  /* GP4_PD */
0190 #define WM8903_GP4_PD_MASK                      0x0008  /* GP4_PD */
0191 #define WM8903_GP4_PD_SHIFT                          3  /* GP4_PD */
0192 #define WM8903_GP4_PD_WIDTH                          1  /* GP4_PD */
0193 #define WM8903_GP4_PU                           0x0004  /* GP4_PU */
0194 #define WM8903_GP4_PU_MASK                      0x0004  /* GP4_PU */
0195 #define WM8903_GP4_PU_SHIFT                          2  /* GP4_PU */
0196 #define WM8903_GP4_PU_WIDTH                          1  /* GP4_PU */
0197 #define WM8903_GP4_INTMODE                      0x0002  /* GP4_INTMODE */
0198 #define WM8903_GP4_INTMODE_MASK                 0x0002  /* GP4_INTMODE */
0199 #define WM8903_GP4_INTMODE_SHIFT                     1  /* GP4_INTMODE */
0200 #define WM8903_GP4_INTMODE_WIDTH                     1  /* GP4_INTMODE */
0201 #define WM8903_GP4_DB                           0x0001  /* GP4_DB */
0202 #define WM8903_GP4_DB_MASK                      0x0001  /* GP4_DB */
0203 #define WM8903_GP4_DB_SHIFT                          0  /* GP4_DB */
0204 #define WM8903_GP4_DB_WIDTH                          1  /* GP4_DB */
0205
0206 /*
0207  * R120 (0x78) - GPIO Control 5
0208  */
0209 #define WM8903_GP5_FN_MASK                      0x1F00  /* GP5_FN - [12:8] */
0210 #define WM8903_GP5_FN_SHIFT                          8  /* GP5_FN - [12:8] */
0211 #define WM8903_GP5_FN_WIDTH                          5  /* GP5_FN - [12:8] */
0212 #define WM8903_GP5_DIR                          0x0080  /* GP5_DIR */
0213 #define WM8903_GP5_DIR_MASK                     0x0080  /* GP5_DIR */
0214 #define WM8903_GP5_DIR_SHIFT                         7  /* GP5_DIR */
0215 #define WM8903_GP5_DIR_WIDTH                         1  /* GP5_DIR */
0216 #define WM8903_GP5_OP_CFG                       0x0040  /* GP5_OP_CFG */
0217 #define WM8903_GP5_OP_CFG_MASK                  0x0040  /* GP5_OP_CFG */
0218 #define WM8903_GP5_OP_CFG_SHIFT                      6  /* GP5_OP_CFG */
0219 #define WM8903_GP5_OP_CFG_WIDTH                      1  /* GP5_OP_CFG */
0220 #define WM8903_GP5_IP_CFG                       0x0020  /* GP5_IP_CFG */
0221 #define WM8903_GP5_IP_CFG_MASK                  0x0020  /* GP5_IP_CFG */
0222 #define WM8903_GP5_IP_CFG_SHIFT                      5  /* GP5_IP_CFG */
0223 #define WM8903_GP5_IP_CFG_WIDTH                      1  /* GP5_IP_CFG */
0224 #define WM8903_GP5_LVL                          0x0010  /* GP5_LVL */
0225 #define WM8903_GP5_LVL_MASK                     0x0010  /* GP5_LVL */
0226 #define WM8903_GP5_LVL_SHIFT                         4  /* GP5_LVL */
0227 #define WM8903_GP5_LVL_WIDTH                         1  /* GP5_LVL */
0228 #define WM8903_GP5_PD                           0x0008  /* GP5_PD */
0229 #define WM8903_GP5_PD_MASK                      0x0008  /* GP5_PD */
0230 #define WM8903_GP5_PD_SHIFT                          3  /* GP5_PD */
0231 #define WM8903_GP5_PD_WIDTH                          1  /* GP5_PD */
0232 #define WM8903_GP5_PU                           0x0004  /* GP5_PU */
0233 #define WM8903_GP5_PU_MASK                      0x0004  /* GP5_PU */
0234 #define WM8903_GP5_PU_SHIFT                          2  /* GP5_PU */
0235 #define WM8903_GP5_PU_WIDTH                          1  /* GP5_PU */
0236 #define WM8903_GP5_INTMODE                      0x0002  /* GP5_INTMODE */
0237 #define WM8903_GP5_INTMODE_MASK                 0x0002  /* GP5_INTMODE */
0238 #define WM8903_GP5_INTMODE_SHIFT                     1  /* GP5_INTMODE */
0239 #define WM8903_GP5_INTMODE_WIDTH                     1  /* GP5_INTMODE */
0240 #define WM8903_GP5_DB                           0x0001  /* GP5_DB */
0241 #define WM8903_GP5_DB_MASK                      0x0001  /* GP5_DB */
0242 #define WM8903_GP5_DB_SHIFT                          0  /* GP5_DB */
0243 #define WM8903_GP5_DB_WIDTH                          1  /* GP5_DB */
0244
0245 #define WM8903_NUM_GPIO 5
0246
0247 struct wm8903_platform_data {
0248     bool irq_active_low;   /* Set if IRQ active low, default high */
0249
0250         /* Default register value for R6 (Mic bias), used to configure
0251      * microphone detection.  In conjunction with gpio_cfg this
0252      * can be used to route the microphone status signals out onto
0253      * the GPIOs for use with snd_soc_jack_add_gpios().
0254      */
0255     u16 micdet_cfg;
0256
0257     int micdet_delay;      /* Delay after microphone detection (ms) */
0258
0259     int gpio_base;
0260     u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */
0261 };
0262
0263 #endif