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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for Digigram VX soundcards
0004  *
0005  * Hardware core part
0006  *
0007  * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de>
0008  */
0009 
0010 #ifndef __SOUND_VX_COMMON_H
0011 #define __SOUND_VX_COMMON_H
0012 
0013 #include <sound/pcm.h>
0014 #include <sound/hwdep.h>
0015 #include <linux/interrupt.h>
0016 
0017 struct firmware;
0018 struct device;
0019 
0020 #define VX_DRIVER_VERSION   0x010000    /* 1.0.0 */
0021 
0022 /*
0023  */
0024 #define SIZE_MAX_CMD    0x10
0025 #define SIZE_MAX_STATUS 0x10
0026 
0027 struct vx_rmh {
0028     u16 LgCmd;      /* length of the command to send (WORDs) */
0029     u16 LgStat;     /* length of the status received (WORDs) */
0030     u32 Cmd[SIZE_MAX_CMD];
0031     u32 Stat[SIZE_MAX_STATUS];
0032     u16 DspStat;    /* status type, RMP_SSIZE_XXX */
0033 };
0034     
0035 typedef u64 pcx_time_t;
0036 
0037 #define VX_MAX_PIPES    16
0038 #define VX_MAX_PERIODS  32
0039 #define VX_MAX_CODECS   2
0040 
0041 struct vx_ibl_info {
0042     int size;   /* the current IBL size (0 = query) in bytes */
0043     int max_size;   /* max. IBL size in bytes */
0044     int min_size;   /* min. IBL size in bytes */
0045     int granularity;    /* granularity */
0046 };
0047 
0048 struct vx_pipe {
0049     int number;
0050     unsigned int is_capture: 1;
0051     unsigned int data_mode: 1;
0052     unsigned int running: 1;
0053     unsigned int prepared: 1;
0054     int channels;
0055     unsigned int differed_type;
0056     pcx_time_t pcx_time;
0057     struct snd_pcm_substream *substream;
0058 
0059     int hbuf_size;      /* H-buffer size in bytes */
0060     int buffer_bytes;   /* the ALSA pcm buffer size in bytes */
0061     int period_bytes;   /* the ALSA pcm period size in bytes */
0062     int hw_ptr;     /* the current hardware pointer in bytes */
0063     int position;       /* the current position in frames (playback only) */
0064     int transferred;    /* the transferred size (per period) in frames */
0065     int align;      /* size of alignment */
0066     u64 cur_count;      /* current sample position (for playback) */
0067 
0068     unsigned int references;     /* an output pipe may be used for monitoring and/or playback */
0069     struct vx_pipe *monitoring_pipe;  /* pointer to the monitoring pipe (capture pipe only)*/
0070 };
0071 
0072 struct vx_core;
0073 
0074 struct snd_vx_ops {
0075     /* low-level i/o */
0076     unsigned char (*in8)(struct vx_core *chip, int reg);
0077     unsigned int (*in32)(struct vx_core *chip, int reg);
0078     void (*out8)(struct vx_core *chip, int reg, unsigned char val);
0079     void (*out32)(struct vx_core *chip, int reg, unsigned int val);
0080     /* irq */
0081     int (*test_and_ack)(struct vx_core *chip);
0082     void (*validate_irq)(struct vx_core *chip, int enable);
0083     /* codec */
0084     void (*write_codec)(struct vx_core *chip, int codec, unsigned int data);
0085     void (*akm_write)(struct vx_core *chip, int reg, unsigned int data);
0086     void (*reset_codec)(struct vx_core *chip);
0087     void (*change_audio_source)(struct vx_core *chip, int src);
0088     void (*set_clock_source)(struct vx_core *chp, int src);
0089     /* chip init */
0090     int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw);
0091     void (*reset_dsp)(struct vx_core *chip);
0092     void (*reset_board)(struct vx_core *chip, int cold_reset);
0093     int (*add_controls)(struct vx_core *chip);
0094     /* pcm */
0095     void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0096               struct vx_pipe *pipe, int count);
0097     void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0098               struct vx_pipe *pipe, int count);
0099 };
0100 
0101 struct snd_vx_hardware {
0102     const char *name;
0103     int type;   /* VX_TYPE_XXX */
0104 
0105     /* hardware specs */
0106     unsigned int num_codecs;
0107     unsigned int num_ins;
0108     unsigned int num_outs;
0109     unsigned int output_level_max;
0110     const unsigned int *output_level_db_scale;
0111 };
0112 
0113 /* hwdep id string */
0114 #define SND_VX_HWDEP_ID     "VX Loader"
0115 
0116 /* hardware type */
0117 enum {
0118     /* VX222 PCI */
0119     VX_TYPE_BOARD,      /* old VX222 PCI */
0120     VX_TYPE_V2,     /* VX222 V2 PCI */
0121     VX_TYPE_MIC,        /* VX222 Mic PCI */
0122     /* VX-pocket */
0123     VX_TYPE_VXPOCKET,   /* VXpocket V2 */
0124     VX_TYPE_VXP440,     /* VXpocket 440 */
0125     VX_TYPE_NUMS
0126 };
0127 
0128 /* chip status */
0129 enum {
0130     VX_STAT_XILINX_LOADED   = (1 << 0), /* devices are registered */
0131     VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */
0132     VX_STAT_CHIP_INIT   = (1 << 2), /* all operational */
0133     VX_STAT_IN_SUSPEND  = (1 << 10),    /* in suspend phase */
0134     VX_STAT_IS_STALE    = (1 << 15) /* device is stale */
0135 };
0136 
0137 /* min/max values for analog output for old codecs */
0138 #define VX_ANALOG_OUT_LEVEL_MAX     0xe3
0139 
0140 struct vx_core {
0141     /* ALSA stuff */
0142     struct snd_card *card;
0143     struct snd_pcm *pcm[VX_MAX_CODECS];
0144     int type;   /* VX_TYPE_XXX */
0145 
0146     int irq;
0147     /* ports are defined externally */
0148 
0149     /* low-level functions */
0150     const struct snd_vx_hardware *hw;
0151     const struct snd_vx_ops *ops;
0152 
0153     struct mutex lock;
0154 
0155     unsigned int chip_status;
0156     unsigned int pcm_running;
0157 
0158     struct device *dev;
0159     struct snd_hwdep *hwdep;
0160 
0161     struct vx_rmh irq_rmh;  /* RMH used in interrupts */
0162 
0163     unsigned int audio_info; /* see VX_AUDIO_INFO */
0164     unsigned int audio_ins;
0165     unsigned int audio_outs;
0166     struct vx_pipe **playback_pipes;
0167     struct vx_pipe **capture_pipes;
0168 
0169     /* clock and audio sources */
0170     unsigned int audio_source;  /* current audio input source */
0171     unsigned int audio_source_target;
0172     unsigned int clock_mode;    /* clock mode (VX_CLOCK_MODE_XXX) */
0173     unsigned int clock_source;  /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */
0174     unsigned int freq;      /* current frequency */
0175     unsigned int freq_detected; /* detected frequency from digital in */
0176     unsigned int uer_detected;  /* VX_UER_MODE_XXX */
0177     unsigned int uer_bits;  /* IEC958 status bits */
0178     struct vx_ibl_info ibl; /* IBL information */
0179 
0180     /* mixer setting */
0181     int output_level[VX_MAX_CODECS][2]; /* analog output level */
0182     int audio_gain[2][4];           /* digital audio level (playback/capture) */
0183     unsigned char audio_active[4];      /* mute/unmute on digital playback */
0184     int audio_monitor[4];           /* playback hw-monitor level */
0185     unsigned char audio_monitor_active[4];  /* playback hw-monitor mute/unmute */
0186 
0187     struct mutex mixer_mutex;
0188 
0189     const struct firmware *firmware[4]; /* loaded firmware data */
0190 };
0191 
0192 
0193 /*
0194  * constructor
0195  */
0196 struct vx_core *snd_vx_create(struct snd_card *card,
0197                   const struct snd_vx_hardware *hw,
0198                   const struct snd_vx_ops *ops, int extra_size);
0199 int snd_vx_setup_firmware(struct vx_core *chip);
0200 int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp);
0201 int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp);
0202 int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp);
0203 
0204 void snd_vx_free_firmware(struct vx_core *chip);
0205 
0206 /*
0207  * interrupt handler; exported for pcmcia
0208  */
0209 irqreturn_t snd_vx_irq_handler(int irq, void *dev);
0210 irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev);
0211 
0212 /*
0213  * lowlevel functions
0214  */
0215 static inline int vx_test_and_ack(struct vx_core *chip)
0216 {
0217     return chip->ops->test_and_ack(chip);
0218 }
0219 
0220 static inline void vx_validate_irq(struct vx_core *chip, int enable)
0221 {
0222     chip->ops->validate_irq(chip, enable);
0223 }
0224 
0225 static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
0226 {
0227     return chip->ops->in8(chip, reg);
0228 }
0229 
0230 static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
0231 {
0232     return chip->ops->in32(chip, reg);
0233 }
0234 
0235 static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
0236 {
0237     chip->ops->out8(chip, reg, val);
0238 }
0239 
0240 static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
0241 {
0242     chip->ops->out32(chip, reg, val);
0243 }
0244 
0245 #define vx_inb(chip,reg)    snd_vx_inb(chip, VX_##reg)
0246 #define vx_outb(chip,reg,val)   snd_vx_outb(chip, VX_##reg,val)
0247 #define vx_inl(chip,reg)    snd_vx_inl(chip, VX_##reg)
0248 #define vx_outl(chip,reg,val)   snd_vx_outl(chip, VX_##reg,val)
0249 
0250 static inline void vx_reset_dsp(struct vx_core *chip)
0251 {
0252     chip->ops->reset_dsp(chip);
0253 }
0254 
0255 int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh);
0256 int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh);
0257 int vx_send_rih(struct vx_core *chip, int cmd);
0258 int vx_send_rih_nolock(struct vx_core *chip, int cmd);
0259 
0260 void vx_reset_codec(struct vx_core *chip, int cold_reset);
0261 
0262 /*
0263  * check the bit on the specified register
0264  * returns zero if a bit matches, or a negative error code.
0265  * exported for vxpocket driver
0266  */
0267 int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time);
0268 #define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time)
0269 #define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200)
0270 #define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL)
0271 
0272 
0273 /*
0274  * pseudo-DMA transfer
0275  */
0276 static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0277                        struct vx_pipe *pipe, int count)
0278 {
0279     chip->ops->dma_write(chip, runtime, pipe, count);
0280 }
0281 
0282 static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
0283                       struct vx_pipe *pipe, int count)
0284 {
0285     chip->ops->dma_read(chip, runtime, pipe, count);
0286 }
0287 
0288 
0289 
0290 /* error with hardware code,
0291  * the return value is -(VX_ERR_MASK | actual-hw-error-code)
0292  */
0293 #define VX_ERR_MASK 0x1000000
0294 #define vx_get_error(err)   (-(err) & ~VX_ERR_MASK)
0295 
0296 
0297 /*
0298  * pcm stuff
0299  */
0300 int snd_vx_pcm_new(struct vx_core *chip);
0301 void vx_pcm_update_intr(struct vx_core *chip, unsigned int events);
0302 
0303 /*
0304  * mixer stuff
0305  */
0306 int snd_vx_mixer_new(struct vx_core *chip);
0307 void vx_toggle_dac_mute(struct vx_core *chip, int mute);
0308 int vx_sync_audio_source(struct vx_core *chip);
0309 int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active);
0310 
0311 /*
0312  * IEC958 & clock stuff
0313  */
0314 void vx_set_iec958_status(struct vx_core *chip, unsigned int bits);
0315 int vx_set_clock(struct vx_core *chip, unsigned int freq);
0316 void vx_set_internal_clock(struct vx_core *chip, unsigned int freq);
0317 int vx_change_frequency(struct vx_core *chip);
0318 
0319 
0320 /*
0321  * PM
0322  */
0323 int snd_vx_suspend(struct vx_core *card);
0324 int snd_vx_resume(struct vx_core *card);
0325 
0326 /*
0327  * hardware constants
0328  */
0329 
0330 #define vx_has_new_dsp(chip)    ((chip)->type != VX_TYPE_BOARD)
0331 #define vx_is_pcmcia(chip)  ((chip)->type >= VX_TYPE_VXPOCKET)
0332 
0333 /* audio input source */
0334 enum {
0335     VX_AUDIO_SRC_DIGITAL,
0336     VX_AUDIO_SRC_LINE,
0337     VX_AUDIO_SRC_MIC
0338 };
0339 
0340 /* clock source */
0341 enum {
0342     INTERNAL_QUARTZ,
0343     UER_SYNC
0344 };
0345 
0346 /* clock mode */
0347 enum {
0348     VX_CLOCK_MODE_AUTO, /* depending on the current audio source */
0349     VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */
0350     VX_CLOCK_MODE_EXTERNAL  /* fixed to UER sync */
0351 };
0352 
0353 /* SPDIF/UER type */
0354 enum {
0355     VX_UER_MODE_CONSUMER,
0356     VX_UER_MODE_PROFESSIONAL,
0357     VX_UER_MODE_NOT_PRESENT,
0358 };
0359 
0360 /* register indices */
0361 enum {
0362     VX_ICR,
0363     VX_CVR,
0364     VX_ISR,
0365     VX_IVR,
0366     VX_RXH,
0367     VX_TXH = VX_RXH,
0368     VX_RXM,
0369     VX_TXM = VX_RXM,
0370     VX_RXL,
0371     VX_TXL = VX_RXL,
0372     VX_DMA,
0373     VX_CDSP,
0374     VX_RFREQ,
0375     VX_RUER_V2,
0376     VX_GAIN,
0377     VX_DATA = VX_GAIN,
0378     VX_MEMIRQ,
0379     VX_ACQ,
0380     VX_BIT0,
0381     VX_BIT1,
0382     VX_MIC0,
0383     VX_MIC1,
0384     VX_MIC2,
0385     VX_MIC3,
0386     VX_PLX0,
0387     VX_PLX1,
0388     VX_PLX2,
0389 
0390     VX_LOFREQ,  // V2: ACQ, VP: RFREQ
0391     VX_HIFREQ,  // V2: BIT0, VP: RUER_V2
0392     VX_CSUER,   // V2: BIT1, VP: BIT0
0393     VX_RUER,    // V2: RUER_V2, VP: BIT1
0394 
0395     VX_REG_MAX,
0396 
0397     /* aliases for VX board */
0398     VX_RESET_DMA = VX_ISR,
0399     VX_CFG = VX_RFREQ,
0400     VX_STATUS = VX_MEMIRQ,
0401     VX_SELMIC = VX_MIC0,
0402     VX_COMPOT = VX_MIC1,
0403     VX_SCOMPR = VX_MIC2,
0404     VX_GLIMIT = VX_MIC3,
0405     VX_INTCSR = VX_PLX0,
0406     VX_CNTRL = VX_PLX1,
0407     VX_GPIOC = VX_PLX2,
0408 
0409     /* aliases for VXPOCKET board */
0410     VX_MICRO = VX_MEMIRQ,
0411     VX_CODEC2 = VX_MEMIRQ,
0412     VX_DIALOG = VX_ACQ,
0413 
0414 };
0415 
0416 /* RMH status type */
0417 enum {
0418     RMH_SSIZE_FIXED = 0,    /* status size given by the driver (in LgStat) */
0419     RMH_SSIZE_ARG = 1,  /* status size given in the LSB byte */
0420     RMH_SSIZE_MASK = 2, /* status size given in bitmask */
0421 };
0422 
0423 
0424 /* bits for ICR register */
0425 #define ICR_HF1     0x10
0426 #define ICR_HF0     0x08
0427 #define ICR_TREQ    0x02    /* Interrupt mode + HREQ set on for transfer (->DSP) request */
0428 #define ICR_RREQ    0x01    /* Interrupt mode + RREQ set on for transfer (->PC) request */
0429 
0430 /* bits for CVR register */
0431 #define CVR_HC      0x80
0432 
0433 /* bits for ISR register */
0434 #define ISR_HF3     0x10
0435 #define ISR_HF2     0x08
0436 #define ISR_CHK     0x10
0437 #define ISR_ERR     0x08
0438 #define ISR_TX_READY    0x04
0439 #define ISR_TX_EMPTY    0x02
0440 #define ISR_RX_FULL 0x01
0441 
0442 /* Constants used to access the DATA register */
0443 #define VX_DATA_CODEC_MASK  0x80
0444 #define VX_DATA_XICOR_MASK  0x80
0445 
0446 /* Constants used to access the CSUER register (both for VX2 and VXP) */
0447 #define VX_SUER_FREQ_MASK       0x0c
0448 #define VX_SUER_FREQ_32KHz_MASK     0x0c
0449 #define VX_SUER_FREQ_44KHz_MASK     0x00
0450 #define VX_SUER_FREQ_48KHz_MASK     0x04
0451 #define VX_SUER_DATA_PRESENT_MASK   0x02
0452 #define VX_SUER_CLOCK_PRESENT_MASK  0x01
0453 
0454 #define VX_CUER_HH_BITC_SEL_MASK    0x08
0455 #define VX_CUER_MH_BITC_SEL_MASK    0x04
0456 #define VX_CUER_ML_BITC_SEL_MASK    0x02
0457 #define VX_CUER_LL_BITC_SEL_MASK    0x01
0458 
0459 #define XX_UER_CBITS_OFFSET_MASK    0x1f
0460 
0461 
0462 /* bits for audio_info */
0463 #define VX_AUDIO_INFO_REAL_TIME (1<<0)  /* real-time processing available */
0464 #define VX_AUDIO_INFO_OFFLINE   (1<<1)  /* offline processing available */
0465 #define VX_AUDIO_INFO_MPEG1 (1<<5)
0466 #define VX_AUDIO_INFO_MPEG2 (1<<6)
0467 #define VX_AUDIO_INFO_LINEAR_8  (1<<7)
0468 #define VX_AUDIO_INFO_LINEAR_16 (1<<8)
0469 #define VX_AUDIO_INFO_LINEAR_24 (1<<9)
0470 
0471 /* DSP Interrupt Request values */
0472 #define VXP_IRQ_OFFSET      0x40 /* add 0x40 offset for vxpocket and vx222/v2 */
0473 /* call with vx_send_irq_dsp() */
0474 #define IRQ_MESS_WRITE_END          0x30
0475 #define IRQ_MESS_WRITE_NEXT         0x32
0476 #define IRQ_MESS_READ_NEXT          0x34
0477 #define IRQ_MESS_READ_END           0x36
0478 #define IRQ_MESSAGE                 0x38
0479 #define IRQ_RESET_CHK               0x3A
0480 #define IRQ_CONNECT_STREAM_NEXT     0x26
0481 #define IRQ_CONNECT_STREAM_END      0x28
0482 #define IRQ_PAUSE_START_CONNECT     0x2A
0483 #define IRQ_END_CONNECTION          0x2C
0484 
0485 /* Is there async. events pending ( IT Source Test ) */
0486 #define ASYNC_EVENTS_PENDING            0x008000
0487 #define HBUFFER_EVENTS_PENDING          0x004000   // Not always accurate
0488 #define NOTIF_EVENTS_PENDING            0x002000
0489 #define TIME_CODE_EVENT_PENDING         0x001000
0490 #define FREQUENCY_CHANGE_EVENT_PENDING  0x000800
0491 #define END_OF_BUFFER_EVENTS_PENDING    0x000400
0492 #define FATAL_DSP_ERROR                 0xff0000
0493 
0494 /* Stream Format Header Defines */ 
0495 #define HEADER_FMT_BASE         0xFED00000
0496 #define HEADER_FMT_MONO         0x000000C0
0497 #define HEADER_FMT_INTEL        0x00008000
0498 #define HEADER_FMT_16BITS       0x00002000
0499 #define HEADER_FMT_24BITS       0x00004000
0500 #define HEADER_FMT_UPTO11       0x00000200  /* frequency is less or equ. to 11k.*/
0501 #define HEADER_FMT_UPTO32       0x00000100  /* frequency is over 11k and less then 32k.*/
0502 
0503 /* Constants used to access the Codec */
0504 #define XX_CODEC_SELECTOR               0x20
0505 /* codec commands */
0506 #define XX_CODEC_ADC_CONTROL_REGISTER   0x01
0507 #define XX_CODEC_DAC_CONTROL_REGISTER   0x02
0508 #define XX_CODEC_LEVEL_LEFT_REGISTER    0x03
0509 #define XX_CODEC_LEVEL_RIGHT_REGISTER   0x04
0510 #define XX_CODEC_PORT_MODE_REGISTER     0x05
0511 #define XX_CODEC_STATUS_REPORT_REGISTER 0x06
0512 #define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07
0513 
0514 /*
0515  * Audio-level control values
0516  */
0517 #define CVAL_M110DB     0x000   /* -110dB */
0518 #define CVAL_M99DB      0x02C
0519 #define CVAL_M21DB      0x163
0520 #define CVAL_M18DB      0x16F
0521 #define CVAL_M10DB      0x18F
0522 #define CVAL_0DB        0x1B7
0523 #define CVAL_18DB       0x1FF   /* +18dB */
0524 #define CVAL_MAX        0x1FF
0525 
0526 #define AUDIO_IO_HAS_MUTE_LEVEL         0x400000
0527 #define AUDIO_IO_HAS_MUTE_MONITORING_1      0x200000
0528 #define AUDIO_IO_HAS_MUTE_MONITORING_2      0x100000
0529 #define VALID_AUDIO_IO_DIGITAL_LEVEL        0x01
0530 #define VALID_AUDIO_IO_MONITORING_LEVEL     0x02
0531 #define VALID_AUDIO_IO_MUTE_LEVEL       0x04
0532 #define VALID_AUDIO_IO_MUTE_MONITORING_1    0x08
0533 #define VALID_AUDIO_IO_MUTE_MONITORING_2    0x10
0534 
0535 
0536 #endif /* __SOUND_VX_COMMON_H */
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