sound/sof/topology.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2018 Intel Corporation. All rights reserved.
0007  */
0008
0009 #ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__
0010 #define __INCLUDE_SOUND_SOF_TOPOLOGY_H__
0011
0012 #include <sound/sof/header.h>
0013
0014 /*
0015  * Component
0016  */
0017
0018 /* types of component */
0019 enum sof_comp_type {
0020     SOF_COMP_NONE = 0,
0021     SOF_COMP_HOST,
0022     SOF_COMP_DAI,
0023     SOF_COMP_SG_HOST,   /**< scatter gather variant */
0024     SOF_COMP_SG_DAI,    /**< scatter gather variant */
0025     SOF_COMP_VOLUME,
0026     SOF_COMP_MIXER,
0027     SOF_COMP_MUX,
0028     SOF_COMP_SRC,
0029     SOF_COMP_SPLITTER,
0030     SOF_COMP_TONE,
0031     SOF_COMP_SWITCH,
0032     SOF_COMP_BUFFER,
0033     SOF_COMP_EQ_IIR,
0034     SOF_COMP_EQ_FIR,
0035     SOF_COMP_KEYWORD_DETECT,
0036     SOF_COMP_KPB,           /* A key phrase buffer component */
0037     SOF_COMP_SELECTOR,      /**< channel selector component */
0038     SOF_COMP_DEMUX,
0039     SOF_COMP_ASRC,      /**< Asynchronous sample rate converter */
0040     SOF_COMP_DCBLOCK,
0041     SOF_COMP_SMART_AMP,             /**< smart amplifier component */
0042     /* keep FILEREAD/FILEWRITE as the last ones */
0043     SOF_COMP_FILEREAD = 10000,  /**< host test based file IO */
0044     SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */
0045 };
0046
0047 /* XRUN action for component */
0048 #define SOF_XRUN_STOP       1   /**< stop stream */
0049 #define SOF_XRUN_UNDER_ZERO 2   /**< send 0s to sink */
0050 #define SOF_XRUN_OVER_NULL  4   /**< send data to NULL */
0051
0052 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */
0053 struct sof_ipc_comp {
0054     struct sof_ipc_cmd_hdr hdr;
0055     uint32_t id;
0056     enum sof_comp_type type;
0057     uint32_t pipeline_id;
0058     uint32_t core;
0059
0060     /* extended data length, 0 if no extended data */
0061     uint32_t ext_data_length;
0062 } __packed;
0063
0064 /*
0065  * Component Buffers
0066  */
0067
0068 /*
0069  * SOF memory capabilities, add new ones at the end
0070  */
0071 #define SOF_MEM_CAPS_RAM            (1 << 0)
0072 #define SOF_MEM_CAPS_ROM            (1 << 1)
0073 #define SOF_MEM_CAPS_EXT            (1 << 2) /**< external */
0074 #define SOF_MEM_CAPS_LP         (1 << 3) /**< low power */
0075 #define SOF_MEM_CAPS_HP         (1 << 4) /**< high performance */
0076 #define SOF_MEM_CAPS_DMA            (1 << 5) /**< DMA'able */
0077 #define SOF_MEM_CAPS_CACHE          (1 << 6) /**< cacheable */
0078 #define SOF_MEM_CAPS_EXEC           (1 << 7) /**< executable */
0079
0080 /*
0081  * overrun will cause ring buffer overwrite, instead of XRUN.
0082  */
0083 #define SOF_BUF_OVERRUN_PERMITTED   BIT(0)
0084
0085 /*
0086  * underrun will cause readback of 0s, instead of XRUN.
0087  */
0088 #define SOF_BUF_UNDERRUN_PERMITTED  BIT(1)
0089
0090 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */
0091 struct sof_ipc_buffer {
0092     struct sof_ipc_comp comp;
0093     uint32_t size;      /**< buffer size in bytes */
0094     uint32_t caps;      /**< SOF_MEM_CAPS_ */
0095     uint32_t flags;     /**< SOF_BUF_ flags defined above */
0096     uint32_t reserved;  /**< reserved for future use */
0097 } __packed;
0098
0099 /* generic component config data - must always be after struct sof_ipc_comp */
0100 struct sof_ipc_comp_config {
0101     struct sof_ipc_cmd_hdr hdr;
0102     uint32_t periods_sink;  /**< 0 means variable */
0103     uint32_t periods_source;/**< 0 means variable */
0104     uint32_t reserved1; /**< reserved */
0105     uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */
0106     uint32_t xrun_action;
0107
0108     /* reserved for future use */
0109     uint32_t reserved[2];
0110 } __packed;
0111
0112 /* generic host component */
0113 struct sof_ipc_comp_host {
0114     struct sof_ipc_comp comp;
0115     struct sof_ipc_comp_config config;
0116     uint32_t direction; /**< SOF_IPC_STREAM_ */
0117     uint32_t no_irq;    /**< don't send periodic IRQ to host/DSP */
0118     uint32_t dmac_config; /**< DMA engine specific */
0119 }  __packed;
0120
0121 /* generic DAI component */
0122 struct sof_ipc_comp_dai {
0123     struct sof_ipc_comp comp;
0124     struct sof_ipc_comp_config config;
0125     uint32_t direction; /**< SOF_IPC_STREAM_ */
0126     uint32_t dai_index; /**< index of this type dai */
0127     uint32_t type;      /**< DAI type - SOF_DAI_ */
0128     uint32_t reserved;  /**< reserved */
0129 }  __packed;
0130
0131 /* generic mixer component */
0132 struct sof_ipc_comp_mixer {
0133     struct sof_ipc_comp comp;
0134     struct sof_ipc_comp_config config;
0135 }  __packed;
0136
0137 /* volume ramping types */
0138 enum sof_volume_ramp {
0139     SOF_VOLUME_LINEAR   = 0,
0140     SOF_VOLUME_LOG,
0141     SOF_VOLUME_LINEAR_ZC,
0142     SOF_VOLUME_LOG_ZC,
0143 };
0144
0145 /* generic volume component */
0146 struct sof_ipc_comp_volume {
0147     struct sof_ipc_comp comp;
0148     struct sof_ipc_comp_config config;
0149     uint32_t channels;
0150     uint32_t min_value;
0151     uint32_t max_value;
0152     uint32_t ramp;      /**< SOF_VOLUME_ */
0153     uint32_t initial_ramp;  /**< ramp space in ms */
0154 }  __packed;
0155
0156 /* generic SRC component */
0157 struct sof_ipc_comp_src {
0158     struct sof_ipc_comp comp;
0159     struct sof_ipc_comp_config config;
0160     /* either source or sink rate must be non zero */
0161     uint32_t source_rate;   /**< source rate or 0 for variable */
0162     uint32_t sink_rate; /**< sink rate or 0 for variable */
0163     uint32_t rate_mask; /**< SOF_RATE_ supported rates */
0164 } __packed;
0165
0166 /* generic ASRC component */
0167 struct sof_ipc_comp_asrc {
0168     struct sof_ipc_comp comp;
0169     struct sof_ipc_comp_config config;
0170     /* either source or sink rate must be non zero */
0171     uint32_t source_rate;       /**< Define fixed source rate or */
0172                     /**< use 0 to indicate need to get */
0173                     /**< the rate from stream */
0174     uint32_t sink_rate;     /**< Define fixed sink rate or */
0175                     /**< use 0 to indicate need to get */
0176                     /**< the rate from stream */
0177     uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */
0178                     /**< When 1 the ASRC tracks and */
0179                     /**< compensates for drift. */
0180     uint32_t operation_mode;    /**< push 0, pull 1, In push mode the */
0181                     /**< ASRC consumes a defined number */
0182                     /**< of frames at input, with varying */
0183                     /**< number of frames at output. */
0184                     /**< In pull mode the ASRC outputs */
0185                     /**< a defined number of frames while */
0186                     /**< number of input frames varies. */
0187
0188     /* reserved for future use */
0189     uint32_t reserved[4];
0190 } __attribute__((packed));
0191
0192 /* generic MUX component */
0193 struct sof_ipc_comp_mux {
0194     struct sof_ipc_comp comp;
0195     struct sof_ipc_comp_config config;
0196 } __packed;
0197
0198 /* generic tone generator component */
0199 struct sof_ipc_comp_tone {
0200     struct sof_ipc_comp comp;
0201     struct sof_ipc_comp_config config;
0202     int32_t sample_rate;
0203     int32_t frequency;
0204     int32_t amplitude;
0205     int32_t freq_mult;
0206     int32_t ampl_mult;
0207     int32_t length;
0208     int32_t period;
0209     int32_t repeats;
0210     int32_t ramp_step;
0211 } __packed;
0212
0213 /** \brief Types of processing components */
0214 enum sof_ipc_process_type {
0215     SOF_PROCESS_NONE = 0,       /**< None */
0216     SOF_PROCESS_EQFIR,      /**< Intel FIR */
0217     SOF_PROCESS_EQIIR,      /**< Intel IIR */
0218     SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */
0219     SOF_PROCESS_KPB,        /**< KeyPhrase Buffer Manager */
0220     SOF_PROCESS_CHAN_SELECTOR,  /**< Channel Selector */
0221     SOF_PROCESS_MUX,
0222     SOF_PROCESS_DEMUX,
0223     SOF_PROCESS_DCBLOCK,
0224     SOF_PROCESS_SMART_AMP,  /**< Smart Amplifier */
0225 };
0226
0227 /* generic "effect", "codec" or proprietary processing component */
0228 struct sof_ipc_comp_process {
0229     struct sof_ipc_comp comp;
0230     struct sof_ipc_comp_config config;
0231     uint32_t size;  /**< size of bespoke data section in bytes */
0232     uint32_t type;  /**< sof_ipc_process_type */
0233
0234     /* reserved for future use */
0235     uint32_t reserved[7];
0236
0237     uint8_t data[];
0238 } __packed;
0239
0240 /* frees components, buffers and pipelines
0241  * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE
0242  */
0243 struct sof_ipc_free {
0244     struct sof_ipc_cmd_hdr hdr;
0245     uint32_t id;
0246 } __packed;
0247
0248 struct sof_ipc_comp_reply {
0249     struct sof_ipc_reply rhdr;
0250     uint32_t id;
0251     uint32_t offset;
0252 } __packed;
0253
0254 /*
0255  * Pipeline
0256  */
0257
0258 /** \brief Types of pipeline scheduling time domains */
0259 enum sof_ipc_pipe_sched_time_domain {
0260     SOF_TIME_DOMAIN_DMA = 0,    /**< DMA interrupt */
0261     SOF_TIME_DOMAIN_TIMER,      /**< Timer interrupt */
0262 };
0263
0264 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */
0265 struct sof_ipc_pipe_new {
0266     struct sof_ipc_cmd_hdr hdr;
0267     uint32_t comp_id;   /**< component id for pipeline */
0268     uint32_t pipeline_id;   /**< pipeline id */
0269     uint32_t sched_id;  /**< Scheduling component id */
0270     uint32_t core;      /**< core we run on */
0271     uint32_t period;    /**< execution period in us*/
0272     uint32_t priority;  /**< priority level 0 (low) to 10 (max) */
0273     uint32_t period_mips;   /**< worst case instruction count per period */
0274     uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */
0275     uint32_t xrun_limit_usecs; /**< report xruns greater than limit */
0276     uint32_t time_domain;   /**< scheduling time domain */
0277 }  __packed;
0278
0279 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */
0280 struct sof_ipc_pipe_ready {
0281     struct sof_ipc_cmd_hdr hdr;
0282     uint32_t comp_id;
0283 }  __packed;
0284
0285 struct sof_ipc_pipe_free {
0286     struct sof_ipc_cmd_hdr hdr;
0287     uint32_t comp_id;
0288 }  __packed;
0289
0290 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */
0291 struct sof_ipc_pipe_comp_connect {
0292     struct sof_ipc_cmd_hdr hdr;
0293     uint32_t source_id;
0294     uint32_t sink_id;
0295 }  __packed;
0296
0297 /* external events */
0298 enum sof_event_types {
0299     SOF_EVENT_NONE = 0,
0300     SOF_KEYWORD_DETECT_DAPM_EVENT,
0301 };
0302
0303 #endif