sof/ipc4/header.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2022 Intel Corporation. All rights reserved.
0007  */
0008
0009 #ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
0010 #define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__
0011
0012 #include <linux/types.h>
0013 #include <uapi/sound/sof/abi.h>
0014
0015 /* maximum message size for mailbox Tx/Rx */
0016 #define SOF_IPC4_MSG_MAX_SIZE           4096
0017
0018 /** \addtogroup sof_uapi uAPI
0019  *  SOF uAPI specification.
0020  *  @{
0021  */
0022
0023 /**
0024  * struct sof_ipc4_msg - Placeholder of an IPC4 message
0025  * @header_u64:     IPC4 header as single u64 number
0026  * @primary:        Primary, mandatory part of the header
0027  * @extension:      Extended part of the header, if not used it should be
0028  *          set to 0
0029  * @data_size:      Size of data in bytes pointed by @data_ptr
0030  * @data_ptr:       Pointer to the optional payload of a message
0031  */
0032 struct sof_ipc4_msg {
0033     union {
0034         u64 header_u64;
0035         struct {
0036             u32 primary;
0037             u32 extension;
0038         };
0039     };
0040
0041     size_t data_size;
0042     void *data_ptr;
0043 };
0044
0045 /**
0046  * struct sof_ipc4_tuple - Generic type/ID and parameter tuple
0047  * @type:       type/ID
0048  * @size:       size of the @value array in bytes
0049  * @value:      value for the given type
0050  */
0051 struct sof_ipc4_tuple {
0052     uint32_t type;
0053     uint32_t size;
0054     uint32_t value[];
0055 } __packed;
0056
0057 /*
0058  * IPC4 messages have two 32 bit identifier made up as follows :-
0059  *
0060  * header - msg type, msg id, msg direction ...
0061  * extension - extra params such as msg data size in mailbox
0062  *
0063  * These are sent at the start of the IPC message in the mailbox. Messages
0064  * should not be sent in the doorbell (special exceptions for firmware).
0065  */
0066
0067 /*
0068  * IPC4 primary header bit allocation for messages
0069  * bit 0-23:    message type specific
0070  * bit 24-28:   type:   enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
0071  *          enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
0072  * bit 29:  response - sof_ipc4_msg_dir
0073  * bit 30:  target - enum sof_ipc4_msg_target
0074  * bit 31:  reserved, unused
0075  */
0076
0077 /* Value of target field - must fit into 1 bit */
0078 enum sof_ipc4_msg_target {
0079     /* Global FW message */
0080     SOF_IPC4_FW_GEN_MSG,
0081
0082     /* Module message */
0083     SOF_IPC4_MODULE_MSG
0084 };
0085
0086 /* Value of type field - must fit into 5 bits */
0087 enum sof_ipc4_global_msg {
0088     SOF_IPC4_GLB_BOOT_CONFIG,
0089     SOF_IPC4_GLB_ROM_CONTROL,
0090     SOF_IPC4_GLB_IPCGATEWAY_CMD,
0091
0092     /* 3 .. 12: RESERVED - do not use */
0093
0094     SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13,
0095     SOF_IPC4_GLB_CHAIN_DMA,
0096
0097     SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES,
0098     SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES,
0099
0100     /* pipeline settings */
0101     SOF_IPC4_GLB_CREATE_PIPELINE,
0102     SOF_IPC4_GLB_DELETE_PIPELINE,
0103     SOF_IPC4_GLB_SET_PIPELINE_STATE,
0104     SOF_IPC4_GLB_GET_PIPELINE_STATE,
0105     SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE,
0106     SOF_IPC4_GLB_SAVE_PIPELINE,
0107     SOF_IPC4_GLB_RESTORE_PIPELINE,
0108
0109     /* Loads library (using Code Load or HD/A Host Output DMA) */
0110     SOF_IPC4_GLB_LOAD_LIBRARY,
0111
0112     /* 25: RESERVED - do not use */
0113
0114     SOF_IPC4_GLB_INTERNAL_MESSAGE = 26,
0115
0116     /* Notification (FW to SW driver) */
0117     SOF_IPC4_GLB_NOTIFICATION,
0118
0119     /* 28 .. 31: RESERVED - do not use */
0120
0121     SOF_IPC4_GLB_TYPE_LAST,
0122 };
0123
0124 /* Value of response field - must fit into 1 bit */
0125 enum sof_ipc4_msg_dir {
0126     SOF_IPC4_MSG_REQUEST,
0127     SOF_IPC4_MSG_REPLY,
0128 };
0129
0130 enum sof_ipc4_pipeline_state {
0131     SOF_IPC4_PIPE_INVALID_STATE,
0132     SOF_IPC4_PIPE_UNINITIALIZED,
0133     SOF_IPC4_PIPE_RESET,
0134     SOF_IPC4_PIPE_PAUSED,
0135     SOF_IPC4_PIPE_RUNNING,
0136     SOF_IPC4_PIPE_EOS
0137 };
0138
0139 /* Generic message fields (bit 24-30) */
0140
0141 /* encoded to header's msg_tgt field */
0142 #define SOF_IPC4_MSG_TARGET_SHIFT       30
0143 #define SOF_IPC4_MSG_TARGET_MASK        BIT(30)
0144 #define SOF_IPC4_MSG_TARGET(x)          ((x) << SOF_IPC4_MSG_TARGET_SHIFT)
0145 #define SOF_IPC4_MSG_IS_MODULE_MSG(x)       ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0)
0146
0147 /* encoded to header's rsp field */
0148 #define SOF_IPC4_MSG_DIR_SHIFT          29
0149 #define SOF_IPC4_MSG_DIR_MASK           BIT(29)
0150 #define SOF_IPC4_MSG_DIR(x)         ((x) << SOF_IPC4_MSG_DIR_SHIFT)
0151
0152 /* encoded to header's type field */
0153 #define SOF_IPC4_MSG_TYPE_SHIFT         24
0154 #define SOF_IPC4_MSG_TYPE_MASK          GENMASK(28, 24)
0155 #define SOF_IPC4_MSG_TYPE_SET(x)        (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \
0156                          SOF_IPC4_MSG_TYPE_MASK)
0157 #define SOF_IPC4_MSG_TYPE_GET(x)        (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \
0158                          SOF_IPC4_MSG_TYPE_SHIFT)
0159
0160 /* Global message type specific field definitions */
0161
0162 /* pipeline creation ipc msg */
0163 #define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT    16
0164 #define SOF_IPC4_GLB_PIPE_INSTANCE_MASK     GENMASK(23, 16)
0165 #define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x)    ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT)
0166
0167 #define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT    11
0168 #define SOF_IPC4_GLB_PIPE_PRIORITY_MASK     GENMASK(15, 11)
0169 #define SOF_IPC4_GLB_PIPE_PRIORITY(x)       ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT)
0170
0171 #define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT    0
0172 #define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK     GENMASK(10, 0)
0173 #define SOF_IPC4_GLB_PIPE_MEM_SIZE(x)       ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT)
0174
0175 #define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT      0
0176 #define SOF_IPC4_GLB_PIPE_EXT_LP_MASK       BIT(0)
0177 #define SOF_IPC4_GLB_PIPE_EXT_LP(x)     ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT)
0178
0179 /* pipeline set state ipc msg */
0180 #define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT        16
0181 #define SOF_IPC4_GLB_PIPE_STATE_ID_MASK     GENMASK(23, 16)
0182 #define SOF_IPC4_GLB_PIPE_STATE_ID(x)       ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT)
0183
0184 #define SOF_IPC4_GLB_PIPE_STATE_SHIFT       0
0185 #define SOF_IPC4_GLB_PIPE_STATE_MASK        GENMASK(15, 0)
0186 #define SOF_IPC4_GLB_PIPE_STATE(x)      ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT)
0187
0188 enum sof_ipc4_channel_config {
0189     /* one channel only. */
0190     SOF_IPC4_CHANNEL_CONFIG_MONO,
0191     /* L & R. */
0192     SOF_IPC4_CHANNEL_CONFIG_STEREO,
0193     /* L, R & LFE; PCM only. */
0194     SOF_IPC4_CHANNEL_CONFIG_2_POINT_1,
0195     /* L, C & R; MP3 & AAC only. */
0196     SOF_IPC4_CHANNEL_CONFIG_3_POINT_0,
0197     /* L, C, R & LFE; PCM only. */
0198     SOF_IPC4_CHANNEL_CONFIG_3_POINT_1,
0199     /* L, R, Ls & Rs; PCM only. */
0200     SOF_IPC4_CHANNEL_CONFIG_QUATRO,
0201     /* L, C, R & Cs; MP3 & AAC only. */
0202     SOF_IPC4_CHANNEL_CONFIG_4_POINT_0,
0203     /* L, C, R, Ls & Rs. */
0204     SOF_IPC4_CHANNEL_CONFIG_5_POINT_0,
0205     /* L, C, R, Ls, Rs & LFE. */
0206     SOF_IPC4_CHANNEL_CONFIG_5_POINT_1,
0207     /* one channel replicated in two. */
0208     SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO,
0209     /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */
0210     SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0,
0211     /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */
0212     SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1,
0213     /* L, C, R, Ls, Rs & LFE., LS, RS */
0214     SOF_IPC4_CHANNEL_CONFIG_7_POINT_1,
0215 };
0216
0217 enum sof_ipc4_interleaved_style {
0218     SOF_IPC4_CHANNELS_INTERLEAVED,
0219     SOF_IPC4_CHANNELS_NONINTERLEAVED,
0220 };
0221
0222 enum sof_ipc4_sample_type {
0223     SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */
0224     SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */
0225 };
0226
0227 struct sof_ipc4_audio_format {
0228     uint32_t sampling_frequency;
0229     uint32_t bit_depth;
0230     uint32_t ch_map;
0231     uint32_t ch_cfg; /* sof_ipc4_channel_config */
0232     uint32_t interleaving_style;
0233     uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */
0234 } __packed __aligned(4);
0235
0236 #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT  0
0237 #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK   GENMASK(7, 0)
0238 #define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \
0239     ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK)
0240 #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8
0241 #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK  GENMASK(15, 8)
0242 #define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x)    \
0243     (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \
0244      SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT)
0245 #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16
0246 #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK  GENMASK(23, 16)
0247 #define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x)    \
0248     (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >>  \
0249      SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT)
0250
0251 /* Module message type specific field definitions */
0252
0253 enum sof_ipc4_module_type {
0254     SOF_IPC4_MOD_INIT_INSTANCE,
0255     SOF_IPC4_MOD_CONFIG_GET,
0256     SOF_IPC4_MOD_CONFIG_SET,
0257     SOF_IPC4_MOD_LARGE_CONFIG_GET,
0258     SOF_IPC4_MOD_LARGE_CONFIG_SET,
0259     SOF_IPC4_MOD_BIND,
0260     SOF_IPC4_MOD_UNBIND,
0261     SOF_IPC4_MOD_SET_DX,
0262     SOF_IPC4_MOD_SET_D0IX,
0263     SOF_IPC4_MOD_ENTER_MODULE_RESTORE,
0264     SOF_IPC4_MOD_EXIT_MODULE_RESTORE,
0265     SOF_IPC4_MOD_DELETE_INSTANCE,
0266
0267     SOF_IPC4_MOD_TYPE_LAST,
0268 };
0269
0270 struct sof_ipc4_base_module_cfg {
0271     uint32_t cpc; /* the max count of Cycles Per Chunk processing */
0272     uint32_t ibs; /* input Buffer Size (in bytes)  */
0273     uint32_t obs; /* output Buffer Size (in bytes) */
0274     uint32_t is_pages; /* number of physical pages used */
0275     struct sof_ipc4_audio_format audio_fmt;
0276 } __packed __aligned(4);
0277
0278 /* common module ipc msg */
0279 #define SOF_IPC4_MOD_INSTANCE_SHIFT     16
0280 #define SOF_IPC4_MOD_INSTANCE_MASK      GENMASK(23, 16)
0281 #define SOF_IPC4_MOD_INSTANCE(x)        ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT)
0282
0283 #define SOF_IPC4_MOD_ID_SHIFT           0
0284 #define SOF_IPC4_MOD_ID_MASK            GENMASK(15, 0)
0285 #define SOF_IPC4_MOD_ID(x)          ((x) << SOF_IPC4_MOD_ID_SHIFT)
0286
0287 /* init module ipc msg */
0288 #define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT   0
0289 #define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK    GENMASK(15, 0)
0290 #define SOF_IPC4_MOD_EXT_PARAM_SIZE(x)      ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT)
0291
0292 #define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT       16
0293 #define SOF_IPC4_MOD_EXT_PPL_ID_MASK        GENMASK(23, 16)
0294 #define SOF_IPC4_MOD_EXT_PPL_ID(x)      ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT)
0295
0296 #define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT      24
0297 #define SOF_IPC4_MOD_EXT_CORE_ID_MASK       GENMASK(27, 24)
0298 #define SOF_IPC4_MOD_EXT_CORE_ID(x)     ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT)
0299
0300 #define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT       28
0301 #define SOF_IPC4_MOD_EXT_DOMAIN_MASK        BIT(28)
0302 #define SOF_IPC4_MOD_EXT_DOMAIN(x)      ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT)
0303
0304 /*  bind/unbind module ipc msg */
0305 #define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT   0
0306 #define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK    GENMASK(15, 0)
0307 #define SOF_IPC4_MOD_EXT_DST_MOD_ID(x)      ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT)
0308
0309 #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16
0310 #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK  GENMASK(23, 16)
0311 #define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x)    ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT)
0312
0313 #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24
0314 #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK  GENMASK(26, 24)
0315 #define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x)    ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT)
0316
0317 #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27
0318 #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK  GENMASK(29, 27)
0319 #define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x)    ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT)
0320
0321 #define MOD_ENABLE_LOG  6
0322 #define MOD_SYSTEM_TIME 20
0323
0324 /* set module large config */
0325 #define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT     0
0326 #define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK      GENMASK(19, 0)
0327 #define SOF_IPC4_MOD_EXT_MSG_SIZE(x)        ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT)
0328
0329 #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20
0330 #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK  GENMASK(27, 20)
0331 #define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x)    ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT)
0332
0333 #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT   28
0334 #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK    BIT(28)
0335 #define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x)  ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT)
0336
0337 #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT  29
0338 #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK   BIT(29)
0339 #define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT)
0340
0341 /* Init instance messagees */
0342 #define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID     0
0343 #define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID    0
0344
0345 enum sof_ipc4_base_fw_params {
0346     SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6,
0347     SOF_IPC4_FW_PARAM_FW_CONFIG,
0348     SOF_IPC4_FW_PARAM_HW_CONFIG_GET,
0349     SOF_IPC4_FW_PARAM_MODULES_INFO_GET,
0350     SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16,
0351     SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20,
0352 };
0353
0354 enum sof_ipc4_fw_config_params {
0355     SOF_IPC4_FW_CFG_FW_VERSION,
0356     SOF_IPC4_FW_CFG_MEMORY_RECLAIMED,
0357     SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ,
0358     SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ,
0359     SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG,
0360     SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL,
0361     SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES,
0362     SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES,
0363     SOF_IPC4_FW_CFG_TRACE_LOG_BYTES,
0364     SOF_IPC4_FW_CFG_MAX_PPL_COUNT,
0365     SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT,
0366     SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT,
0367     SOF_IPC4_FW_CFG_MODULES_COUNT,
0368     SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT,
0369     SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT,
0370     SOF_IPC4_FW_CFG_LL_PRI_COUNT,
0371     SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT,
0372     SOF_IPC4_FW_CFG_MAX_LIBS_COUNT,
0373     SOF_IPC4_FW_CFG_SCHEDULER_CONFIG,
0374     SOF_IPC4_FW_CFG_XTAL_FREQ_HZ,
0375     SOF_IPC4_FW_CFG_CLOCKS_CONFIG,
0376     SOF_IPC4_FW_CFG_RESERVED,
0377     SOF_IPC4_FW_CFG_POWER_GATING_POLICY,
0378     SOF_IPC4_FW_CFG_ASSERT_MODE,
0379 };
0380
0381 struct sof_ipc4_fw_version {
0382     uint16_t major;
0383     uint16_t minor;
0384     uint16_t hotfix;
0385     uint16_t build;
0386 } __packed;
0387
0388 /* Payload data for SOF_IPC4_MOD_SET_DX */
0389 struct sof_ipc4_dx_state_info {
0390     /* core(s) to apply the change */
0391     uint32_t core_mask;
0392     /* core state: 0: put core_id to D3; 1: put core_id to D0 */
0393     uint32_t dx_mask;
0394 } __packed __aligned(4);
0395
0396 /* Reply messages */
0397
0398 /*
0399  * IPC4 primary header bit allocation for replies
0400  * bit 0-23:    status
0401  * bit 24-28:   type:   enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG
0402  *          enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG
0403  * bit 29:  response - sof_ipc4_msg_dir
0404  * bit 30:  target - enum sof_ipc4_msg_target
0405  * bit 31:  reserved, unused
0406  */
0407
0408 #define SOF_IPC4_REPLY_STATUS           GENMASK(23, 0)
0409
0410 /* Notification messages */
0411
0412 /*
0413  * IPC4 primary header bit allocation for notifications
0414  * bit 0-15:    notification type specific
0415  * bit 16-23:   enum sof_ipc4_notification_type
0416  * bit 24-28:   SOF_IPC4_GLB_NOTIFICATION
0417  * bit 29:  response - sof_ipc4_msg_dir
0418  * bit 30:  target - enum sof_ipc4_msg_target
0419  * bit 31:  reserved, unused
0420  */
0421
0422 #define SOF_IPC4_MSG_IS_NOTIFICATION(x)     (SOF_IPC4_MSG_TYPE_GET(x) == \
0423                          SOF_IPC4_GLB_NOTIFICATION)
0424
0425 #define SOF_IPC4_NOTIFICATION_TYPE_SHIFT    16
0426 #define SOF_IPC4_NOTIFICATION_TYPE_MASK     GENMASK(23, 16)
0427 #define SOF_IPC4_NOTIFICATION_TYPE_GET(x)   (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \
0428                          SOF_IPC4_NOTIFICATION_TYPE_SHIFT)
0429
0430 /* Value of notification type field - must fit into 8 bits */
0431 enum sof_ipc4_notification_type {
0432     /* Phrase detected (notification from WoV module) */
0433     SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4,
0434     /* Event from a resource (pipeline or module instance) */
0435     SOF_IPC4_NOTIFY_RESOURCE_EVENT,
0436     /* Debug log buffer status changed */
0437     SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS,
0438     /* Timestamp captured at the link */
0439     SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED,
0440     /* FW complete initialization */
0441     SOF_IPC4_NOTIFY_FW_READY,
0442     /* Audio classifier result (ACA) */
0443     SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT,
0444     /* Exception caught by DSP FW */
0445     SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT,
0446     /* 11 is skipped by the existing cavs firmware */
0447     /* Custom module notification */
0448     SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12,
0449     /* 13 is reserved - do not use */
0450     /* Probe notify data available */
0451     SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14,
0452     /* AM module notifications */
0453     SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE,
0454
0455     SOF_IPC4_NOTIFY_TYPE_LAST,
0456 };
0457
0458 struct sof_ipc4_notify_resource_data {
0459     uint32_t resource_type;
0460     uint32_t resource_id;
0461     uint32_t event_type;
0462     uint32_t reserved;
0463     uint32_t data[6];
0464 } __packed __aligned(4);
0465
0466 /** @}*/
0467
0468 #endif