sound/sof/dai.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2018 Intel Corporation. All rights reserved.
0007  */
0008
0009 #ifndef __INCLUDE_SOUND_SOF_DAI_H__
0010 #define __INCLUDE_SOUND_SOF_DAI_H__
0011
0012 #include <sound/sof/header.h>
0013 #include <sound/sof/dai-intel.h>
0014 #include <sound/sof/dai-imx.h>
0015 #include <sound/sof/dai-amd.h>
0016 #include <sound/sof/dai-mediatek.h>
0017
0018 /*
0019  * DAI Configuration.
0020  *
0021  * Each different DAI type will have it's own structure and IPC cmd.
0022  */
0023
0024 #define SOF_DAI_FMT_I2S     1 /**< I2S mode */
0025 #define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */
0026 #define SOF_DAI_FMT_LEFT_J  3 /**< Left Justified mode */
0027 #define SOF_DAI_FMT_DSP_A   4 /**< L data MSB after FRM LRC */
0028 #define SOF_DAI_FMT_DSP_B   5 /**< L data MSB during FRM LRC */
0029 #define SOF_DAI_FMT_PDM     6 /**< Pulse density modulation */
0030
0031 #define SOF_DAI_FMT_CONT    (1 << 4) /**< continuous clock */
0032 #define SOF_DAI_FMT_GATED   (0 << 4) /**< clock is gated */
0033
0034 #define SOF_DAI_FMT_NB_NF   (0 << 8) /**< normal bit clock + frame */
0035 #define SOF_DAI_FMT_NB_IF   (2 << 8) /**< normal BCLK + inv FRM */
0036 #define SOF_DAI_FMT_IB_NF   (3 << 8) /**< invert BCLK + nor FRM */
0037 #define SOF_DAI_FMT_IB_IF   (4 << 8) /**< invert BCLK + FRM */
0038
0039 #define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */
0040 #define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */
0041 #define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */
0042 #define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */
0043
0044 /* keep old definitions for backwards compatibility */
0045 #define SOF_DAI_FMT_CBM_CFM SOF_DAI_FMT_CBP_CFP
0046 #define SOF_DAI_FMT_CBS_CFM SOF_DAI_FMT_CBC_CFP
0047 #define SOF_DAI_FMT_CBM_CFS SOF_DAI_FMT_CBP_CFC
0048 #define SOF_DAI_FMT_CBS_CFS SOF_DAI_FMT_CBC_CFC
0049
0050 #define SOF_DAI_FMT_FORMAT_MASK     0x000f
0051 #define SOF_DAI_FMT_CLOCK_MASK      0x00f0
0052 #define SOF_DAI_FMT_INV_MASK        0x0f00
0053 #define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000
0054
0055 /*
0056  * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE
0057  * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above
0058  * commands.
0059  */
0060 #define SOF_DAI_CONFIG_FLAGS_CMD_MASK   0xF
0061 #define SOF_DAI_CONFIG_FLAGS_NONE   0 /**< DAI_CONFIG sent without stage information */
0062 #define SOF_DAI_CONFIG_FLAGS_HW_PARAMS  BIT(0) /**< DAI_CONFIG sent during hw_params stage */
0063 #define SOF_DAI_CONFIG_FLAGS_HW_FREE    BIT(1) /**< DAI_CONFIG sent during hw_free stage */
0064 /**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */
0065 #define SOF_DAI_CONFIG_FLAGS_PAUSE  BIT(2)
0066 #define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4
0067 #define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK  (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT)
0068 /*
0069  * This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline
0070  * stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available
0071  * ABI 3.20 onwards.
0072  */
0073 #define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0)
0074
0075 /** \brief Types of DAI */
0076 enum sof_ipc_dai_type {
0077     SOF_DAI_INTEL_NONE = 0,     /**< None */
0078     SOF_DAI_INTEL_SSP,      /**< Intel SSP */
0079     SOF_DAI_INTEL_DMIC,     /**< Intel DMIC */
0080     SOF_DAI_INTEL_HDA,      /**< Intel HD/A */
0081     SOF_DAI_INTEL_ALH,      /**< Intel ALH  */
0082     SOF_DAI_IMX_SAI,        /**< i.MX SAI */
0083     SOF_DAI_IMX_ESAI,       /**< i.MX ESAI */
0084     SOF_DAI_AMD_BT,         /**< AMD ACP BT*/
0085     SOF_DAI_AMD_SP,         /**< AMD ACP SP */
0086     SOF_DAI_AMD_DMIC,       /**< AMD ACP DMIC */
0087     SOF_DAI_MEDIATEK_AFE,       /**< Mediatek AFE */
0088 };
0089
0090 /* general purpose DAI configuration */
0091 struct sof_ipc_dai_config {
0092     struct sof_ipc_cmd_hdr hdr;
0093     uint32_t type;      /**< DAI type - enum sof_ipc_dai_type */
0094     uint32_t dai_index; /**< index of this type dai */
0095
0096     /* physical protocol and clocking */
0097     uint16_t format;    /**< SOF_DAI_FMT_ */
0098     uint8_t group_id;   /**< group ID, 0 means no group (ABI 3.17) */
0099     uint8_t flags;      /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */
0100
0101     /* reserved for future use */
0102     uint32_t reserved[8];
0103
0104     /* HW specific data */
0105     union {
0106         struct sof_ipc_dai_ssp_params ssp;
0107         struct sof_ipc_dai_dmic_params dmic;
0108         struct sof_ipc_dai_hda_params hda;
0109         struct sof_ipc_dai_alh_params alh;
0110         struct sof_ipc_dai_esai_params esai;
0111         struct sof_ipc_dai_sai_params sai;
0112         struct sof_ipc_dai_acp_params acpbt;
0113         struct sof_ipc_dai_acp_params acpsp;
0114         struct sof_ipc_dai_acpdmic_params acpdmic;
0115         struct sof_ipc_dai_mtk_afe_params afe;
0116     };
0117 } __packed;
0118
0119 struct sof_dai_private_data {
0120     struct sof_ipc_comp_dai *comp_dai;
0121     struct sof_ipc_dai_config *dai_config;
0122 };
0123
0124 #endif