sound/sof/dai-intel.h

0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * This file is provided under a dual BSD/GPLv2 license.  When using or
0004  * redistributing this file, you may do so under either license.
0005  *
0006  * Copyright(c) 2018 Intel Corporation. All rights reserved.
0007  */
0008
0009 #ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__
0010 #define __INCLUDE_SOUND_SOF_DAI_INTEL_H__
0011
0012 #include <sound/sof/header.h>
0013
0014  /* ssc1: TINTE */
0015 #define SOF_DAI_INTEL_SSP_QUIRK_TINTE       (1 << 0)
0016  /* ssc1: PINTE */
0017 #define SOF_DAI_INTEL_SSP_QUIRK_PINTE       (1 << 1)
0018  /* ssc2: SMTATF */
0019 #define SOF_DAI_INTEL_SSP_QUIRK_SMTATF      (1 << 2)
0020  /* ssc2: MMRATF */
0021 #define SOF_DAI_INTEL_SSP_QUIRK_MMRATF      (1 << 3)
0022  /* ssc2: PSPSTWFDFD */
0023 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD  (1 << 4)
0024  /* ssc2: PSPSRWFDFD */
0025 #define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD  (1 << 5)
0026 /* ssc1: LBM */
0027 #define SOF_DAI_INTEL_SSP_QUIRK_LBM     (1 << 6)
0028
0029  /* here is the possibility to define others aux macros */
0030
0031 #define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX     38
0032 #define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX      31
0033
0034 /* SSP clocks control settings
0035  *
0036  * Macros for clks_control field in sof_ipc_dai_ssp_params struct.
0037  */
0038
0039 /* mclk 0 disable */
0040 #define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE        BIT(0)
0041 /* mclk 1 disable */
0042 #define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE        BIT(1)
0043 /* mclk keep active */
0044 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA       BIT(2)
0045 /* bclk keep active */
0046 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA       BIT(3)
0047 /* fs keep active */
0048 #define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA         BIT(4)
0049 /* bclk idle */
0050 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH    BIT(5)
0051 /* mclk early start */
0052 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES               BIT(6)
0053 /* bclk early start */
0054 #define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES               BIT(7)
0055 /* mclk always on */
0056 #define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON      BIT(8)
0057
0058 /* DMIC max. four controllers for eight microphone channels */
0059 #define SOF_DAI_INTEL_DMIC_NUM_CTRL         4
0060
0061 /* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */
0062 struct sof_ipc_dai_ssp_params {
0063     struct sof_ipc_hdr hdr;
0064     uint16_t reserved1;
0065     uint16_t mclk_id;
0066
0067     uint32_t mclk_rate; /* mclk frequency in Hz */
0068     uint32_t fsync_rate;    /* fsync frequency in Hz */
0069     uint32_t bclk_rate; /* bclk frequency in Hz */
0070
0071     /* TDM */
0072     uint32_t tdm_slots;
0073     uint32_t rx_slots;
0074     uint32_t tx_slots;
0075
0076     /* data */
0077     uint32_t sample_valid_bits;
0078     uint16_t tdm_slot_width;
0079     uint16_t reserved2; /* alignment */
0080
0081     /* MCLK */
0082     uint32_t mclk_direction;
0083
0084     uint16_t frame_pulse_width;
0085     uint16_t tdm_per_slot_padding_flag;
0086     uint32_t clks_control;
0087     uint32_t quirks;
0088     uint32_t bclk_delay;    /* guaranteed time (ms) for which BCLK
0089                  * will be driven, before sending data
0090                  */
0091 } __packed;
0092
0093 /* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */
0094 struct sof_ipc_dai_hda_params {
0095     struct sof_ipc_hdr hdr;
0096     uint32_t link_dma_ch;
0097     uint32_t rate;
0098     uint32_t channels;
0099 } __packed;
0100
0101 /* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */
0102 struct sof_ipc_dai_alh_params {
0103     struct sof_ipc_hdr hdr;
0104     uint32_t stream_id;
0105     uint32_t rate;
0106     uint32_t channels;
0107
0108     /* reserved for future use */
0109     uint32_t reserved[13];
0110 } __packed;
0111
0112 /* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */
0113
0114 /* This struct is defined per 2ch PDM controller available in the platform.
0115  * Normally it is sufficient to set the used microphone specific enables to 1
0116  * and keep other parameters as zero. The customizations are:
0117  *
0118  * 1. If a device mixes different microphones types with different polarity
0119  * and/or the absolute polarity matters the PCM signal from a microphone
0120  * can be inverted with the controls.
0121  *
0122  * 2. If the microphones in a stereo pair do not appear in captured stream
0123  * in desired order due to board schematics choises they can be swapped with
0124  * the clk_edge parameter.
0125  *
0126  * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter
0127  * that delays the sampling time of data by half cycles of DMIC source clock
0128  * can be tried for improvement. However there is no guarantee for this to fix
0129  * data integrity problems.
0130  */
0131 struct sof_ipc_dai_dmic_pdm_ctrl {
0132     struct sof_ipc_hdr hdr;
0133     uint16_t id;        /**< PDM controller ID */
0134
0135     uint16_t enable_mic_a;  /**< Use A (left) channel mic (0 or 1)*/
0136     uint16_t enable_mic_b;  /**< Use B (right) channel mic (0 or 1)*/
0137
0138     uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */
0139     uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */
0140
0141     uint16_t clk_edge;  /**< Optionally swap data clock edge (0 or 1) */
0142     uint16_t skew;      /**< Adjust PDM data sampling vs. clock (0..15) */
0143
0144     uint16_t reserved[3];   /**< Make sure the total size is 4 bytes aligned */
0145 } __packed;
0146
0147 /* This struct contains the global settings for all 2ch PDM controllers. The
0148  * version number used in configuration data is checked vs. version used by
0149  * device driver src/drivers/dmic.c need to match. It is incremented from
0150  * initial value 1 if updates done for the to driver would alter the operation
0151  * of the microphone.
0152  *
0153  * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max)
0154  * parameters need to be set as defined in microphone data sheet. E.g. clock
0155  * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are
0156  * multi-mode capable and there may be denied mic clock frequencies between
0157  * the modes. In such case set the clock range limits of the desired mode to
0158  * avoid the driver to set clock to an illegal rate.
0159  *
0160  * The duty cycle could be set to 48-52% if not known. Generally these
0161  * parameters can be altered within data sheet specified limits to match
0162  * required audio application performance power.
0163  *
0164  * The microphone clock needs to be usually about 50-80 times the used audio
0165  * sample rate. With highest sample rates above 48 kHz this can relaxed
0166  * somewhat.
0167  *
0168  * The parameter wake_up_time describes how long time the microphone needs
0169  * for the data line to produce valid output from mic clock start. The driver
0170  * will mute the captured audio for the given time. The min_clock_on_time
0171  * parameter is used to prevent too short clock bursts to happen. The driver
0172  * will keep the clock active after capture stop if this time is not yet
0173  * met. The unit for both is microseconds (us). Exceed of 100 ms will be
0174  * treated as an error.
0175  */
0176 struct sof_ipc_dai_dmic_params {
0177     struct sof_ipc_hdr hdr;
0178     uint32_t driver_ipc_version;    /**< Version (1..N) */
0179
0180     uint32_t pdmclk_min;    /**< Minimum microphone clock in Hz (100000..N) */
0181     uint32_t pdmclk_max;    /**< Maximum microphone clock in Hz (min...N) */
0182
0183     uint32_t fifo_fs;   /**< FIFO sample rate in Hz (8000..96000) */
0184     uint32_t reserved_1;    /**< Reserved */
0185     uint16_t fifo_bits; /**< FIFO word length (16 or 32) */
0186     uint16_t fifo_bits_b;   /**< Deprecated since firmware ABI 3.0.1 */
0187
0188     uint16_t duty_min;  /**< Min. mic clock duty cycle in % (20..80) */
0189     uint16_t duty_max;  /**< Max. mic clock duty cycle in % (min..80) */
0190
0191     uint32_t num_pdm_active; /**< Number of active pdm controllers. */
0192                  /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */
0193
0194     uint32_t wake_up_time;      /**< Time from clock start to data (us) */
0195     uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */
0196     uint32_t unmute_ramp_time;  /**< Length of logarithmic gain ramp (ms) */
0197
0198     /* reserved for future use */
0199     uint32_t reserved[5];
0200
0201     /**< PDM controllers configuration */
0202     struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL];
0203 } __packed;
0204
0205 #endif