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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
0002 /*
0003  * Copyright 2019 NXP
0004  *
0005  * Author: Daniel Baluta <daniel.baluta@nxp.com>
0006  */
0007 
0008 #ifndef __INCLUDE_SOUND_SOF_DAI_IMX_H__
0009 #define __INCLUDE_SOUND_SOF_DAI_IMX_H__
0010 
0011 #include <sound/sof/header.h>
0012 
0013 /* ESAI Configuration Request - SOF_IPC_DAI_ESAI_CONFIG */
0014 struct sof_ipc_dai_esai_params {
0015     struct sof_ipc_hdr hdr;
0016 
0017     /* MCLK */
0018     uint16_t reserved1;
0019     uint16_t mclk_id;
0020     uint32_t mclk_direction;
0021 
0022     uint32_t mclk_rate; /* MCLK frequency in Hz */
0023     uint32_t fsync_rate;    /* FSYNC frequency in Hz */
0024     uint32_t bclk_rate; /* BCLK frequency in Hz */
0025 
0026     /* TDM */
0027     uint32_t tdm_slots;
0028     uint32_t rx_slots;
0029     uint32_t tx_slots;
0030     uint16_t tdm_slot_width;
0031     uint16_t reserved2; /* alignment */
0032 } __packed;
0033 
0034 /* SAI Configuration Request - SOF_IPC_DAI_SAI_CONFIG */
0035 struct sof_ipc_dai_sai_params {
0036     struct sof_ipc_hdr hdr;
0037 
0038     /* MCLK */
0039     uint16_t reserved1;
0040     uint16_t mclk_id;
0041     uint32_t mclk_direction;
0042 
0043     uint32_t mclk_rate; /* MCLK frequency in Hz */
0044     uint32_t fsync_rate;    /* FSYNC frequency in Hz */
0045     uint32_t bclk_rate; /* BCLK frequency in Hz */
0046 
0047     /* TDM */
0048     uint32_t tdm_slots;
0049     uint32_t rx_slots;
0050     uint32_t tx_slots;
0051     uint16_t tdm_slot_width;
0052     uint16_t reserved2; /* alignment */
0053 } __packed;
0054 #endif