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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * HD-audio core stuff
0004  */
0005 
0006 #ifndef __SOUND_HDAUDIO_H
0007 #define __SOUND_HDAUDIO_H
0008 
0009 #include <linux/device.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/io.h>
0012 #include <linux/io-64-nonatomic-lo-hi.h>
0013 #include <linux/pm_runtime.h>
0014 #include <linux/timecounter.h>
0015 #include <sound/core.h>
0016 #include <sound/pcm.h>
0017 #include <sound/memalloc.h>
0018 #include <sound/hda_verbs.h>
0019 #include <drm/i915_component.h>
0020 
0021 /* codec node id */
0022 typedef u16 hda_nid_t;
0023 
0024 struct hdac_bus;
0025 struct hdac_stream;
0026 struct hdac_device;
0027 struct hdac_driver;
0028 struct hdac_widget_tree;
0029 struct hda_device_id;
0030 
0031 /*
0032  * exported bus type
0033  */
0034 extern struct bus_type snd_hda_bus_type;
0035 
0036 /*
0037  * generic arrays
0038  */
0039 struct snd_array {
0040     unsigned int used;
0041     unsigned int alloced;
0042     unsigned int elem_size;
0043     unsigned int alloc_align;
0044     void *list;
0045 };
0046 
0047 /*
0048  * HD-audio codec base device
0049  */
0050 struct hdac_device {
0051     struct device dev;
0052     int type;
0053     struct hdac_bus *bus;
0054     unsigned int addr;      /* codec address */
0055     struct list_head list;      /* list point for bus codec_list */
0056 
0057     hda_nid_t afg;          /* AFG node id */
0058     hda_nid_t mfg;          /* MFG node id */
0059 
0060     /* ids */
0061     unsigned int vendor_id;
0062     unsigned int subsystem_id;
0063     unsigned int revision_id;
0064     unsigned int afg_function_id;
0065     unsigned int mfg_function_id;
0066     unsigned int afg_unsol:1;
0067     unsigned int mfg_unsol:1;
0068 
0069     unsigned int power_caps;    /* FG power caps */
0070 
0071     const char *vendor_name;    /* codec vendor name */
0072     const char *chip_name;      /* codec chip name */
0073 
0074     /* verb exec op override */
0075     int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
0076              unsigned int flags, unsigned int *res);
0077 
0078     /* widgets */
0079     unsigned int num_nodes;
0080     hda_nid_t start_nid, end_nid;
0081 
0082     /* misc flags */
0083     atomic_t in_pm;     /* suspend/resume being performed */
0084 
0085     /* sysfs */
0086     struct mutex widget_lock;
0087     struct hdac_widget_tree *widgets;
0088 
0089     /* regmap */
0090     struct regmap *regmap;
0091     struct mutex regmap_lock;
0092     struct snd_array vendor_verbs;
0093     bool lazy_cache:1;  /* don't wake up for writes */
0094     bool caps_overwriting:1; /* caps overwrite being in process */
0095     bool cache_coef:1;  /* cache COEF read/write too */
0096     unsigned int registered:1; /* codec was registered */
0097 };
0098 
0099 /* device/driver type used for matching */
0100 enum {
0101     HDA_DEV_CORE,
0102     HDA_DEV_LEGACY,
0103     HDA_DEV_ASOC,
0104 };
0105 
0106 enum {
0107     SND_SKL_PCI_BIND_AUTO,  /* automatic selection based on pci class */
0108     SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */
0109     SND_SKL_PCI_BIND_ASOC   /* bind only with ASoC driver */
0110 };
0111 
0112 /* direction */
0113 enum {
0114     HDA_INPUT, HDA_OUTPUT
0115 };
0116 
0117 #define dev_to_hdac_dev(_dev)   container_of(_dev, struct hdac_device, dev)
0118 
0119 int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
0120              const char *name, unsigned int addr);
0121 void snd_hdac_device_exit(struct hdac_device *dev);
0122 int snd_hdac_device_register(struct hdac_device *codec);
0123 void snd_hdac_device_unregister(struct hdac_device *codec);
0124 int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
0125 int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size);
0126 
0127 int snd_hdac_refresh_widgets(struct hdac_device *codec);
0128 
0129 int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
0130           unsigned int verb, unsigned int parm, unsigned int *res);
0131 int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
0132             unsigned int *res);
0133 int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
0134                 int parm);
0135 int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
0136                unsigned int parm, unsigned int val);
0137 int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
0138                  hda_nid_t *conn_list, int max_conns);
0139 int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
0140                hda_nid_t *start_id);
0141 unsigned int snd_hdac_calc_stream_format(unsigned int rate,
0142                      unsigned int channels,
0143                      snd_pcm_format_t format,
0144                      unsigned int maxbps,
0145                      unsigned short spdif_ctls);
0146 int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
0147                 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
0148 bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
0149                   unsigned int format);
0150 
0151 int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
0152             int flags, unsigned int verb, unsigned int parm);
0153 int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
0154             int flags, unsigned int verb, unsigned int parm);
0155 bool snd_hdac_check_power_state(struct hdac_device *hdac,
0156         hda_nid_t nid, unsigned int target_state);
0157 unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac,
0158               hda_nid_t nid, unsigned int target_state);
0159 /**
0160  * snd_hdac_read_parm - read a codec parameter
0161  * @codec: the codec object
0162  * @nid: NID to read a parameter
0163  * @parm: parameter to read
0164  *
0165  * Returns -1 for error.  If you need to distinguish the error more
0166  * strictly, use _snd_hdac_read_parm() directly.
0167  */
0168 static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
0169                      int parm)
0170 {
0171     unsigned int val;
0172 
0173     return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
0174 }
0175 
0176 #ifdef CONFIG_PM
0177 int snd_hdac_power_up(struct hdac_device *codec);
0178 int snd_hdac_power_down(struct hdac_device *codec);
0179 int snd_hdac_power_up_pm(struct hdac_device *codec);
0180 int snd_hdac_power_down_pm(struct hdac_device *codec);
0181 int snd_hdac_keep_power_up(struct hdac_device *codec);
0182 
0183 /* call this at entering into suspend/resume callbacks in codec driver */
0184 static inline void snd_hdac_enter_pm(struct hdac_device *codec)
0185 {
0186     atomic_inc(&codec->in_pm);
0187 }
0188 
0189 /* call this at leaving from suspend/resume callbacks in codec driver */
0190 static inline void snd_hdac_leave_pm(struct hdac_device *codec)
0191 {
0192     atomic_dec(&codec->in_pm);
0193 }
0194 
0195 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec)
0196 {
0197     return atomic_read(&codec->in_pm);
0198 }
0199 
0200 static inline bool snd_hdac_is_power_on(struct hdac_device *codec)
0201 {
0202     return !pm_runtime_suspended(&codec->dev);
0203 }
0204 #else
0205 static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
0206 static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
0207 static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
0208 static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
0209 static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
0210 static inline void snd_hdac_enter_pm(struct hdac_device *codec) {}
0211 static inline void snd_hdac_leave_pm(struct hdac_device *codec) {}
0212 static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; }
0213 static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; }
0214 #endif
0215 
0216 /*
0217  * HD-audio codec base driver
0218  */
0219 struct hdac_driver {
0220     struct device_driver driver;
0221     int type;
0222     const struct hda_device_id *id_table;
0223     int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
0224     void (*unsol_event)(struct hdac_device *dev, unsigned int event);
0225 
0226     /* fields used by ext bus APIs */
0227     int (*probe)(struct hdac_device *dev);
0228     int (*remove)(struct hdac_device *dev);
0229     void (*shutdown)(struct hdac_device *dev);
0230 };
0231 
0232 #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
0233 
0234 const struct hda_device_id *
0235 hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
0236 
0237 /*
0238  * Bus verb operators
0239  */
0240 struct hdac_bus_ops {
0241     /* send a single command */
0242     int (*command)(struct hdac_bus *bus, unsigned int cmd);
0243     /* get a response from the last command */
0244     int (*get_response)(struct hdac_bus *bus, unsigned int addr,
0245                 unsigned int *res);
0246     /* notify of codec link power-up/down */
0247     void (*link_power)(struct hdac_device *hdev, bool enable);
0248 };
0249 
0250 /*
0251  * ops used for ASoC HDA codec drivers
0252  */
0253 struct hdac_ext_bus_ops {
0254     int (*hdev_attach)(struct hdac_device *hdev);
0255     int (*hdev_detach)(struct hdac_device *hdev);
0256 };
0257 
0258 #define HDA_UNSOL_QUEUE_SIZE    64
0259 #define HDA_MAX_CODECS      8   /* limit by controller side */
0260 
0261 /*
0262  * CORB/RIRB
0263  *
0264  * Each CORB entry is 4byte, RIRB is 8byte
0265  */
0266 struct hdac_rb {
0267     __le32 *buf;        /* virtual address of CORB/RIRB buffer */
0268     dma_addr_t addr;    /* physical address of CORB/RIRB buffer */
0269     unsigned short rp, wp;  /* RIRB read/write pointers */
0270     int cmds[HDA_MAX_CODECS];   /* number of pending requests */
0271     u32 res[HDA_MAX_CODECS];    /* last read value */
0272 };
0273 
0274 /*
0275  * HD-audio bus base driver
0276  *
0277  * @ppcap: pp capabilities pointer
0278  * @spbcap: SPIB capabilities pointer
0279  * @mlcap: MultiLink capabilities pointer
0280  * @gtscap: gts capabilities pointer
0281  * @drsmcap: dma resume capabilities pointer
0282  * @num_streams: streams supported
0283  * @idx: HDA link index
0284  * @hlink_list: link list of HDA links
0285  * @lock: lock for link and display power mgmt
0286  * @cmd_dma_state: state of cmd DMAs: CORB and RIRB
0287  */
0288 struct hdac_bus {
0289     struct device *dev;
0290     const struct hdac_bus_ops *ops;
0291     const struct hdac_ext_bus_ops *ext_ops;
0292 
0293     /* h/w resources */
0294     unsigned long addr;
0295     void __iomem *remap_addr;
0296     int irq;
0297 
0298     void __iomem *ppcap;
0299     void __iomem *spbcap;
0300     void __iomem *mlcap;
0301     void __iomem *gtscap;
0302     void __iomem *drsmcap;
0303 
0304     /* codec linked list */
0305     struct list_head codec_list;
0306     unsigned int num_codecs;
0307 
0308     /* link caddr -> codec */
0309     struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
0310 
0311     /* unsolicited event queue */
0312     u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
0313     unsigned int unsol_rp, unsol_wp;
0314     struct work_struct unsol_work;
0315 
0316     /* bit flags of detected codecs */
0317     unsigned long codec_mask;
0318 
0319     /* bit flags of powered codecs */
0320     unsigned long codec_powered;
0321 
0322     /* CORB/RIRB */
0323     struct hdac_rb corb;
0324     struct hdac_rb rirb;
0325     unsigned int last_cmd[HDA_MAX_CODECS];  /* last sent command */
0326     wait_queue_head_t rirb_wq;
0327 
0328     /* CORB/RIRB and position buffers */
0329     struct snd_dma_buffer rb;
0330     struct snd_dma_buffer posbuf;
0331     int dma_type;           /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */
0332 
0333     /* hdac_stream linked list */
0334     struct list_head stream_list;
0335 
0336     /* operation state */
0337     bool chip_init:1;       /* h/w initialized */
0338 
0339     /* behavior flags */
0340     bool aligned_mmio:1;        /* aligned MMIO access */
0341     bool sync_write:1;      /* sync after verb write */
0342     bool use_posbuf:1;      /* use position buffer */
0343     bool snoop:1;           /* enable snooping */
0344     bool align_bdle_4k:1;       /* BDLE align 4K boundary */
0345     bool reverse_assign:1;      /* assign devices in reverse order */
0346     bool corbrp_self_clear:1;   /* CORBRP clears itself after reset */
0347     bool polling_mode:1;
0348     bool needs_damn_long_delay:1;
0349 
0350     int poll_count;
0351 
0352     int bdl_pos_adj;        /* BDL position adjustment */
0353 
0354     /* delay time in us for dma stop */
0355     unsigned int dma_stop_delay;
0356 
0357     /* locks */
0358     spinlock_t reg_lock;
0359     struct mutex cmd_mutex;
0360     struct mutex lock;
0361 
0362     /* DRM component interface */
0363     struct drm_audio_component *audio_component;
0364     long display_power_status;
0365     unsigned long display_power_active;
0366 
0367     /* parameters required for enhanced capabilities */
0368     int num_streams;
0369     int idx;
0370 
0371     /* link management */
0372     struct list_head hlink_list;
0373     bool cmd_dma_state;
0374 
0375     /* factor used to derive STRIPE control value */
0376     unsigned int sdo_limit;
0377 };
0378 
0379 int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
0380               const struct hdac_bus_ops *ops);
0381 void snd_hdac_bus_exit(struct hdac_bus *bus);
0382 int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
0383                     unsigned int cmd, unsigned int *res);
0384 
0385 void snd_hdac_codec_link_up(struct hdac_device *codec);
0386 void snd_hdac_codec_link_down(struct hdac_device *codec);
0387 
0388 int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
0389 int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
0390                   unsigned int *res);
0391 int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
0392 
0393 bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
0394 void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
0395 void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
0396 void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
0397 void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
0398 void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
0399 int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
0400 void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable);
0401 
0402 void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
0403 int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
0404                     void (*ack)(struct hdac_bus *,
0405                         struct hdac_stream *));
0406 
0407 int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
0408 void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
0409 
0410 #ifdef CONFIG_SND_HDA_ALIGNED_MMIO
0411 unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask);
0412 void snd_hdac_aligned_write(unsigned int val, void __iomem *addr,
0413                 unsigned int mask);
0414 #define snd_hdac_aligned_mmio(bus)  (bus)->aligned_mmio
0415 #else
0416 #define snd_hdac_aligned_mmio(bus)  false
0417 #define snd_hdac_aligned_read(addr, mask)   0
0418 #define snd_hdac_aligned_write(val, addr, mask) do {} while (0)
0419 #endif
0420 
0421 static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr,
0422                        u8 val)
0423 {
0424     if (snd_hdac_aligned_mmio(bus))
0425         snd_hdac_aligned_write(val, addr, 0xff);
0426     else
0427         writeb(val, addr);
0428 }
0429 
0430 static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr,
0431                        u16 val)
0432 {
0433     if (snd_hdac_aligned_mmio(bus))
0434         snd_hdac_aligned_write(val, addr, 0xffff);
0435     else
0436         writew(val, addr);
0437 }
0438 
0439 static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr)
0440 {
0441     return snd_hdac_aligned_mmio(bus) ?
0442         snd_hdac_aligned_read(addr, 0xff) : readb(addr);
0443 }
0444 
0445 static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr)
0446 {
0447     return snd_hdac_aligned_mmio(bus) ?
0448         snd_hdac_aligned_read(addr, 0xffff) : readw(addr);
0449 }
0450 
0451 #define snd_hdac_reg_writel(bus, addr, val) writel(val, addr)
0452 #define snd_hdac_reg_readl(bus, addr)   readl(addr)
0453 #define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr)
0454 #define snd_hdac_reg_readq(bus, addr)       readq(addr)
0455 
0456 /*
0457  * macros for easy use
0458  */
0459 #define _snd_hdac_chip_writeb(chip, reg, value) \
0460     snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value)
0461 #define _snd_hdac_chip_readb(chip, reg) \
0462     snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg))
0463 #define _snd_hdac_chip_writew(chip, reg, value) \
0464     snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value)
0465 #define _snd_hdac_chip_readw(chip, reg) \
0466     snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg))
0467 #define _snd_hdac_chip_writel(chip, reg, value) \
0468     snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value)
0469 #define _snd_hdac_chip_readl(chip, reg) \
0470     snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg))
0471 
0472 /* read/write a register, pass without AZX_REG_ prefix */
0473 #define snd_hdac_chip_writel(chip, reg, value) \
0474     _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
0475 #define snd_hdac_chip_writew(chip, reg, value) \
0476     _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
0477 #define snd_hdac_chip_writeb(chip, reg, value) \
0478     _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
0479 #define snd_hdac_chip_readl(chip, reg) \
0480     _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
0481 #define snd_hdac_chip_readw(chip, reg) \
0482     _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
0483 #define snd_hdac_chip_readb(chip, reg) \
0484     _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
0485 
0486 /* update a register, pass without AZX_REG_ prefix */
0487 #define snd_hdac_chip_updatel(chip, reg, mask, val) \
0488     snd_hdac_chip_writel(chip, reg, \
0489                  (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
0490 #define snd_hdac_chip_updatew(chip, reg, mask, val) \
0491     snd_hdac_chip_writew(chip, reg, \
0492                  (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
0493 #define snd_hdac_chip_updateb(chip, reg, mask, val) \
0494     snd_hdac_chip_writeb(chip, reg, \
0495                  (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
0496 
0497 /*
0498  * HD-audio stream
0499  */
0500 struct hdac_stream {
0501     struct hdac_bus *bus;
0502     struct snd_dma_buffer bdl; /* BDL buffer */
0503     __le32 *posbuf;     /* position buffer pointer */
0504     int direction;      /* playback / capture (SNDRV_PCM_STREAM_*) */
0505 
0506     unsigned int bufsize;   /* size of the play buffer in bytes */
0507     unsigned int period_bytes; /* size of the period in bytes */
0508     unsigned int frags; /* number for period in the play buffer */
0509     unsigned int fifo_size; /* FIFO size */
0510 
0511     void __iomem *sd_addr;  /* stream descriptor pointer */
0512 
0513     u32 sd_int_sta_mask;    /* stream int status mask */
0514 
0515     /* pcm support */
0516     struct snd_pcm_substream *substream;    /* assigned substream,
0517                          * set in PCM open
0518                          */
0519     struct snd_compr_stream *cstream;
0520     unsigned int format_val;    /* format value to be set in the
0521                      * controller and the codec
0522                      */
0523     unsigned char stream_tag;   /* assigned stream */
0524     unsigned char index;        /* stream index */
0525     int assigned_key;       /* last device# key assigned to */
0526 
0527     bool opened:1;
0528     bool running:1;
0529     bool prepared:1;
0530     bool no_period_wakeup:1;
0531     bool locked:1;
0532     bool stripe:1;          /* apply stripe control */
0533 
0534     u64 curr_pos;
0535     /* timestamp */
0536     unsigned long start_wallclk;    /* start + minimum wallclk */
0537     unsigned long period_wallclk;   /* wallclk for period */
0538     struct timecounter  tc;
0539     struct cyclecounter cc;
0540     int delay_negative_threshold;
0541 
0542     struct list_head list;
0543 #ifdef CONFIG_SND_HDA_DSP_LOADER
0544     /* DSP access mutex */
0545     struct mutex dsp_mutex;
0546 #endif
0547 };
0548 
0549 void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
0550               int idx, int direction, int tag);
0551 struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
0552                        struct snd_pcm_substream *substream);
0553 void snd_hdac_stream_release(struct hdac_stream *azx_dev);
0554 struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
0555                     int dir, int stream_tag);
0556 
0557 int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
0558 void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
0559 int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
0560 int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
0561                 unsigned int format_val);
0562 void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start);
0563 void snd_hdac_stream_clear(struct hdac_stream *azx_dev);
0564 void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
0565 void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus);
0566 void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
0567 void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
0568                   unsigned int streams, unsigned int reg);
0569 void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
0570               unsigned int streams);
0571 void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
0572                       unsigned int streams);
0573 int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus,
0574                 struct snd_pcm_substream *substream);
0575 
0576 /*
0577  * macros for easy use
0578  */
0579 /* read/write a register, pass without AZX_REG_ prefix */
0580 #define snd_hdac_stream_writel(dev, reg, value) \
0581     snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
0582 #define snd_hdac_stream_writew(dev, reg, value) \
0583     snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
0584 #define snd_hdac_stream_writeb(dev, reg, value) \
0585     snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value)
0586 #define snd_hdac_stream_readl(dev, reg) \
0587     snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
0588 #define snd_hdac_stream_readw(dev, reg) \
0589     snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
0590 #define snd_hdac_stream_readb(dev, reg) \
0591     snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg)
0592 
0593 /* update a register, pass without AZX_REG_ prefix */
0594 #define snd_hdac_stream_updatel(dev, reg, mask, val) \
0595     snd_hdac_stream_writel(dev, reg, \
0596                    (snd_hdac_stream_readl(dev, reg) & \
0597                 ~(mask)) | (val))
0598 #define snd_hdac_stream_updatew(dev, reg, mask, val) \
0599     snd_hdac_stream_writew(dev, reg, \
0600                    (snd_hdac_stream_readw(dev, reg) & \
0601                 ~(mask)) | (val))
0602 #define snd_hdac_stream_updateb(dev, reg, mask, val) \
0603     snd_hdac_stream_writeb(dev, reg, \
0604                    (snd_hdac_stream_readb(dev, reg) & \
0605                 ~(mask)) | (val))
0606 
0607 #ifdef CONFIG_SND_HDA_DSP_LOADER
0608 /* DSP lock helpers */
0609 #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
0610 #define snd_hdac_dsp_lock(dev)      mutex_lock(&(dev)->dsp_mutex)
0611 #define snd_hdac_dsp_unlock(dev)    mutex_unlock(&(dev)->dsp_mutex)
0612 #define snd_hdac_stream_is_locked(dev)  ((dev)->locked)
0613 /* DSP loader helpers */
0614 int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
0615              unsigned int byte_size, struct snd_dma_buffer *bufp);
0616 void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
0617 void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
0618               struct snd_dma_buffer *dmab);
0619 #else /* CONFIG_SND_HDA_DSP_LOADER */
0620 #define snd_hdac_dsp_lock_init(dev) do {} while (0)
0621 #define snd_hdac_dsp_lock(dev)      do {} while (0)
0622 #define snd_hdac_dsp_unlock(dev)    do {} while (0)
0623 #define snd_hdac_stream_is_locked(dev)  0
0624 
0625 static inline int
0626 snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
0627              unsigned int byte_size, struct snd_dma_buffer *bufp)
0628 {
0629     return 0;
0630 }
0631 
0632 static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
0633 {
0634 }
0635 
0636 static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
0637                     struct snd_dma_buffer *dmab)
0638 {
0639 }
0640 #endif /* CONFIG_SND_HDA_DSP_LOADER */
0641 
0642 
0643 /*
0644  * generic array helpers
0645  */
0646 void *snd_array_new(struct snd_array *array);
0647 void snd_array_free(struct snd_array *array);
0648 static inline void snd_array_init(struct snd_array *array, unsigned int size,
0649                   unsigned int align)
0650 {
0651     array->elem_size = size;
0652     array->alloc_align = align;
0653 }
0654 
0655 static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
0656 {
0657     return array->list + idx * array->elem_size;
0658 }
0659 
0660 static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
0661 {
0662     return (unsigned long)(ptr - array->list) / array->elem_size;
0663 }
0664 
0665 /* a helper macro to iterate for each snd_array element */
0666 #define snd_array_for_each(array, idx, ptr) \
0667     for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \
0668          (ptr) = snd_array_elem(array, ++(idx)))
0669 
0670 #endif /* __SOUND_HDAUDIO_H */
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