include/sound/cs8427.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_CS8427_H
0003 #define __SOUND_CS8427_H
0004
0005 /*
0006  *  Routines for Cirrus Logic CS8427
0007  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
0008  */
0009
0010 #include <sound/i2c.h>
0011
0012 #define CS8427_BASE_ADDR    0x10    /* base I2C address */
0013
0014 #define CS8427_REG_AUTOINC  0x80    /* flag - autoincrement */
0015 #define CS8427_REG_CONTROL1 0x01
0016 #define CS8427_REG_CONTROL2 0x02
0017 #define CS8427_REG_DATAFLOW 0x03
0018 #define CS8427_REG_CLOCKSOURCE  0x04
0019 #define CS8427_REG_SERIALINPUT  0x05
0020 #define CS8427_REG_SERIALOUTPUT 0x06
0021 #define CS8427_REG_INT1STATUS   0x07
0022 #define CS8427_REG_INT2STATUS   0x08
0023 #define CS8427_REG_INT1MASK 0x09
0024 #define CS8427_REG_INT1MODEMSB  0x0a
0025 #define CS8427_REG_INT1MODELSB  0x0b
0026 #define CS8427_REG_INT2MASK 0x0c
0027 #define CS8427_REG_INT2MODEMSB  0x0d
0028 #define CS8427_REG_INT2MODELSB  0x0e
0029 #define CS8427_REG_RECVCSDATA   0x0f
0030 #define CS8427_REG_RECVERRORS   0x10
0031 #define CS8427_REG_RECVERRMASK  0x11
0032 #define CS8427_REG_CSDATABUF    0x12
0033 #define CS8427_REG_UDATABUF 0x13
0034 #define CS8427_REG_QSUBCODE 0x14    /* 0x14-0x1d (10 bytes) */
0035 #define CS8427_REG_OMCKRMCKRATIO 0x1e
0036 #define CS8427_REG_CORU_DATABUF 0x20    /* 24 byte buffer area */
0037 #define CS8427_REG_ID_AND_VER   0x7f
0038
0039 /* CS8427_REG_CONTROL1 bits */
0040 #define CS8427_SWCLK        (1<<7)  /* 0 = RMCK default, 1 = OMCK output on RMCK pin */
0041 #define CS8427_VSET     (1<<6)  /* 0 = valid PCM data, 1 = invalid PCM data */
0042 #define CS8427_MUTESAO      (1<<5)  /* mute control for the serial audio output port, 0 = disabled, 1 = enabled */
0043 #define CS8427_MUTEAES      (1<<4)  /* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */
0044 #define CS8427_INTMASK      (3<<1)  /* interrupt output pin setup mask */
0045 #define CS8427_INTACTHIGH   (0<<1)  /* active high */
0046 #define CS8427_INTACTLOW    (1<<1)  /* active low */
0047 #define CS8427_INTOPENDRAIN (2<<1)  /* open drain, active low */
0048 #define CS8427_TCBLDIR      (1<<0)  /* 0 = TCBL is an input, 1 = TCBL is an output */
0049
0050 /* CS8427_REQ_CONTROL2 bits */
0051 #define CS8427_HOLDMASK     (3<<5)  /* action when a receiver error occurs */
0052 #define CS8427_HOLDLASTSAMPLE   (0<<5)  /* hold the last valid sample */
0053 #define CS8427_HOLDZERO     (1<<5)  /* replace the current audio sample with zero (mute) */
0054 #define CS8427_HOLDNOCHANGE (2<<5)  /* do not change the received audio sample */
0055 #define CS8427_RMCKF        (1<<4)  /* 0 = 256*Fsi, 1 = 128*Fsi */
0056 #define CS8427_MMR      (1<<3)  /* AES3 receiver operation, 0 = stereo, 1 = mono */
0057 #define CS8427_MMT      (1<<2)  /* AES3 transmitter operation, 0 = stereo, 1 = mono */
0058 #define CS8427_MMTCS        (1<<1)  /* 0 = use A + B CS data, 1 = use MMTLR CS data */
0059 #define CS8427_MMTLR        (1<<0)  /* 0 = use A CS data, 1 = use B CS data */
0060
0061 /* CS8427_REG_DATAFLOW */
0062 #define CS8427_TXOFF        (1<<6)  /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */
0063 #define CS8427_AESBP        (1<<5)  /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */
0064 #define CS8427_TXDMASK      (3<<3)  /* AES3 Transmitter Data Source Mask */
0065 #define CS8427_TXDSERIAL    (1<<3)  /* TXD - serial audio input port */
0066 #define CS8427_TXAES3DRECEIVER  (2<<3)  /* TXD - AES3 receiver */
0067 #define CS8427_SPDMASK      (3<<1)  /* Serial Audio Output Port Data Source Mask */
0068 #define CS8427_SPDSERIAL    (1<<1)  /* SPD - serial audio input port */
0069 #define CS8427_SPDAES3RECEIVER  (2<<1)  /* SPD - AES3 receiver */
0070
0071 /* CS8427_REG_CLOCKSOURCE */
0072 #define CS8427_RUN      (1<<6)  /* 0 = clock off, 1 = clock on */
0073 #define CS8427_CLKMASK      (3<<4)  /* OMCK frequency mask */
0074 #define CS8427_CLK256       (0<<4)  /* 256*Fso */
0075 #define CS8427_CLK384       (1<<4)  /* 384*Fso */
0076 #define CS8427_CLK512       (2<<4)  /* 512*Fso */
0077 #define CS8427_OUTC     (1<<3)  /* Output Time Base, 0 = OMCK, 1 = recovered input clock */
0078 #define CS8427_INC      (1<<2)  /* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */
0079 #define CS8427_RXDMASK      (3<<0)  /* Recovered Input Clock Source Mask */
0080 #define CS8427_RXDILRCK     (0<<0)  /* 256*Fsi from ILRCK pin */
0081 #define CS8427_RXDAES3INPUT (1<<0)  /* 256*Fsi from AES3 input */
0082 #define CS8427_EXTCLOCKRESET    (2<<0)  /* bypass PLL, 256*Fsi clock, synchronous reset */
0083 #define CS8427_EXTCLOCK     (3<<0)  /* bypass PLL, 256*Fsi clock */
0084
0085 /* CS8427_REG_SERIALINPUT */
0086 #define CS8427_SIMS     (1<<7)  /* 0 = slave, 1 = master mode */
0087 #define CS8427_SISF     (1<<6)  /* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */
0088 #define CS8427_SIRESMASK    (3<<4)  /* Resolution of the input data for right justified formats */
0089 #define CS8427_SIRES24      (0<<4)  /* SIRES 24-bit */
0090 #define CS8427_SIRES20      (1<<4)  /* SIRES 20-bit */
0091 #define CS8427_SIRES16      (2<<4)  /* SIRES 16-bit */
0092 #define CS8427_SIJUST       (1<<3)  /* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */
0093 #define CS8427_SIDEL        (1<<2)  /* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */
0094 #define CS8427_SISPOL       (1<<1)  /* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
0095 #define CS8427_SILRPOL      (1<<0)  /* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */
0096
0097 /* CS8427_REG_SERIALOUTPUT */
0098 #define CS8427_SOMS     (1<<7)  /* 0 = slave, 1 = master mode */
0099 #define CS8427_SOSF     (1<<6)  /* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */
0100 #define CS8427_SORESMASK    (3<<4)  /* Resolution of the output data on SDOUT and AES3 output */
0101 #define CS8427_SORES24      (0<<4)  /* SIRES 24-bit */
0102 #define CS8427_SORES20      (1<<4)  /* SIRES 20-bit */
0103 #define CS8427_SORES16      (2<<4)  /* SIRES 16-bit */
0104 #define CS8427_SORESDIRECT  (2<<4)  /* SIRES direct copy from AES3 receiver */
0105 #define CS8427_SOJUST       (1<<3)  /* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */
0106 #define CS8427_SODEL        (1<<2)  /* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */
0107 #define CS8427_SOSPOL       (1<<1)  /* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */
0108 #define CS8427_SOLRPOL      (1<<0)  /* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */
0109
0110 /* CS8427_REG_INT1STATUS */
0111 #define CS8427_TSLIP        (1<<7)  /* AES3 transmitter source data slip interrupt */
0112 #define CS8427_OSLIP        (1<<6)  /* Serial audio output port data slip interrupt */
0113 #define CS8427_DETC     (1<<2)  /* D to E C-buffer transfer interrupt */
0114 #define CS8427_EFTC     (1<<1)  /* E to F C-buffer transfer interrupt */
0115 #define CS8427_RERR     (1<<0)  /* A receiver error has occurred */
0116
0117 /* CS8427_REG_INT2STATUS */
0118 #define CS8427_DETU     (1<<3)  /* D to E U-buffer transfer interrupt */
0119 #define CS8427_EFTU     (1<<2)  /* E to F U-buffer transfer interrupt */
0120 #define CS8427_QCH      (1<<1)  /* A new block of Q-subcode data is available for reading */
0121
0122 /* CS8427_REG_INT1MODEMSB && CS8427_REG_INT1MODELSB */
0123 /* bits are defined in CS8427_REG_INT1STATUS */
0124 /* CS8427_REG_INT2MODEMSB && CS8427_REG_INT2MODELSB */
0125 /* bits are defined in CS8427_REG_INT2STATUS */
0126 #define CS8427_INTMODERISINGMSB 0
0127 #define CS8427_INTMODERESINGLSB 0
0128 #define CS8427_INTMODEFALLINGMSB 0
0129 #define CS8427_INTMODEFALLINGLSB 1
0130 #define CS8427_INTMODELEVELMSB  1
0131 #define CS8427_INTMODELEVELLSB  0
0132
0133 /* CS8427_REG_RECVCSDATA */
0134 #define CS8427_AUXMASK      (15<<4) /* auxiliary data field width */
0135 #define CS8427_AUXSHIFT     4
0136 #define CS8427_PRO      (1<<3)  /* Channel status block format indicator */
0137 #define CS8427_AUDIO        (1<<2)  /* Audio indicator (0 = audio, 1 = nonaudio */
0138 #define CS8427_COPY     (1<<1)  /* 0 = copyright asserted, 1 = copyright not asserted */
0139 #define CS8427_ORIG     (1<<0)  /* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */
0140
0141 /* CS8427_REG_RECVERRORS */
0142 /* CS8427_REG_RECVERRMASK for CS8427_RERR */
0143 #define CS8427_QCRC     (1<<6)  /* Q-subcode data CRC error indicator */
0144 #define CS8427_CCRC     (1<<5)  /* Chancnel Status Block Cyclick Redundancy Check Bit */
0145 #define CS8427_UNLOCK       (1<<4)  /* PLL lock status bit */
0146 #define CS8427_V        (1<<3)  /* 0 = valid data */
0147 #define CS8427_CONF     (1<<2)  /* Confidence bit */
0148 #define CS8427_BIP      (1<<1)  /* Bi-phase error bit */
0149 #define CS8427_PAR      (1<<0)  /* Parity error */
0150
0151 /* CS8427_REG_CSDATABUF */
0152 #define CS8427_BSEL     (1<<5)  /* 0 = CS data, 1 = U data */
0153 #define CS8427_CBMR     (1<<4)  /* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */
0154 #define CS8427_DETCI        (1<<3)  /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
0155 #define CS8427_EFTCI        (1<<2)  /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
0156 #define CS8427_CAM      (1<<1)  /* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */
0157 #define CS8427_CHS      (1<<0)  /* Channel select bit, 0 = Channel A, 1 = Channel B */
0158
0159 /* CS8427_REG_UDATABUF */
0160 #define CS8427_UD       (1<<4)  /* User data pin (U) direction, 0 = input, 1 = output */
0161 #define CS8427_UBMMASK      (3<<2)  /* Operating mode of the AES3 U bit manager */
0162 #define CS8427_UBMZEROS     (0<<2)  /* transmit all zeros mode */
0163 #define CS8427_UBMBLOCK     (1<<2)  /* block mode */
0164 #define CS8427_DETUI        (1<<1)  /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
0165 #define CS8427_EFTUI        (1<<1)  /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
0166
0167 /* CS8427_REG_ID_AND_VER */
0168 #define CS8427_IDMASK       (15<<4)
0169 #define CS8427_IDSHIFT      4
0170 #define CS8427_VERMASK      (15<<0)
0171 #define CS8427_VERSHIFT     0
0172 #define CS8427_VER8427A     0x71
0173
0174 struct snd_pcm_substream;
0175
0176 int snd_cs8427_init(struct snd_i2c_bus *bus, struct snd_i2c_device *device);
0177 int snd_cs8427_create(struct snd_i2c_bus *bus, unsigned char addr,
0178               unsigned int reset_timeout, struct snd_i2c_device **r_cs8427);
0179 int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg,
0180              unsigned char val);
0181 int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427,
0182                 struct snd_pcm_substream *playback_substream,
0183                 struct snd_pcm_substream *capture_substream);
0184 int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active);
0185 int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate);
0186
0187 #endif /* __SOUND_CS8427_H */