include/sound/ak4117.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_AK4117_H
0003 #define __SOUND_AK4117_H
0004
0005 /*
0006  *  Routines for Asahi Kasei AK4117
0007  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
0008  */
0009
0010 #define AK4117_REG_PWRDN    0x00    /* power down */
0011 #define AK4117_REG_CLOCK    0x01    /* clock control */
0012 #define AK4117_REG_IO       0x02    /* input/output control */
0013 #define AK4117_REG_INT0_MASK    0x03    /* interrupt0 mask */
0014 #define AK4117_REG_INT1_MASK    0x04    /* interrupt1 mask */
0015 #define AK4117_REG_RCS0     0x05    /* receiver status 0 */
0016 #define AK4117_REG_RCS1     0x06    /* receiver status 1 */
0017 #define AK4117_REG_RCS2     0x07    /* receiver status 2 */
0018 #define AK4117_REG_RXCSB0   0x08    /* RX channel status byte 0 */
0019 #define AK4117_REG_RXCSB1   0x09    /* RX channel status byte 1 */
0020 #define AK4117_REG_RXCSB2   0x0a    /* RX channel status byte 2 */
0021 #define AK4117_REG_RXCSB3   0x0b    /* RX channel status byte 3 */
0022 #define AK4117_REG_RXCSB4   0x0c    /* RX channel status byte 4 */
0023 #define AK4117_REG_Pc0      0x0d    /* burst preamble Pc byte 0 */
0024 #define AK4117_REG_Pc1      0x0e    /* burst preamble Pc byte 1 */
0025 #define AK4117_REG_Pd0      0x0f    /* burst preamble Pd byte 0 */
0026 #define AK4117_REG_Pd1      0x10    /* burst preamble Pd byte 1 */
0027 #define AK4117_REG_QSUB_ADDR    0x11    /* Q-subcode address + control */
0028 #define AK4117_REG_QSUB_TRACK   0x12    /* Q-subcode track */
0029 #define AK4117_REG_QSUB_INDEX   0x13    /* Q-subcode index */
0030 #define AK4117_REG_QSUB_MINUTE  0x14    /* Q-subcode minute */
0031 #define AK4117_REG_QSUB_SECOND  0x15    /* Q-subcode second */
0032 #define AK4117_REG_QSUB_FRAME   0x16    /* Q-subcode frame */
0033 #define AK4117_REG_QSUB_ZERO    0x17    /* Q-subcode zero */
0034 #define AK4117_REG_QSUB_ABSMIN  0x18    /* Q-subcode absolute minute */
0035 #define AK4117_REG_QSUB_ABSSEC  0x19    /* Q-subcode absolute second */
0036 #define AK4117_REG_QSUB_ABSFRM  0x1a    /* Q-subcode absolute frame */
0037
0038 /* sizes */
0039 #define AK4117_REG_RXCSB_SIZE   ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1)
0040 #define AK4117_REG_QSUB_SIZE    ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1)
0041
0042 /* AK4117_REG_PWRDN bits */
0043 #define AK4117_EXCT     (1<<4)  /* 0 = X'tal mode, 1 = external clock mode */
0044 #define AK4117_XTL1     (1<<3)  /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
0045 #define AK4117_XTL0     (1<<2)  /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
0046 #define AK4117_XTL_11_2896M (0)
0047 #define AK4117_XTL_12_288M  AK4117_XTL0
0048 #define AK4117_XTL_24_576M  AK4117_XTL1
0049 #define AK4117_XTL_EXT      (AK4117_XTL1|AK4117_XTL0)
0050 #define AK4117_PWN      (1<<1)  /* 0 = power down, 1 = normal operation */
0051 #define AK4117_RST      (1<<0)  /* 0 = reset & initialize (except this register), 1 = normal operation */
0052
0053 /* AK4117_REQ_CLOCK bits */
0054 #define AK4117_LP       (1<<7)  /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */
0055 #define AK4117_PKCS1        (1<<6)  /* master clock frequency at PLL mode (when LP == 0) */
0056 #define AK4117_PKCS0        (1<<5)
0057 #define AK4117_PKCS_512fs   (0)
0058 #define AK4117_PKCS_256fs   AK4117_PKCS0
0059 #define AK4117_PKCS_128fs   AK4117_PKCS1
0060 #define AK4117_DIV      (1<<4)  /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */
0061 #define AK4117_XCKS1        (1<<3)  /* master clock frequency at X'tal mode */
0062 #define AK4117_XCKS0        (1<<2)
0063 #define AK4117_XCKS_128fs   (0)
0064 #define AK4117_XCKS_256fs   AK4117_XCKS0
0065 #define AK4117_XCKS_512fs   AK4117_XCKS1
0066 #define AK4117_XCKS_1024fs  (AK4117_XCKS1|AK4117_XCKS0)
0067 #define AK4117_CM1      (1<<1)  /* MCKO operation mode select */
0068 #define AK4117_CM0      (1<<0)
0069 #define AK4117_CM_PLL       (0)     /* use RX input as master clock */
0070 #define AK4117_CM_XTAL      (AK4117_CM0)    /* use X'tal as master clock */
0071 #define AK4117_CM_PLL_XTAL  (AK4117_CM1)    /* use Rx input but X'tal when PLL loses lock */
0072 #define AK4117_CM_MONITOR   (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */
0073
0074 /* AK4117_REG_IO */
0075 #define AK4117_IPS      (1<<7)  /* Input Recovery Data Select, 0 = RX0, 1 = RX1 */
0076 #define AK4117_UOUTE        (1<<6)  /* U-bit output enable to UOUT, 0 = disable, 1 = enable */
0077 #define AK4117_CS12     (1<<5)  /* channel status select, 0 = channel1, 1 = channel2 */
0078 #define AK4117_EFH2     (1<<4)  /* INT0 pin hold count select */
0079 #define AK4117_EFH1     (1<<3)
0080 #define AK4117_EFH_512LRCLK (0)
0081 #define AK4117_EFH_1024LRCLK    (AK4117_EFH1)
0082 #define AK4117_EFH_2048LRCLK    (AK4117_EFH2)
0083 #define AK4117_EFH_4096LRCLK    (AK4117_EFH1|AK4117_EFH2)
0084 #define AK4117_DIF2     (1<<2)  /* audio data format control */
0085 #define AK4117_DIF1     (1<<1)
0086 #define AK4117_DIF0     (1<<0)
0087 #define AK4117_DIF_16R      (0)             /* STDO: 16-bit, right justified */
0088 #define AK4117_DIF_18R      (AK4117_DIF0)           /* STDO: 18-bit, right justified */
0089 #define AK4117_DIF_20R      (AK4117_DIF1)           /* STDO: 20-bit, right justified */
0090 #define AK4117_DIF_24R      (AK4117_DIF1|AK4117_DIF0)   /* STDO: 24-bit, right justified */
0091 #define AK4117_DIF_24L      (AK4117_DIF2)           /* STDO: 24-bit, left justified */
0092 #define AK4117_DIF_24I2S    (AK4117_DIF2|AK4117_DIF0)   /* STDO: I2S */
0093
0094 /* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */
0095 #define AK4117_MULK     (1<<7)  /* mask enable for UNLOCK bit */
0096 #define AK4117_MPAR     (1<<6)  /* mask enable for PAR bit */
0097 #define AK4117_MAUTO        (1<<5)  /* mask enable for AUTO bit */
0098 #define AK4117_MV       (1<<4)  /* mask enable for V bit */
0099 #define AK4117_MAUD     (1<<3)  /* mask enable for AUDION bit */
0100 #define AK4117_MSTC     (1<<2)  /* mask enable for STC bit */
0101 #define AK4117_MCIT     (1<<1)  /* mask enable for CINT bit */
0102 #define AK4117_MQIT     (1<<0)  /* mask enable for QINT bit */
0103
0104 /* AK4117_REG_RCS0 */
0105 #define AK4117_UNLCK        (1<<7)  /* PLL lock status, 0 = lock, 1 = unlock */
0106 #define AK4117_PAR      (1<<6)  /* parity error or biphase error status, 0 = no error, 1 = error */
0107 #define AK4117_AUTO     (1<<5)  /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
0108 #define AK4117_V        (1<<4)  /* Validity bit, 0 = valid, 1 = invalid */
0109 #define AK4117_AUDION       (1<<3)  /* audio bit output, 0 = audio, 1 = non-audio */
0110 #define AK4117_STC      (1<<2)  /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
0111 #define AK4117_CINT     (1<<1)  /* channel status buffer interrupt, 0 = no change, 1 = change */
0112 #define AK4117_QINT     (1<<0)  /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
0113
0114 /* AK4117_REG_RCS1 */
0115 #define AK4117_DTSCD        (1<<6)  /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
0116 #define AK4117_NPCM     (1<<5)  /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
0117 #define AK4117_PEM      (1<<4)  /* Pre-emphasis detect, 0 = OFF, 1 = ON */
0118 #define AK4117_FS3      (1<<3)  /* sampling frequency detection */
0119 #define AK4117_FS2      (1<<2)
0120 #define AK4117_FS1      (1<<1)
0121 #define AK4117_FS0      (1<<0)
0122 #define AK4117_FS_44100HZ   (0)
0123 #define AK4117_FS_48000HZ   (AK4117_FS1)
0124 #define AK4117_FS_32000HZ   (AK4117_FS1|AK4117_FS0)
0125 #define AK4117_FS_88200HZ   (AK4117_FS3)
0126 #define AK4117_FS_96000HZ   (AK4117_FS3|AK4117_FS1)
0127 #define AK4117_FS_176400HZ  (AK4117_FS3|AK4117_FS2)
0128 #define AK4117_FS_192000HZ  (AK4117_FS3|AK4117_FS2|AK4117_FS1)
0129
0130 /* AK4117_REG_RCS2 */
0131 #define AK4117_CCRC     (1<<1)  /* CRC for channel status, 0 = no error, 1 = error */
0132 #define AK4117_QCRC     (1<<0)  /* CRC for Q-subcode, 0 = no error, 1 = error */
0133
0134 /* flags for snd_ak4117_check_rate_and_errors() */
0135 #define AK4117_CHECK_NO_STAT    (1<<0)  /* no statistics */
0136 #define AK4117_CHECK_NO_RATE    (1<<1)  /* no rate check */
0137
0138 #define AK4117_CONTROLS     13
0139
0140 typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data);
0141 typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr);
0142
0143 enum {
0144     AK4117_PARITY_ERRORS,
0145     AK4117_V_BIT_ERRORS,
0146     AK4117_QCRC_ERRORS,
0147     AK4117_CCRC_ERRORS,
0148     AK4117_NUM_ERRORS
0149 };
0150
0151 struct ak4117 {
0152     struct snd_card *card;
0153     ak4117_write_t * write;
0154     ak4117_read_t * read;
0155     void * private_data;
0156     unsigned int init: 1;
0157     spinlock_t lock;
0158     unsigned char regmap[5];
0159     struct snd_kcontrol *kctls[AK4117_CONTROLS];
0160     struct snd_pcm_substream *substream;
0161     unsigned long errors[AK4117_NUM_ERRORS];
0162     unsigned char rcs0;
0163     unsigned char rcs1;
0164     unsigned char rcs2;
0165     struct timer_list timer;    /* statistic timer */
0166     void *change_callback_private;
0167     void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1);
0168 };
0169
0170 int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write,
0171               const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117);
0172 void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val);
0173 void snd_ak4117_reinit(struct ak4117 *ak4117);
0174 int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream);
0175 int snd_ak4117_external_rate(struct ak4117 *ak4117);
0176 int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags);
0177
0178 #endif /* __SOUND_AK4117_H */
0179