include/sound/ak4114.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_AK4114_H
0003 #define __SOUND_AK4114_H
0004
0005 /*
0006  *  Routines for Asahi Kasei AK4114
0007  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
0008  */
0009
0010 /* AK4114 registers */
0011 #define AK4114_REG_PWRDN    0x00    /* power down */
0012 #define AK4114_REG_FORMAT   0x01    /* format control */
0013 #define AK4114_REG_IO0      0x02    /* input/output control */
0014 #define AK4114_REG_IO1      0x03    /* input/output control */
0015 #define AK4114_REG_INT0_MASK    0x04    /* interrupt0 mask */
0016 #define AK4114_REG_INT1_MASK    0x05    /* interrupt1 mask */
0017 #define AK4114_REG_RCS0     0x06    /* receiver status 0 */
0018 #define AK4114_REG_RCS1     0x07    /* receiver status 1 */
0019 #define AK4114_REG_RXCSB0   0x08    /* RX channel status byte 0 */
0020 #define AK4114_REG_RXCSB1   0x09    /* RX channel status byte 1 */
0021 #define AK4114_REG_RXCSB2   0x0a    /* RX channel status byte 2 */
0022 #define AK4114_REG_RXCSB3   0x0b    /* RX channel status byte 3 */
0023 #define AK4114_REG_RXCSB4   0x0c    /* RX channel status byte 4 */
0024 #define AK4114_REG_TXCSB0   0x0d    /* TX channel status byte 0 */
0025 #define AK4114_REG_TXCSB1   0x0e    /* TX channel status byte 1 */
0026 #define AK4114_REG_TXCSB2   0x0f    /* TX channel status byte 2 */
0027 #define AK4114_REG_TXCSB3   0x10    /* TX channel status byte 3 */
0028 #define AK4114_REG_TXCSB4   0x11    /* TX channel status byte 4 */
0029 #define AK4114_REG_Pc0      0x12    /* burst preamble Pc byte 0 */
0030 #define AK4114_REG_Pc1      0x13    /* burst preamble Pc byte 1 */
0031 #define AK4114_REG_Pd0      0x14    /* burst preamble Pd byte 0 */
0032 #define AK4114_REG_Pd1      0x15    /* burst preamble Pd byte 1 */
0033 #define AK4114_REG_QSUB_ADDR    0x16    /* Q-subcode address + control */
0034 #define AK4114_REG_QSUB_TRACK   0x17    /* Q-subcode track */
0035 #define AK4114_REG_QSUB_INDEX   0x18    /* Q-subcode index */
0036 #define AK4114_REG_QSUB_MINUTE  0x19    /* Q-subcode minute */
0037 #define AK4114_REG_QSUB_SECOND  0x1a    /* Q-subcode second */
0038 #define AK4114_REG_QSUB_FRAME   0x1b    /* Q-subcode frame */
0039 #define AK4114_REG_QSUB_ZERO    0x1c    /* Q-subcode zero */
0040 #define AK4114_REG_QSUB_ABSMIN  0x1d    /* Q-subcode absolute minute */
0041 #define AK4114_REG_QSUB_ABSSEC  0x1e    /* Q-subcode absolute second */
0042 #define AK4114_REG_QSUB_ABSFRM  0x1f    /* Q-subcode absolute frame */
0043
0044 /* sizes */
0045 #define AK4114_REG_RXCSB_SIZE   ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1)
0046 #define AK4114_REG_TXCSB_SIZE   ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1)
0047 #define AK4114_REG_QSUB_SIZE    ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1)
0048
0049 /* AK4117_REG_PWRDN bits */
0050 #define AK4114_CS12     (1<<7)  /* Channel Status Select */
0051 #define AK4114_BCU      (1<<6)  /* Block Start & C/U Output Mode */
0052 #define AK4114_CM1      (1<<5)  /* Master Clock Operation Select */
0053 #define AK4114_CM0      (1<<4)  /* Master Clock Operation Select */
0054 #define AK4114_OCKS1        (1<<3)  /* Master Clock Frequency Select */
0055 #define AK4114_OCKS0        (1<<2)  /* Master Clock Frequency Select */
0056 #define AK4114_PWN      (1<<1)  /* 0 = power down, 1 = normal operation */
0057 #define AK4114_RST      (1<<0)  /* 0 = reset & initialize (except this register), 1 = normal operation */
0058
0059 /* AK4114_REQ_FORMAT bits */
0060 #define AK4114_MONO     (1<<7)  /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */
0061 #define AK4114_DIF2     (1<<6)  /* Audio Data Control */
0062 #define AK4114_DIF1     (1<<5)  /* Audio Data Control */
0063 #define AK4114_DIF0     (1<<4)  /* Audio Data Control */
0064 #define AK4114_DIF_16R      (0)             /* STDO: 16-bit, right justified */
0065 #define AK4114_DIF_18R      (AK4114_DIF0)           /* STDO: 18-bit, right justified */
0066 #define AK4114_DIF_20R      (AK4114_DIF1)           /* STDO: 20-bit, right justified */
0067 #define AK4114_DIF_24R      (AK4114_DIF1|AK4114_DIF0)   /* STDO: 24-bit, right justified */
0068 #define AK4114_DIF_24L      (AK4114_DIF2)           /* STDO: 24-bit, left justified */
0069 #define AK4114_DIF_24I2S    (AK4114_DIF2|AK4114_DIF0)   /* STDO: I2S */
0070 #define AK4114_DIF_I24L     (AK4114_DIF2|AK4114_DIF1)   /* STDO: 24-bit, left justified; LRCLK, BICK = Input */
0071 #define AK4114_DIF_I24I2S   (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S;  LRCLK, BICK = Input */
0072 #define AK4114_DEAU     (1<<3)  /* Deemphasis Autodetect Enable (1 = enable) */
0073 #define AK4114_DEM1     (1<<2)  /* 32kHz-48kHz Deemphasis Control */
0074 #define AK4114_DEM0     (1<<1)  /* 32kHz-48kHz Deemphasis Control */
0075 #define AK4114_DEM_44KHZ    (0)
0076 #define AK4114_DEM_48KHZ    (AK4114_DEM1)
0077 #define AK4114_DEM_32KHZ    (AK4114_DEM0|AK4114_DEM1)
0078 #define AK4114_DEM_96KHZ    (AK4114_DEM1)   /* DFS must be set */
0079 #define AK4114_DFS      (1<<0)  /* 96kHz Deemphasis Control */
0080
0081 /* AK4114_REG_IO0 */
0082 #define AK4114_TX1E     (1<<7)  /* TX1 Output Enable (1 = enable) */
0083 #define AK4114_OPS12        (1<<6)  /* Output Data Selector for TX1 pin */
0084 #define AK4114_OPS11        (1<<5)  /* Output Data Selector for TX1 pin */
0085 #define AK4114_OPS10        (1<<4)  /* Output Data Selector for TX1 pin */
0086 #define AK4114_TX0E     (1<<3)  /* TX0 Output Enable (1 = enable) */
0087 #define AK4114_OPS02        (1<<2)  /* Output Data Selector for TX0 pin */
0088 #define AK4114_OPS01        (1<<1)  /* Output Data Selector for TX0 pin */
0089 #define AK4114_OPS00        (1<<0)  /* Output Data Selector for TX0 pin */
0090
0091 /* AK4114_REG_IO1 */
0092 #define AK4114_EFH1     (1<<7)  /* Interrupt 0 pin Hold */
0093 #define AK4114_EFH0     (1<<6)  /* Interrupt 0 pin Hold */
0094 #define AK4114_EFH_512      (0)
0095 #define AK4114_EFH_1024     (AK4114_EFH0)
0096 #define AK4114_EFH_2048     (AK4114_EFH1)
0097 #define AK4114_EFH_4096     (AK4114_EFH1|AK4114_EFH0)
0098 #define AK4114_UDIT     (1<<5)  /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */
0099 #define AK4114_TLR      (1<<4)  /* Double Sampling Frequency Select for DIT (0 = L channel, 1 = R channel) */
0100 #define AK4114_DIT      (1<<3)  /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */
0101 #define AK4114_IPS2     (1<<2)  /* Input Recovery Data Select */
0102 #define AK4114_IPS1     (1<<1)  /* Input Recovery Data Select */
0103 #define AK4114_IPS0     (1<<0)  /* Input Recovery Data Select */
0104 #define AK4114_IPS(x)       ((x)&7)
0105
0106 /* AK4114_REG_INT0_MASK && AK4114_REG_INT1_MASK*/
0107 #define AK4117_MQI              (1<<7)  /* mask enable for QINT bit */
0108 #define AK4117_MAT              (1<<6)  /* mask enable for AUTO bit */
0109 #define AK4117_MCI              (1<<5)  /* mask enable for CINT bit */
0110 #define AK4117_MUL              (1<<4)  /* mask enable for UNLOCK bit */
0111 #define AK4117_MDTS             (1<<3)  /* mask enable for DTSCD bit */
0112 #define AK4117_MPE              (1<<2)  /* mask enable for PEM bit */
0113 #define AK4117_MAN              (1<<1)  /* mask enable for AUDN bit */
0114 #define AK4117_MPR              (1<<0)  /* mask enable for PAR bit */
0115
0116 /* AK4114_REG_RCS0 */
0117 #define AK4114_QINT     (1<<7)  /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
0118 #define AK4114_AUTO     (1<<6)  /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
0119 #define AK4114_CINT     (1<<5)  /* channel status buffer interrupt, 0 = no change, 1 = change */
0120 #define AK4114_UNLCK        (1<<4)  /* PLL lock status, 0 = lock, 1 = unlock */
0121 #define AK4114_DTSCD        (1<<3)  /* DTS-CD Detect, 0 = No detect, 1 = Detect */
0122 #define AK4114_PEM      (1<<2)  /* Pre-emphasis Detect, 0 = OFF, 1 = ON */
0123 #define AK4114_AUDION       (1<<1)  /* audio bit output, 0 = audio, 1 = non-audio */
0124 #define AK4114_PAR      (1<<0)  /* parity error or biphase error status, 0 = no error, 1 = error */
0125
0126 /* AK4114_REG_RCS1 */
0127 #define AK4114_FS3      (1<<7)  /* sampling frequency detection */
0128 #define AK4114_FS2      (1<<6)
0129 #define AK4114_FS1      (1<<5)
0130 #define AK4114_FS0      (1<<4)
0131 #define AK4114_FS_44100HZ   (0)
0132 #define AK4114_FS_48000HZ   (AK4114_FS1)
0133 #define AK4114_FS_32000HZ   (AK4114_FS1|AK4114_FS0)
0134 #define AK4114_FS_88200HZ   (AK4114_FS3)
0135 #define AK4114_FS_96000HZ   (AK4114_FS3|AK4114_FS1)
0136 #define AK4114_FS_176400HZ  (AK4114_FS3|AK4114_FS2)
0137 #define AK4114_FS_192000HZ  (AK4114_FS3|AK4114_FS2|AK4114_FS1)
0138 #define AK4114_V        (1<<3)  /* Validity of Channel Status, 0 = Valid, 1 = Invalid */
0139 #define AK4114_QCRC     (1<<1)  /* CRC for Q-subcode, 0 = no error, 1 = error */
0140 #define AK4114_CCRC     (1<<0)  /* CRC for channel status, 0 = no error, 1 = error */
0141
0142 /* flags for snd_ak4114_check_rate_and_errors() */
0143 #define AK4114_CHECK_NO_STAT    (1<<0)  /* no statistics */
0144 #define AK4114_CHECK_NO_RATE    (1<<1)  /* no rate check */
0145
0146 #define AK4114_CONTROLS     15
0147
0148 typedef void (ak4114_write_t)(void *private_data, unsigned char addr, unsigned char data);
0149 typedef unsigned char (ak4114_read_t)(void *private_data, unsigned char addr);
0150
0151 enum {
0152     AK4114_PARITY_ERRORS,
0153     AK4114_V_BIT_ERRORS,
0154     AK4114_QCRC_ERRORS,
0155     AK4114_CCRC_ERRORS,
0156     AK4114_NUM_ERRORS
0157 };
0158
0159 struct ak4114 {
0160     struct snd_card *card;
0161     ak4114_write_t * write;
0162     ak4114_read_t * read;
0163     void * private_data;
0164     atomic_t wq_processing;
0165     struct mutex reinit_mutex;
0166     spinlock_t lock;
0167     unsigned char regmap[6];
0168     unsigned char txcsb[5];
0169     struct snd_kcontrol *kctls[AK4114_CONTROLS];
0170     struct snd_pcm_substream *playback_substream;
0171     struct snd_pcm_substream *capture_substream;
0172     unsigned long errors[AK4114_NUM_ERRORS];
0173     unsigned char rcs0;
0174     unsigned char rcs1;
0175     struct delayed_work work;
0176     unsigned int check_flags;
0177     void *change_callback_private;
0178     void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1);
0179 };
0180
0181 int snd_ak4114_create(struct snd_card *card,
0182               ak4114_read_t *read, ak4114_write_t *write,
0183               const unsigned char pgm[6], const unsigned char txcsb[5],
0184               void *private_data, struct ak4114 **r_ak4114);
0185 void snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val);
0186 void snd_ak4114_reinit(struct ak4114 *ak4114);
0187 int snd_ak4114_build(struct ak4114 *ak4114,
0188              struct snd_pcm_substream *playback_substream,
0189                      struct snd_pcm_substream *capture_substream);
0190 int snd_ak4114_external_rate(struct ak4114 *ak4114);
0191 int snd_ak4114_check_rate_and_errors(struct ak4114 *ak4114, unsigned int flags);
0192
0193 #ifdef CONFIG_PM
0194 void snd_ak4114_suspend(struct ak4114 *chip);
0195 void snd_ak4114_resume(struct ak4114 *chip);
0196 #else
0197 static inline void snd_ak4114_suspend(struct ak4114 *chip) {}
0198 static inline void snd_ak4114_resume(struct ak4114 *chip) {}
0199 #endif
0200
0201 #endif /* __SOUND_AK4114_H */
0202