include/sound/ak4113.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 #ifndef __SOUND_AK4113_H
0003 #define __SOUND_AK4113_H
0004
0005 /*
0006  *  Routines for Asahi Kasei AK4113
0007  *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
0008  *  Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>,
0009  */
0010
0011 /* AK4113 registers */
0012 /* power down */
0013 #define AK4113_REG_PWRDN    0x00
0014 /* format control */
0015 #define AK4113_REG_FORMAT   0x01
0016 /* input/output control */
0017 #define AK4113_REG_IO0      0x02
0018 /* input/output control */
0019 #define AK4113_REG_IO1      0x03
0020 /* interrupt0 mask */
0021 #define AK4113_REG_INT0_MASK    0x04
0022 /* interrupt1 mask */
0023 #define AK4113_REG_INT1_MASK    0x05
0024 /* DAT mask & DTS select */
0025 #define AK4113_REG_DATDTS   0x06
0026 /* receiver status 0 */
0027 #define AK4113_REG_RCS0     0x07
0028 /* receiver status 1 */
0029 #define AK4113_REG_RCS1     0x08
0030 /* receiver status 2 */
0031 #define AK4113_REG_RCS2     0x09
0032 /* RX channel status byte 0 */
0033 #define AK4113_REG_RXCSB0   0x0a
0034 /* RX channel status byte 1 */
0035 #define AK4113_REG_RXCSB1   0x0b
0036 /* RX channel status byte 2 */
0037 #define AK4113_REG_RXCSB2   0x0c
0038 /* RX channel status byte 3 */
0039 #define AK4113_REG_RXCSB3   0x0d
0040 /* RX channel status byte 4 */
0041 #define AK4113_REG_RXCSB4   0x0e
0042 /* burst preamble Pc byte 0 */
0043 #define AK4113_REG_Pc0      0x0f
0044 /* burst preamble Pc byte 1 */
0045 #define AK4113_REG_Pc1      0x10
0046 /* burst preamble Pd byte 0 */
0047 #define AK4113_REG_Pd0      0x11
0048 /* burst preamble Pd byte 1 */
0049 #define AK4113_REG_Pd1      0x12
0050 /* Q-subcode address + control */
0051 #define AK4113_REG_QSUB_ADDR    0x13
0052 /* Q-subcode track */
0053 #define AK4113_REG_QSUB_TRACK   0x14
0054 /* Q-subcode index */
0055 #define AK4113_REG_QSUB_INDEX   0x15
0056 /* Q-subcode minute */
0057 #define AK4113_REG_QSUB_MINUTE  0x16
0058 /* Q-subcode second */
0059 #define AK4113_REG_QSUB_SECOND  0x17
0060 /* Q-subcode frame */
0061 #define AK4113_REG_QSUB_FRAME   0x18
0062 /* Q-subcode zero */
0063 #define AK4113_REG_QSUB_ZERO    0x19
0064 /* Q-subcode absolute minute */
0065 #define AK4113_REG_QSUB_ABSMIN  0x1a
0066 /* Q-subcode absolute second */
0067 #define AK4113_REG_QSUB_ABSSEC  0x1b
0068 /* Q-subcode absolute frame */
0069 #define AK4113_REG_QSUB_ABSFRM  0x1c
0070
0071 /* sizes */
0072 #define AK4113_REG_RXCSB_SIZE   ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1)
0073 #define AK4113_REG_QSUB_SIZE    ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\
0074         +1)
0075
0076 #define AK4113_WRITABLE_REGS    (AK4113_REG_DATDTS + 1)
0077
0078 /* AK4113_REG_PWRDN bits */
0079 /* Channel Status Select */
0080 #define AK4113_CS12     (1<<7)
0081 /* Block Start & C/U Output Mode */
0082 #define AK4113_BCU      (1<<6)
0083 /* Master Clock Operation Select */
0084 #define AK4113_CM1      (1<<5)
0085 /* Master Clock Operation Select */
0086 #define AK4113_CM0      (1<<4)
0087 /* Master Clock Frequency Select */
0088 #define AK4113_OCKS1        (1<<3)
0089 /* Master Clock Frequency Select */
0090 #define AK4113_OCKS0        (1<<2)
0091 /* 0 = power down, 1 = normal operation */
0092 #define AK4113_PWN      (1<<1)
0093 /* 0 = reset & initialize (except thisregister), 1 = normal operation */
0094 #define AK4113_RST      (1<<0)
0095
0096 /* AK4113_REQ_FORMAT bits */
0097 /* V/TX Output select: 0 = Validity Flag Output, 1 = TX */
0098 #define AK4113_VTX      (1<<7)
0099 /* Audio Data Control */
0100 #define AK4113_DIF2     (1<<6)
0101 /* Audio Data Control */
0102 #define AK4113_DIF1     (1<<5)
0103 /* Audio Data Control */
0104 #define AK4113_DIF0     (1<<4)
0105 /* Deemphasis Autodetect Enable (1 = enable) */
0106 #define AK4113_DEAU     (1<<3)
0107 /* 32kHz-48kHz Deemphasis Control */
0108 #define AK4113_DEM1     (1<<2)
0109 /* 32kHz-48kHz Deemphasis Control */
0110 #define AK4113_DEM0     (1<<1)
0111 #define AK4113_DEM_OFF      (AK4113_DEM0)
0112 #define AK4113_DEM_44KHZ    (0)
0113 #define AK4113_DEM_48KHZ    (AK4113_DEM1)
0114 #define AK4113_DEM_32KHZ    (AK4113_DEM0|AK4113_DEM1)
0115 /* STDO: 16-bit, right justified */
0116 #define AK4113_DIF_16R      (0)
0117 /* STDO: 18-bit, right justified */
0118 #define AK4113_DIF_18R      (AK4113_DIF0)
0119 /* STDO: 20-bit, right justified */
0120 #define AK4113_DIF_20R      (AK4113_DIF1)
0121 /* STDO: 24-bit, right justified */
0122 #define AK4113_DIF_24R      (AK4113_DIF1|AK4113_DIF0)
0123 /* STDO: 24-bit, left justified */
0124 #define AK4113_DIF_24L      (AK4113_DIF2)
0125 /* STDO: I2S */
0126 #define AK4113_DIF_24I2S    (AK4113_DIF2|AK4113_DIF0)
0127 /* STDO: 24-bit, left justified; LRCLK, BICK = Input */
0128 #define AK4113_DIF_I24L     (AK4113_DIF2|AK4113_DIF1)
0129 /* STDO: I2S;  LRCLK, BICK = Input */
0130 #define AK4113_DIF_I24I2S   (AK4113_DIF2|AK4113_DIF1|AK4113_DIF0)
0131
0132 /* AK4113_REG_IO0 */
0133 /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */
0134 #define AK4113_XTL1     (1<<6)
0135 /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */
0136 #define AK4113_XTL0     (1<<5)
0137 /* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */
0138 #define AK4113_UCE      (1<<4)
0139 /* TX Output Enable (1 = enable) */
0140 #define AK4113_TXE      (1<<3)
0141 /* Output Through Data Selector for TX pin */
0142 #define AK4113_OPS2     (1<<2)
0143 /* Output Through Data Selector for TX pin */
0144 #define AK4113_OPS1     (1<<1)
0145 /* Output Through Data Selector for TX pin */
0146 #define AK4113_OPS0     (1<<0)
0147 /* 11.2896 MHz ref. Xtal freq. */
0148 #define AK4113_XTL_11_2896M (0)
0149 /* 12.288 MHz ref. Xtal freq. */
0150 #define AK4113_XTL_12_288M  (AK4113_XTL0)
0151 /* 24.576 MHz ref. Xtal freq. */
0152 #define AK4113_XTL_24_576M  (AK4113_XTL1)
0153
0154 /* AK4113_REG_IO1 */
0155 /* Interrupt 0 pin Hold */
0156 #define AK4113_EFH1     (1<<7)
0157 /* Interrupt 0 pin Hold */
0158 #define AK4113_EFH0     (1<<6)
0159 #define AK4113_EFH_512LRCLK (0)
0160 #define AK4113_EFH_1024LRCLK    (AK4113_EFH0)
0161 #define AK4113_EFH_2048LRCLK    (AK4113_EFH1)
0162 #define AK4113_EFH_4096LRCLK    (AK4113_EFH1|AK4113_EFH0)
0163 /* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */
0164 #define AK4113_FAST     (1<<5)
0165 /* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */
0166 #define AK4113_XMCK     (1<<4)
0167 /* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5  (req. XMCK = 1) */
0168 #define AK4113_DIV      (1<<3)
0169 /* Input Recovery Data Select */
0170 #define AK4113_IPS2     (1<<2)
0171 /* Input Recovery Data Select */
0172 #define AK4113_IPS1     (1<<1)
0173 /* Input Recovery Data Select */
0174 #define AK4113_IPS0     (1<<0)
0175 #define AK4113_IPS(x)       ((x)&7)
0176
0177 /* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/
0178 /* mask enable for QINT bit */
0179 #define AK4113_MQI      (1<<7)
0180 /* mask enable for AUTO bit */
0181 #define AK4113_MAUT     (1<<6)
0182 /* mask enable for CINT bit */
0183 #define AK4113_MCIT     (1<<5)
0184 /* mask enable for UNLOCK bit */
0185 #define AK4113_MULK     (1<<4)
0186 /* mask enable for V bit */
0187 #define AK4113_V        (1<<3)
0188 /* mask enable for STC bit */
0189 #define AK4113_STC      (1<<2)
0190 /* mask enable for AUDN bit */
0191 #define AK4113_MAN      (1<<1)
0192 /* mask enable for PAR bit */
0193 #define AK4113_MPR      (1<<0)
0194
0195 /* AK4113_REG_DATDTS */
0196 /* DAT Start ID Counter */
0197 #define AK4113_DCNT     (1<<4)
0198 /* DTS-CD 16-bit Sync Word Detect */
0199 #define AK4113_DTS16        (1<<3)
0200 /* DTS-CD 14-bit Sync Word Detect */
0201 #define AK4113_DTS14        (1<<2)
0202 /* mask enable for DAT bit (if 1, no INT1 effect */
0203 #define AK4113_MDAT1        (1<<1)
0204 /* mask enable for DAT bit (if 1, no INT0 effect */
0205 #define AK4113_MDAT0        (1<<0)
0206
0207 /* AK4113_REG_RCS0 */
0208 /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
0209 #define AK4113_QINT     (1<<7)
0210 /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
0211 #define AK4113_AUTO     (1<<6)
0212 /* channel status buffer interrupt, 0 = no change, 1 = change */
0213 #define AK4113_CINT     (1<<5)
0214 /* PLL lock status, 0 = lock, 1 = unlock */
0215 #define AK4113_UNLCK        (1<<4)
0216 /* Validity bit, 0 = valid, 1 = invalid */
0217 #define AK4113_V        (1<<3)
0218 /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */
0219 #define AK4113_STC      (1<<2)
0220 /* audio bit output, 0 = audio, 1 = non-audio */
0221 #define AK4113_AUDION       (1<<1)
0222 /* parity error or biphase error status, 0 = no error, 1 = error */
0223 #define AK4113_PAR      (1<<0)
0224
0225 /* AK4113_REG_RCS1 */
0226 /* sampling frequency detection */
0227 #define AK4113_FS3      (1<<7)
0228 #define AK4113_FS2      (1<<6)
0229 #define AK4113_FS1      (1<<5)
0230 #define AK4113_FS0      (1<<4)
0231 /* Pre-emphasis detect, 0 = OFF, 1 = ON */
0232 #define AK4113_PEM      (1<<3)
0233 /* DAT Start ID Detect, 0 = no detect, 1 = detect */
0234 #define AK4113_DAT      (1<<2)
0235 /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */
0236 #define AK4113_DTSCD        (1<<1)
0237 /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */
0238 #define AK4113_NPCM     (1<<0)
0239 #define AK4113_FS_8000HZ    (AK4113_FS3|AK4113_FS0)
0240 #define AK4113_FS_11025HZ   (AK4113_FS2|AK4113_FS0)
0241 #define AK4113_FS_16000HZ   (AK4113_FS2|AK4113_FS1|AK4113_FS0)
0242 #define AK4113_FS_22050HZ   (AK4113_FS2)
0243 #define AK4113_FS_24000HZ   (AK4113_FS2|AK4113_FS1)
0244 #define AK4113_FS_32000HZ   (AK4113_FS1|AK4113_FS0)
0245 #define AK4113_FS_44100HZ   (0)
0246 #define AK4113_FS_48000HZ   (AK4113_FS1)
0247 #define AK4113_FS_64000HZ   (AK4113_FS3|AK4113_FS1|AK4113_FS0)
0248 #define AK4113_FS_88200HZ   (AK4113_FS3)
0249 #define AK4113_FS_96000HZ   (AK4113_FS3|AK4113_FS1)
0250 #define AK4113_FS_176400HZ  (AK4113_FS3|AK4113_FS2)
0251 #define AK4113_FS_192000HZ  (AK4113_FS3|AK4113_FS2|AK4113_FS1)
0252
0253 /* AK4113_REG_RCS2 */
0254 /* CRC for Q-subcode, 0 = no error, 1 = error */
0255 #define AK4113_QCRC     (1<<1)
0256 /* CRC for channel status, 0 = no error, 1 = error */
0257 #define AK4113_CCRC     (1<<0)
0258
0259 /* flags for snd_ak4113_check_rate_and_errors() */
0260 #define AK4113_CHECK_NO_STAT    (1<<0)  /* no statistics */
0261 #define AK4113_CHECK_NO_RATE    (1<<1)  /* no rate check */
0262
0263 #define AK4113_CONTROLS     13
0264
0265 typedef void (ak4113_write_t)(void *private_data, unsigned char addr,
0266         unsigned char data);
0267 typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr);
0268
0269 enum {
0270     AK4113_PARITY_ERRORS,
0271     AK4113_V_BIT_ERRORS,
0272     AK4113_QCRC_ERRORS,
0273     AK4113_CCRC_ERRORS,
0274     AK4113_NUM_ERRORS
0275 };
0276
0277 struct ak4113 {
0278     struct snd_card *card;
0279     ak4113_write_t *write;
0280     ak4113_read_t *read;
0281     void *private_data;
0282     atomic_t wq_processing;
0283     struct mutex reinit_mutex;
0284     spinlock_t lock;
0285     unsigned char regmap[AK4113_WRITABLE_REGS];
0286     struct snd_kcontrol *kctls[AK4113_CONTROLS];
0287     struct snd_pcm_substream *substream;
0288     unsigned long errors[AK4113_NUM_ERRORS];
0289     unsigned char rcs0;
0290     unsigned char rcs1;
0291     unsigned char rcs2;
0292     struct delayed_work work;
0293     unsigned int check_flags;
0294     void *change_callback_private;
0295     void (*change_callback)(struct ak4113 *ak4113, unsigned char c0,
0296             unsigned char c1);
0297 };
0298
0299 int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read,
0300         ak4113_write_t *write,
0301         const unsigned char *pgm,
0302         void *private_data, struct ak4113 **r_ak4113);
0303 void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg,
0304         unsigned char mask, unsigned char val);
0305 void snd_ak4113_reinit(struct ak4113 *ak4113);
0306 int snd_ak4113_build(struct ak4113 *ak4113,
0307         struct snd_pcm_substream *capture_substream);
0308 int snd_ak4113_external_rate(struct ak4113 *ak4113);
0309 int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags);
0310
0311 #ifdef CONFIG_PM
0312 void snd_ak4113_suspend(struct ak4113 *chip);
0313 void snd_ak4113_resume(struct ak4113 *chip);
0314 #else
0315 static inline void snd_ak4113_suspend(struct ak4113 *chip) {}
0316 static inline void snd_ak4113_resume(struct ak4113 *chip) {}
0317 #endif
0318
0319 #endif /* __SOUND_AK4113_H */
0320