soc/tegra/mc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 NVIDIA Corporation
0004  */
0005
0006 #ifndef __SOC_TEGRA_MC_H__
0007 #define __SOC_TEGRA_MC_H__
0008
0009 #include <linux/bits.h>
0010 #include <linux/debugfs.h>
0011 #include <linux/err.h>
0012 #include <linux/interconnect-provider.h>
0013 #include <linux/irq.h>
0014 #include <linux/reset-controller.h>
0015 #include <linux/types.h>
0016
0017 struct clk;
0018 struct device;
0019 struct page;
0020
0021 struct tegra_mc_timing {
0022     unsigned long rate;
0023
0024     u32 *emem_data;
0025 };
0026
0027 struct tegra_mc_client {
0028     unsigned int id;
0029     const char *name;
0030     /*
0031      * For Tegra210 and earlier, this is the SWGROUP ID used for IOVA translations in the
0032      * Tegra SMMU, whereas on Tegra186 and later this is the ID used to override the ARM SMMU
0033      * stream ID used for IOVA translations for the given memory client.
0034      */
0035     union {
0036         unsigned int swgroup;
0037         unsigned int sid;
0038     };
0039
0040     unsigned int fifo_size;
0041
0042     struct {
0043         /* Tegra SMMU enable (Tegra210 and earlier) */
0044         struct {
0045             unsigned int reg;
0046             unsigned int bit;
0047         } smmu;
0048
0049         /* latency allowance */
0050         struct {
0051             unsigned int reg;
0052             unsigned int shift;
0053             unsigned int mask;
0054             unsigned int def;
0055         } la;
0056
0057         /* stream ID overrides (Tegra186 and later) */
0058         struct {
0059             unsigned int override;
0060             unsigned int security;
0061         } sid;
0062     } regs;
0063 };
0064
0065 struct tegra_smmu_swgroup {
0066     const char *name;
0067     unsigned int swgroup;
0068     unsigned int reg;
0069 };
0070
0071 struct tegra_smmu_group_soc {
0072     const char *name;
0073     const unsigned int *swgroups;
0074     unsigned int num_swgroups;
0075 };
0076
0077 struct tegra_smmu_soc {
0078     const struct tegra_mc_client *clients;
0079     unsigned int num_clients;
0080
0081     const struct tegra_smmu_swgroup *swgroups;
0082     unsigned int num_swgroups;
0083
0084     const struct tegra_smmu_group_soc *groups;
0085     unsigned int num_groups;
0086
0087     bool supports_round_robin_arbitration;
0088     bool supports_request_limit;
0089
0090     unsigned int num_tlb_lines;
0091     unsigned int num_asids;
0092 };
0093
0094 struct tegra_mc;
0095 struct tegra_smmu;
0096 struct gart_device;
0097
0098 #ifdef CONFIG_TEGRA_IOMMU_SMMU
0099 struct tegra_smmu *tegra_smmu_probe(struct device *dev,
0100                     const struct tegra_smmu_soc *soc,
0101                     struct tegra_mc *mc);
0102 void tegra_smmu_remove(struct tegra_smmu *smmu);
0103 #else
0104 static inline struct tegra_smmu *
0105 tegra_smmu_probe(struct device *dev, const struct tegra_smmu_soc *soc,
0106          struct tegra_mc *mc)
0107 {
0108     return NULL;
0109 }
0110
0111 static inline void tegra_smmu_remove(struct tegra_smmu *smmu)
0112 {
0113 }
0114 #endif
0115
0116 #ifdef CONFIG_TEGRA_IOMMU_GART
0117 struct gart_device *tegra_gart_probe(struct device *dev, struct tegra_mc *mc);
0118 int tegra_gart_suspend(struct gart_device *gart);
0119 int tegra_gart_resume(struct gart_device *gart);
0120 #else
0121 static inline struct gart_device *
0122 tegra_gart_probe(struct device *dev, struct tegra_mc *mc)
0123 {
0124     return ERR_PTR(-ENODEV);
0125 }
0126
0127 static inline int tegra_gart_suspend(struct gart_device *gart)
0128 {
0129     return -ENODEV;
0130 }
0131
0132 static inline int tegra_gart_resume(struct gart_device *gart)
0133 {
0134     return -ENODEV;
0135 }
0136 #endif
0137
0138 struct tegra_mc_reset {
0139     const char *name;
0140     unsigned long id;
0141     unsigned int control;
0142     unsigned int status;
0143     unsigned int reset;
0144     unsigned int bit;
0145 };
0146
0147 struct tegra_mc_reset_ops {
0148     int (*hotreset_assert)(struct tegra_mc *mc,
0149                    const struct tegra_mc_reset *rst);
0150     int (*hotreset_deassert)(struct tegra_mc *mc,
0151                  const struct tegra_mc_reset *rst);
0152     int (*block_dma)(struct tegra_mc *mc,
0153              const struct tegra_mc_reset *rst);
0154     bool (*dma_idling)(struct tegra_mc *mc,
0155                const struct tegra_mc_reset *rst);
0156     int (*unblock_dma)(struct tegra_mc *mc,
0157                const struct tegra_mc_reset *rst);
0158     int (*reset_status)(struct tegra_mc *mc,
0159                 const struct tegra_mc_reset *rst);
0160 };
0161
0162 #define TEGRA_MC_ICC_TAG_DEFAULT                0
0163 #define TEGRA_MC_ICC_TAG_ISO                    BIT(0)
0164
0165 struct tegra_mc_icc_ops {
0166     int (*set)(struct icc_node *src, struct icc_node *dst);
0167     int (*aggregate)(struct icc_node *node, u32 tag, u32 avg_bw,
0168              u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
0169     struct icc_node_data *(*xlate_extended)(struct of_phandle_args *spec,
0170                         void *data);
0171 };
0172
0173 struct tegra_mc_ops {
0174     /*
0175      * @probe: Callback to set up SoC-specific bits of the memory controller. This is called
0176      * after basic, common set up that is done by the SoC-agnostic bits.
0177      */
0178     int (*probe)(struct tegra_mc *mc);
0179     void (*remove)(struct tegra_mc *mc);
0180     int (*suspend)(struct tegra_mc *mc);
0181     int (*resume)(struct tegra_mc *mc);
0182     irqreturn_t (*handle_irq)(int irq, void *data);
0183     int (*probe_device)(struct tegra_mc *mc, struct device *dev);
0184 };
0185
0186 struct tegra_mc_soc {
0187     const struct tegra_mc_client *clients;
0188     unsigned int num_clients;
0189
0190     const unsigned long *emem_regs;
0191     unsigned int num_emem_regs;
0192
0193     unsigned int num_address_bits;
0194     unsigned int atom_size;
0195
0196     u16 client_id_mask;
0197     u8 num_channels;
0198
0199     const struct tegra_smmu_soc *smmu;
0200
0201     u32 intmask;
0202     u32 ch_intmask;
0203     u32 global_intstatus_channel_shift;
0204     bool has_addr_hi_reg;
0205
0206     const struct tegra_mc_reset_ops *reset_ops;
0207     const struct tegra_mc_reset *resets;
0208     unsigned int num_resets;
0209
0210     const struct tegra_mc_icc_ops *icc_ops;
0211     const struct tegra_mc_ops *ops;
0212 };
0213
0214 struct tegra_mc {
0215     struct device *dev;
0216     struct tegra_smmu *smmu;
0217     struct gart_device *gart;
0218     void __iomem *regs;
0219     void __iomem *bcast_ch_regs;
0220     void __iomem **ch_regs;
0221     struct clk *clk;
0222     int irq;
0223
0224     const struct tegra_mc_soc *soc;
0225     unsigned long tick;
0226
0227     struct tegra_mc_timing *timings;
0228     unsigned int num_timings;
0229
0230     struct reset_controller_dev reset;
0231
0232     struct icc_provider provider;
0233
0234     spinlock_t lock;
0235
0236     struct {
0237         struct dentry *root;
0238     } debugfs;
0239 };
0240
0241 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate);
0242 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc);
0243
0244 #ifdef CONFIG_TEGRA_MC
0245 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev);
0246 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev);
0247 #else
0248 static inline struct tegra_mc *
0249 devm_tegra_memory_controller_get(struct device *dev)
0250 {
0251     return ERR_PTR(-ENODEV);
0252 }
0253
0254 static inline int
0255 tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
0256 {
0257     return -ENODEV;
0258 }
0259 #endif
0260
0261 #endif /* __SOC_TEGRA_MC_H__ */