soc/tegra/fuse.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef __SOC_TEGRA_FUSE_H__
0007 #define __SOC_TEGRA_FUSE_H__
0008
0009 #include <linux/types.h>
0010
0011 #define TEGRA20     0x20
0012 #define TEGRA30     0x30
0013 #define TEGRA114    0x35
0014 #define TEGRA124    0x40
0015 #define TEGRA132    0x13
0016 #define TEGRA210    0x21
0017 #define TEGRA186    0x18
0018 #define TEGRA194    0x19
0019 #define TEGRA234    0x23
0020
0021 #define TEGRA_FUSE_SKU_CALIB_0  0xf0
0022 #define TEGRA30_FUSE_SATA_CALIB 0x124
0023 #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
0024
0025 #ifndef __ASSEMBLY__
0026
0027 enum tegra_revision {
0028     TEGRA_REVISION_UNKNOWN = 0,
0029     TEGRA_REVISION_A01,
0030     TEGRA_REVISION_A02,
0031     TEGRA_REVISION_A03,
0032     TEGRA_REVISION_A03p,
0033     TEGRA_REVISION_A04,
0034     TEGRA_REVISION_MAX,
0035 };
0036
0037 struct tegra_sku_info {
0038     int sku_id;
0039     int cpu_process_id;
0040     int cpu_speedo_id;
0041     int cpu_speedo_value;
0042     int cpu_iddq_value;
0043     int soc_process_id;
0044     int soc_speedo_id;
0045     int soc_speedo_value;
0046     int gpu_process_id;
0047     int gpu_speedo_id;
0048     int gpu_speedo_value;
0049     enum tegra_revision revision;
0050 };
0051
0052 #ifdef CONFIG_ARCH_TEGRA
0053 extern struct tegra_sku_info tegra_sku_info;
0054 u32 tegra_read_straps(void);
0055 u32 tegra_read_ram_code(void);
0056 int tegra_fuse_readl(unsigned long offset, u32 *value);
0057 u32 tegra_read_chipid(void);
0058 u8 tegra_get_chip_id(void);
0059 u8 tegra_get_platform(void);
0060 bool tegra_is_silicon(void);
0061 #else
0062 static struct tegra_sku_info tegra_sku_info __maybe_unused;
0063
0064 static inline u32 tegra_read_straps(void)
0065 {
0066     return 0;
0067 }
0068
0069 static inline u32 tegra_read_ram_code(void)
0070 {
0071     return 0;
0072 }
0073
0074 static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
0075 {
0076     return -ENODEV;
0077 }
0078
0079 static inline u32 tegra_read_chipid(void)
0080 {
0081     return 0;
0082 }
0083
0084 static inline u8 tegra_get_chip_id(void)
0085 {
0086     return 0;
0087 }
0088
0089 static inline u8 tegra_get_platform(void)
0090 {
0091     return 0;
0092 }
0093
0094 static inline bool tegra_is_silicon(void)
0095 {
0096     return false;
0097 }
0098 #endif
0099
0100 struct device *tegra_soc_device_register(void);
0101
0102 #endif /* __ASSEMBLY__ */
0103
0104 #endif /* __SOC_TEGRA_FUSE_H__ */