soc/tegra/flowctrl.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Functions and macros to control the flowcontroller
0004  *
0005  * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
0006  */
0007
0008 #ifndef __SOC_TEGRA_FLOWCTRL_H__
0009 #define __SOC_TEGRA_FLOWCTRL_H__
0010
0011 #define FLOW_CTRL_HALT_CPU0_EVENTS  0x0
0012 #define FLOW_CTRL_WAITEVENT     (2 << 29)
0013 #define FLOW_CTRL_WAIT_FOR_INTERRUPT    (4 << 29)
0014 #define FLOW_CTRL_JTAG_RESUME       (1 << 28)
0015 #define FLOW_CTRL_SCLK_RESUME       (1 << 27)
0016 #define FLOW_CTRL_HALT_CPU_IRQ      (1 << 10)
0017 #define FLOW_CTRL_HALT_CPU_FIQ      (1 << 8)
0018 #define FLOW_CTRL_HALT_LIC_IRQ      (1 << 11)
0019 #define FLOW_CTRL_HALT_LIC_FIQ      (1 << 10)
0020 #define FLOW_CTRL_HALT_GIC_IRQ      (1 << 9)
0021 #define FLOW_CTRL_HALT_GIC_FIQ      (1 << 8)
0022 #define FLOW_CTRL_CPU0_CSR      0x8
0023 #define FLOW_CTRL_CSR_INTR_FLAG     (1 << 15)
0024 #define FLOW_CTRL_CSR_EVENT_FLAG    (1 << 14)
0025 #define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL  (1 << 13)
0026 #define FLOW_CTRL_CSR_ENABLE_EXT_NCPU   (1 << 12)
0027 #define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
0028         FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
0029         FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
0030 #define FLOW_CTRL_CSR_ENABLE        (1 << 0)
0031 #define FLOW_CTRL_HALT_CPU1_EVENTS  0x14
0032 #define FLOW_CTRL_CPU1_CSR      0x18
0033
0034 #define TEGRA20_FLOW_CTRL_CSR_WFE_CPU0      (1 << 4)
0035 #define TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP    (3 << 4)
0036 #define TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP    0
0037
0038 #define TEGRA30_FLOW_CTRL_CSR_WFI_CPU0      (1 << 8)
0039 #define TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP    (0xF << 4)
0040 #define TEGRA30_FLOW_CTRL_CSR_WFI_BITMAP    (0xF << 8)
0041
0042 #ifndef __ASSEMBLY__
0043 #ifdef CONFIG_SOC_TEGRA_FLOWCTRL
0044 u32 flowctrl_read_cpu_csr(unsigned int cpuid);
0045 void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
0046 void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
0047
0048 void flowctrl_cpu_suspend_enter(unsigned int cpuid);
0049 void flowctrl_cpu_suspend_exit(unsigned int cpuid);
0050 #else
0051 static inline u32 flowctrl_read_cpu_csr(unsigned int cpuid)
0052 {
0053     return 0;
0054 }
0055
0056 static inline void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
0057 {
0058 }
0059
0060 static inline void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value) {}
0061
0062 static inline void flowctrl_cpu_suspend_enter(unsigned int cpuid)
0063 {
0064 }
0065
0066 static inline void flowctrl_cpu_suspend_exit(unsigned int cpuid)
0067 {
0068 }
0069 #endif /* CONFIG_SOC_TEGRA_FLOWCTRL */
0070 #endif /* __ASSEMBLY */
0071 #endif /* __SOC_TEGRA_FLOWCTRL_H__ */