soc/mscc/ocelot_sys.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Microsemi Ocelot Switch driver
0004  *
0005  * Copyright (c) 2017 Microsemi Corporation
0006  */
0007
0008 #ifndef _MSCC_OCELOT_SYS_H_
0009 #define _MSCC_OCELOT_SYS_H_
0010
0011 #define SYS_COUNT_RX_OCTETS_RSZ                           0x4
0012
0013 #define SYS_COUNT_TX_OCTETS_RSZ                           0x4
0014
0015 #define SYS_FRONT_PORT_MODE_RSZ                           0x4
0016
0017 #define SYS_FRONT_PORT_MODE_HDX_MODE                      BIT(0)
0018
0019 #define SYS_FRM_AGING_AGE_TX_ENA                          BIT(20)
0020 #define SYS_FRM_AGING_MAX_AGE(x)                          ((x) & GENMASK(19, 0))
0021 #define SYS_FRM_AGING_MAX_AGE_M                           GENMASK(19, 0)
0022
0023 #define SYS_STAT_CFG_STAT_CLEAR_SHOT(x)                   (((x) << 10) & GENMASK(16, 10))
0024 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_M                    GENMASK(16, 10)
0025 #define SYS_STAT_CFG_STAT_CLEAR_SHOT_X(x)                 (((x) & GENMASK(16, 10)) >> 10)
0026 #define SYS_STAT_CFG_STAT_VIEW(x)                         ((x) & GENMASK(9, 0))
0027 #define SYS_STAT_CFG_STAT_VIEW_M                          GENMASK(9, 0)
0028
0029 #define SYS_SW_STATUS_RSZ                                 0x4
0030
0031 #define SYS_SW_STATUS_PORT_RX_PAUSED                      BIT(0)
0032
0033 #define SYS_MISC_CFG_PTP_RSRV_CLR                         BIT(1)
0034 #define SYS_MISC_CFG_PTP_DIS_NEG_RO                       BIT(0)
0035
0036 #define SYS_REW_MAC_HIGH_CFG_RSZ                          0x4
0037
0038 #define SYS_REW_MAC_LOW_CFG_RSZ                           0x4
0039
0040 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG(x)              (((x) << 6) & GENMASK(21, 6))
0041 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_M               GENMASK(21, 6)
0042 #define SYS_TIMESTAMP_OFFSET_ETH_TYPE_CFG_X(x)            (((x) & GENMASK(21, 6)) >> 6)
0043 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET(x)          ((x) & GENMASK(5, 0))
0044 #define SYS_TIMESTAMP_OFFSET_TIMESTAMP_OFFSET_M           GENMASK(5, 0)
0045
0046 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START(x)              (((x) << 9) & GENMASK(17, 9))
0047 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_M               GENMASK(17, 9)
0048 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_START_X(x)            (((x) & GENMASK(17, 9)) >> 9)
0049 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP(x)               ((x) & GENMASK(8, 0))
0050 #define SYS_PAUSE_TOT_CFG_PAUSE_TOT_STOP_M                GENMASK(8, 0)
0051
0052 #define SYS_ATOP_RSZ                                      0x4
0053
0054 #define SYS_MAC_FC_CFG_RSZ                                0x4
0055
0056 #define SYS_MAC_FC_CFG_FC_LINK_SPEED(x)                   (((x) << 26) & GENMASK(27, 26))
0057 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_M                    GENMASK(27, 26)
0058 #define SYS_MAC_FC_CFG_FC_LINK_SPEED_X(x)                 (((x) & GENMASK(27, 26)) >> 26)
0059 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x)                  (((x) << 20) & GENMASK(25, 20))
0060 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M                   GENMASK(25, 20)
0061 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x)                (((x) & GENMASK(25, 20)) >> 20)
0062 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA                     BIT(18)
0063 #define SYS_MAC_FC_CFG_TX_FC_ENA                          BIT(17)
0064 #define SYS_MAC_FC_CFG_RX_FC_ENA                          BIT(16)
0065 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG(x)                   ((x) & GENMASK(15, 0))
0066 #define SYS_MAC_FC_CFG_PAUSE_VAL_CFG_M                    GENMASK(15, 0)
0067
0068 #define SYS_MMGT_RELCNT(x)                                (((x) << 16) & GENMASK(31, 16))
0069 #define SYS_MMGT_RELCNT_M                                 GENMASK(31, 16)
0070 #define SYS_MMGT_RELCNT_X(x)                              (((x) & GENMASK(31, 16)) >> 16)
0071 #define SYS_MMGT_FREECNT(x)                               ((x) & GENMASK(15, 0))
0072 #define SYS_MMGT_FREECNT_M                                GENMASK(15, 0)
0073
0074 #define SYS_MMGT_FAST_FREEVLD(x)                          (((x) << 4) & GENMASK(7, 4))
0075 #define SYS_MMGT_FAST_FREEVLD_M                           GENMASK(7, 4)
0076 #define SYS_MMGT_FAST_FREEVLD_X(x)                        (((x) & GENMASK(7, 4)) >> 4)
0077 #define SYS_MMGT_FAST_RELVLD(x)                           ((x) & GENMASK(3, 0))
0078 #define SYS_MMGT_FAST_RELVLD_M                            GENMASK(3, 0)
0079
0080 #define SYS_EVENTS_DIF_RSZ                                0x4
0081
0082 #define SYS_EVENTS_DIF_EV_DRX(x)                          (((x) << 6) & GENMASK(8, 6))
0083 #define SYS_EVENTS_DIF_EV_DRX_M                           GENMASK(8, 6)
0084 #define SYS_EVENTS_DIF_EV_DRX_X(x)                        (((x) & GENMASK(8, 6)) >> 6)
0085 #define SYS_EVENTS_DIF_EV_DTX(x)                          ((x) & GENMASK(5, 0))
0086 #define SYS_EVENTS_DIF_EV_DTX_M                           GENMASK(5, 0)
0087
0088 #define SYS_EVENTS_CORE_EV_FWR                            BIT(2)
0089 #define SYS_EVENTS_CORE_EV_ANA(x)                         ((x) & GENMASK(1, 0))
0090 #define SYS_EVENTS_CORE_EV_ANA_M                          GENMASK(1, 0)
0091
0092 #define SYS_CNT_GSZ                                       0x4
0093
0094 #define SYS_PTP_STATUS_PTP_TXSTAMP_OAM                    BIT(29)
0095 #define SYS_PTP_STATUS_PTP_OVFL                           BIT(28)
0096 #define SYS_PTP_STATUS_PTP_MESS_VLD                       BIT(27)
0097 #define SYS_PTP_STATUS_PTP_MESS_ID(x)                     (((x) << 21) & GENMASK(26, 21))
0098 #define SYS_PTP_STATUS_PTP_MESS_ID_M                      GENMASK(26, 21)
0099 #define SYS_PTP_STATUS_PTP_MESS_ID_X(x)                   (((x) & GENMASK(26, 21)) >> 21)
0100 #define SYS_PTP_STATUS_PTP_MESS_TXPORT(x)                 (((x) << 16) & GENMASK(20, 16))
0101 #define SYS_PTP_STATUS_PTP_MESS_TXPORT_M                  GENMASK(20, 16)
0102 #define SYS_PTP_STATUS_PTP_MESS_TXPORT_X(x)               (((x) & GENMASK(20, 16)) >> 16)
0103 #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID(x)                 ((x) & GENMASK(15, 0))
0104 #define SYS_PTP_STATUS_PTP_MESS_SEQ_ID_M                  GENMASK(15, 0)
0105
0106 #define SYS_PTP_TXSTAMP_PTP_TXSTAMP(x)                    ((x) & GENMASK(29, 0))
0107 #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_M                     GENMASK(29, 0)
0108 #define SYS_PTP_TXSTAMP_PTP_TXSTAMP_SEC                   BIT(31)
0109
0110 #define SYS_PTP_NXT_PTP_NXT                               BIT(0)
0111
0112 #define SYS_PTP_CFG_PTP_STAMP_WID(x)                      (((x) << 2) & GENMASK(7, 2))
0113 #define SYS_PTP_CFG_PTP_STAMP_WID_M                       GENMASK(7, 2)
0114 #define SYS_PTP_CFG_PTP_STAMP_WID_X(x)                    (((x) & GENMASK(7, 2)) >> 2)
0115 #define SYS_PTP_CFG_PTP_CF_ROLL_MODE(x)                   ((x) & GENMASK(1, 0))
0116 #define SYS_PTP_CFG_PTP_CF_ROLL_MODE_M                    GENMASK(1, 0)
0117
0118 #define SYS_RAM_INIT_RAM_INIT                             BIT(1)
0119 #define SYS_RAM_INIT_RAM_CFG_HOOK                         BIT(0)
0120
0121 #endif