soc/mscc/ocelot_qsys.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Microsemi Ocelot Switch driver
0004  *
0005  * Copyright (c) 2017 Microsemi Corporation
0006  */
0007
0008 #ifndef _MSCC_OCELOT_QSYS_H_
0009 #define _MSCC_OCELOT_QSYS_H_
0010
0011 #define QSYS_PORT_MODE_RSZ                                0x4
0012
0013 #define QSYS_PORT_MODE_DEQUEUE_DIS                        BIT(1)
0014 #define QSYS_PORT_MODE_DEQUEUE_LATE                       BIT(0)
0015
0016 #define QSYS_STAT_CNT_CFG_TX_GREEN_CNT_MODE               BIT(5)
0017 #define QSYS_STAT_CNT_CFG_TX_YELLOW_CNT_MODE              BIT(4)
0018 #define QSYS_STAT_CNT_CFG_DROP_GREEN_CNT_MODE             BIT(3)
0019 #define QSYS_STAT_CNT_CFG_DROP_YELLOW_CNT_MODE            BIT(2)
0020 #define QSYS_STAT_CNT_CFG_DROP_COUNT_ONCE                 BIT(1)
0021 #define QSYS_STAT_CNT_CFG_DROP_COUNT_EGRESS               BIT(0)
0022
0023 #define QSYS_EEE_CFG_RSZ                                  0x4
0024
0025 #define QSYS_EEE_THRES_EEE_HIGH_BYTES(x)                  (((x) << 8) & GENMASK(15, 8))
0026 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_M                   GENMASK(15, 8)
0027 #define QSYS_EEE_THRES_EEE_HIGH_BYTES_X(x)                (((x) & GENMASK(15, 8)) >> 8)
0028 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES(x)                 ((x) & GENMASK(7, 0))
0029 #define QSYS_EEE_THRES_EEE_HIGH_FRAMES_M                  GENMASK(7, 0)
0030
0031 #define QSYS_SW_STATUS_RSZ                                0x4
0032
0033 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT(x)                  (((x) << 8) & GENMASK(12, 8))
0034 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_M                   GENMASK(12, 8)
0035 #define QSYS_EXT_CPU_CFG_EXT_CPU_PORT_X(x)                (((x) & GENMASK(12, 8)) >> 8)
0036 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK(x)                  ((x) & GENMASK(7, 0))
0037 #define QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M                   GENMASK(7, 0)
0038
0039 #define QSYS_QMAP_GSZ                                     0x4
0040
0041 #define QSYS_QMAP_SE_BASE(x)                              (((x) << 5) & GENMASK(12, 5))
0042 #define QSYS_QMAP_SE_BASE_M                               GENMASK(12, 5)
0043 #define QSYS_QMAP_SE_BASE_X(x)                            (((x) & GENMASK(12, 5)) >> 5)
0044 #define QSYS_QMAP_SE_IDX_SEL(x)                           (((x) << 2) & GENMASK(4, 2))
0045 #define QSYS_QMAP_SE_IDX_SEL_M                            GENMASK(4, 2)
0046 #define QSYS_QMAP_SE_IDX_SEL_X(x)                         (((x) & GENMASK(4, 2)) >> 2)
0047 #define QSYS_QMAP_SE_INP_SEL(x)                           ((x) & GENMASK(1, 0))
0048 #define QSYS_QMAP_SE_INP_SEL_M                            GENMASK(1, 0)
0049
0050 #define QSYS_ISDX_SGRP_GSZ                                0x4
0051
0052 #define QSYS_TIMED_FRAME_ENTRY_GSZ                        0x4
0053
0054 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT(x)               (((x) << 9) & GENMASK(18, 9))
0055 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_M                GENMASK(18, 9)
0056 #define QSYS_TFRM_MISC_TIMED_CANCEL_SLOT_X(x)             (((x) & GENMASK(18, 9)) >> 9)
0057 #define QSYS_TFRM_MISC_TIMED_CANCEL_1SHOT                 BIT(8)
0058 #define QSYS_TFRM_MISC_TIMED_SLOT_MODE_MC                 BIT(7)
0059 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT(x)            ((x) & GENMASK(6, 0))
0060 #define QSYS_TFRM_MISC_TIMED_ENTRY_FAST_CNT_M             GENMASK(6, 0)
0061
0062 #define QSYS_RED_PROFILE_RSZ                              0x4
0063
0064 #define QSYS_RED_PROFILE_WM_RED_LOW(x)                    (((x) << 8) & GENMASK(15, 8))
0065 #define QSYS_RED_PROFILE_WM_RED_LOW_M                     GENMASK(15, 8)
0066 #define QSYS_RED_PROFILE_WM_RED_LOW_X(x)                  (((x) & GENMASK(15, 8)) >> 8)
0067 #define QSYS_RED_PROFILE_WM_RED_HIGH(x)                   ((x) & GENMASK(7, 0))
0068 #define QSYS_RED_PROFILE_WM_RED_HIGH_M                    GENMASK(7, 0)
0069
0070 #define QSYS_RES_CFG_GSZ                                  0x8
0071
0072 #define QSYS_RES_STAT_GSZ                                 0x8
0073
0074 #define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT(x)                  ((x) & GENMASK(15, 0))
0075 #define QSYS_MMGT_EQ_CTRL_FP_FREE_CNT_M                   GENMASK(15, 0)
0076
0077 #define QSYS_EVENTS_CORE_EV_FDC(x)                        (((x) << 2) & GENMASK(4, 2))
0078 #define QSYS_EVENTS_CORE_EV_FDC_M                         GENMASK(4, 2)
0079 #define QSYS_EVENTS_CORE_EV_FDC_X(x)                      (((x) & GENMASK(4, 2)) >> 2)
0080 #define QSYS_EVENTS_CORE_EV_FRD(x)                        ((x) & GENMASK(1, 0))
0081 #define QSYS_EVENTS_CORE_EV_FRD_M                         GENMASK(1, 0)
0082
0083 #define QSYS_QMAXSDU_CFG_0_RSZ                            0x4
0084
0085 #define QSYS_QMAXSDU_CFG_1_RSZ                            0x4
0086
0087 #define QSYS_QMAXSDU_CFG_2_RSZ                            0x4
0088
0089 #define QSYS_QMAXSDU_CFG_3_RSZ                            0x4
0090
0091 #define QSYS_QMAXSDU_CFG_4_RSZ                            0x4
0092
0093 #define QSYS_QMAXSDU_CFG_5_RSZ                            0x4
0094
0095 #define QSYS_QMAXSDU_CFG_6_RSZ                            0x4
0096
0097 #define QSYS_QMAXSDU_CFG_7_RSZ                            0x4
0098
0099 #define QSYS_PREEMPTION_CFG_RSZ                           0x4
0100
0101 #define QSYS_PREEMPTION_CFG_P_QUEUES(x)                   ((x) & GENMASK(7, 0))
0102 #define QSYS_PREEMPTION_CFG_P_QUEUES_M                    GENMASK(7, 0)
0103 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE(x)           (((x) << 8) & GENMASK(9, 8))
0104 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_M            GENMASK(9, 8)
0105 #define QSYS_PREEMPTION_CFG_MM_ADD_FRAG_SIZE_X(x)         (((x) & GENMASK(9, 8)) >> 8)
0106 #define QSYS_PREEMPTION_CFG_STRICT_IPG(x)                 (((x) << 12) & GENMASK(13, 12))
0107 #define QSYS_PREEMPTION_CFG_STRICT_IPG_M                  GENMASK(13, 12)
0108 #define QSYS_PREEMPTION_CFG_STRICT_IPG_X(x)               (((x) & GENMASK(13, 12)) >> 12)
0109 #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE(x)               (((x) << 16) & GENMASK(31, 16))
0110 #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_M                GENMASK(31, 16)
0111 #define QSYS_PREEMPTION_CFG_HOLD_ADVANCE_X(x)             (((x) & GENMASK(31, 16)) >> 16)
0112
0113 #define QSYS_CIR_CFG_GSZ                                  0x80
0114
0115 #define QSYS_CIR_CFG_CIR_RATE(x)                          (((x) << 6) & GENMASK(20, 6))
0116 #define QSYS_CIR_CFG_CIR_RATE_M                           GENMASK(20, 6)
0117 #define QSYS_CIR_CFG_CIR_RATE_X(x)                        (((x) & GENMASK(20, 6)) >> 6)
0118 #define QSYS_CIR_CFG_CIR_BURST(x)                         ((x) & GENMASK(5, 0))
0119 #define QSYS_CIR_CFG_CIR_BURST_M                          GENMASK(5, 0)
0120
0121 #define QSYS_EIR_CFG_GSZ                                  0x80
0122
0123 #define QSYS_EIR_CFG_EIR_RATE(x)                          (((x) << 7) & GENMASK(21, 7))
0124 #define QSYS_EIR_CFG_EIR_RATE_M                           GENMASK(21, 7)
0125 #define QSYS_EIR_CFG_EIR_RATE_X(x)                        (((x) & GENMASK(21, 7)) >> 7)
0126 #define QSYS_EIR_CFG_EIR_BURST(x)                         (((x) << 1) & GENMASK(6, 1))
0127 #define QSYS_EIR_CFG_EIR_BURST_M                          GENMASK(6, 1)
0128 #define QSYS_EIR_CFG_EIR_BURST_X(x)                       (((x) & GENMASK(6, 1)) >> 1)
0129 #define QSYS_EIR_CFG_EIR_MARK_ENA                         BIT(0)
0130
0131 #define QSYS_SE_CFG_GSZ                                   0x80
0132
0133 #define QSYS_SE_CFG_SE_DWRR_CNT(x)                        (((x) << 6) & GENMASK(9, 6))
0134 #define QSYS_SE_CFG_SE_DWRR_CNT_M                         GENMASK(9, 6)
0135 #define QSYS_SE_CFG_SE_DWRR_CNT_X(x)                      (((x) & GENMASK(9, 6)) >> 6)
0136 #define QSYS_SE_CFG_SE_RR_ENA                             BIT(5)
0137 #define QSYS_SE_CFG_SE_AVB_ENA                            BIT(4)
0138 #define QSYS_SE_CFG_SE_FRM_MODE(x)                        (((x) << 2) & GENMASK(3, 2))
0139 #define QSYS_SE_CFG_SE_FRM_MODE_M                         GENMASK(3, 2)
0140 #define QSYS_SE_CFG_SE_FRM_MODE_X(x)                      (((x) & GENMASK(3, 2)) >> 2)
0141 #define QSYS_SE_CFG_SE_EXC_ENA                            BIT(1)
0142 #define QSYS_SE_CFG_SE_EXC_FWD                            BIT(0)
0143
0144 #define QSYS_SE_DWRR_CFG_GSZ                              0x80
0145 #define QSYS_SE_DWRR_CFG_RSZ                              0x4
0146
0147 #define QSYS_SE_CONNECT_GSZ                               0x80
0148
0149 #define QSYS_SE_CONNECT_SE_OUTP_IDX(x)                    (((x) << 17) & GENMASK(24, 17))
0150 #define QSYS_SE_CONNECT_SE_OUTP_IDX_M                     GENMASK(24, 17)
0151 #define QSYS_SE_CONNECT_SE_OUTP_IDX_X(x)                  (((x) & GENMASK(24, 17)) >> 17)
0152 #define QSYS_SE_CONNECT_SE_INP_IDX(x)                     (((x) << 9) & GENMASK(16, 9))
0153 #define QSYS_SE_CONNECT_SE_INP_IDX_M                      GENMASK(16, 9)
0154 #define QSYS_SE_CONNECT_SE_INP_IDX_X(x)                   (((x) & GENMASK(16, 9)) >> 9)
0155 #define QSYS_SE_CONNECT_SE_OUTP_CON(x)                    (((x) << 5) & GENMASK(8, 5))
0156 #define QSYS_SE_CONNECT_SE_OUTP_CON_M                     GENMASK(8, 5)
0157 #define QSYS_SE_CONNECT_SE_OUTP_CON_X(x)                  (((x) & GENMASK(8, 5)) >> 5)
0158 #define QSYS_SE_CONNECT_SE_INP_CNT(x)                     (((x) << 1) & GENMASK(4, 1))
0159 #define QSYS_SE_CONNECT_SE_INP_CNT_M                      GENMASK(4, 1)
0160 #define QSYS_SE_CONNECT_SE_INP_CNT_X(x)                   (((x) & GENMASK(4, 1)) >> 1)
0161 #define QSYS_SE_CONNECT_SE_TERMINAL                       BIT(0)
0162
0163 #define QSYS_SE_DLB_SENSE_GSZ                             0x80
0164
0165 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO(x)                  (((x) << 11) & GENMASK(13, 11))
0166 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_M                   GENMASK(13, 11)
0167 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_X(x)                (((x) & GENMASK(13, 11)) >> 11)
0168 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT(x)                 (((x) << 7) & GENMASK(10, 7))
0169 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_M                  GENMASK(10, 7)
0170 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_X(x)               (((x) & GENMASK(10, 7)) >> 7)
0171 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT(x)                 (((x) << 3) & GENMASK(6, 3))
0172 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_M                  GENMASK(6, 3)
0173 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_X(x)               (((x) & GENMASK(6, 3)) >> 3)
0174 #define QSYS_SE_DLB_SENSE_SE_DLB_PRIO_ENA                 BIT(2)
0175 #define QSYS_SE_DLB_SENSE_SE_DLB_SPORT_ENA                BIT(1)
0176 #define QSYS_SE_DLB_SENSE_SE_DLB_DPORT_ENA                BIT(0)
0177
0178 #define QSYS_CIR_STATE_GSZ                                0x80
0179
0180 #define QSYS_CIR_STATE_CIR_LVL(x)                         (((x) << 4) & GENMASK(25, 4))
0181 #define QSYS_CIR_STATE_CIR_LVL_M                          GENMASK(25, 4)
0182 #define QSYS_CIR_STATE_CIR_LVL_X(x)                       (((x) & GENMASK(25, 4)) >> 4)
0183 #define QSYS_CIR_STATE_SHP_TIME(x)                        ((x) & GENMASK(3, 0))
0184 #define QSYS_CIR_STATE_SHP_TIME_M                         GENMASK(3, 0)
0185
0186 #define QSYS_EIR_STATE_GSZ                                0x80
0187
0188 #define QSYS_SE_STATE_GSZ                                 0x80
0189
0190 #define QSYS_SE_STATE_SE_OUTP_LVL(x)                      (((x) << 1) & GENMASK(2, 1))
0191 #define QSYS_SE_STATE_SE_OUTP_LVL_M                       GENMASK(2, 1)
0192 #define QSYS_SE_STATE_SE_OUTP_LVL_X(x)                    (((x) & GENMASK(2, 1)) >> 1)
0193 #define QSYS_SE_STATE_SE_WAS_YEL                          BIT(0)
0194
0195 #define QSYS_HSCH_MISC_CFG_SE_CONNECT_VLD                 BIT(8)
0196 #define QSYS_HSCH_MISC_CFG_FRM_ADJ(x)                     (((x) << 3) & GENMASK(7, 3))
0197 #define QSYS_HSCH_MISC_CFG_FRM_ADJ_M                      GENMASK(7, 3)
0198 #define QSYS_HSCH_MISC_CFG_FRM_ADJ_X(x)                   (((x) & GENMASK(7, 3)) >> 3)
0199 #define QSYS_HSCH_MISC_CFG_LEAK_DIS                       BIT(2)
0200 #define QSYS_HSCH_MISC_CFG_QSHP_EXC_ENA                   BIT(1)
0201 #define QSYS_HSCH_MISC_CFG_PFC_BYP_UPD                    BIT(0)
0202
0203 #define QSYS_TAG_CONFIG_RSZ                               0x4
0204
0205 #define QSYS_TAG_CONFIG_ENABLE                            BIT(0)
0206 #define QSYS_TAG_CONFIG_LINK_SPEED(x)                     (((x) << 4) & GENMASK(5, 4))
0207 #define QSYS_TAG_CONFIG_LINK_SPEED_M                      GENMASK(5, 4)
0208 #define QSYS_TAG_CONFIG_LINK_SPEED_X(x)                   (((x) & GENMASK(5, 4)) >> 4)
0209 #define QSYS_TAG_CONFIG_INIT_GATE_STATE(x)                (((x) << 8) & GENMASK(15, 8))
0210 #define QSYS_TAG_CONFIG_INIT_GATE_STATE_M                 GENMASK(15, 8)
0211 #define QSYS_TAG_CONFIG_INIT_GATE_STATE_X(x)              (((x) & GENMASK(15, 8)) >> 8)
0212 #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES(x)             (((x) << 16) & GENMASK(23, 16))
0213 #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_M              GENMASK(23, 16)
0214 #define QSYS_TAG_CONFIG_SCH_TRAFFIC_QUEUES_X(x)           (((x) & GENMASK(23, 16)) >> 16)
0215
0216 #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM(x)               ((x) & GENMASK(7, 0))
0217 #define QSYS_TAS_PARAM_CFG_CTRL_PORT_NUM_M                GENMASK(7, 0)
0218 #define QSYS_TAS_PARAM_CFG_CTRL_ALWAYS_GUARD_BAND_SCH_Q   BIT(8)
0219 #define QSYS_TAS_PARAM_CFG_CTRL_CONFIG_CHANGE             BIT(16)
0220
0221 #define QSYS_PORT_MAX_SDU_RSZ                             0x4
0222
0223 #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB(x)         ((x) & GENMASK(15, 0))
0224 #define QSYS_PARAM_CFG_REG_3_BASE_TIME_SEC_MSB_M          GENMASK(15, 0)
0225 #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH(x)               (((x) << 16) & GENMASK(31, 16))
0226 #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_M                GENMASK(31, 16)
0227 #define QSYS_PARAM_CFG_REG_3_LIST_LENGTH_X(x)             (((x) & GENMASK(31, 16)) >> 16)
0228
0229 #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM(x)               ((x) & GENMASK(5, 0))
0230 #define QSYS_GCL_CFG_REG_1_GCL_ENTRY_NUM_M                GENMASK(5, 0)
0231 #define QSYS_GCL_CFG_REG_1_GATE_STATE(x)                  (((x) << 8) & GENMASK(15, 8))
0232 #define QSYS_GCL_CFG_REG_1_GATE_STATE_M                   GENMASK(15, 8)
0233 #define QSYS_GCL_CFG_REG_1_GATE_STATE_X(x)                (((x) & GENMASK(15, 8)) >> 8)
0234
0235 #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB(x)      ((x) & GENMASK(15, 0))
0236 #define QSYS_PARAM_STATUS_REG_3_BASE_TIME_SEC_MSB_M       GENMASK(15, 0)
0237 #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH(x)            (((x) << 16) & GENMASK(31, 16))
0238 #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_M             GENMASK(31, 16)
0239 #define QSYS_PARAM_STATUS_REG_3_LIST_LENGTH_X(x)          (((x) & GENMASK(31, 16)) >> 16)
0240
0241 #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB(x)   ((x) & GENMASK(15, 0))
0242 #define QSYS_PARAM_STATUS_REG_8_CFG_CHG_TIME_SEC_MSB_M    GENMASK(15, 0)
0243 #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE(x)        (((x) << 16) & GENMASK(23, 16))
0244 #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_M         GENMASK(23, 16)
0245 #define QSYS_PARAM_STATUS_REG_8_OPER_GATE_STATE_X(x)      (((x) & GENMASK(23, 16)) >> 16)
0246 #define QSYS_PARAM_STATUS_REG_8_CONFIG_PENDING            BIT(24)
0247
0248 #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM(x)            ((x) & GENMASK(5, 0))
0249 #define QSYS_GCL_STATUS_REG_1_GCL_ENTRY_NUM_M             GENMASK(5, 0)
0250 #define QSYS_GCL_STATUS_REG_1_GATE_STATE(x)               (((x) << 8) & GENMASK(15, 8))
0251 #define QSYS_GCL_STATUS_REG_1_GATE_STATE_M                GENMASK(15, 8)
0252 #define QSYS_GCL_STATUS_REG_1_GATE_STATE_X(x)             (((x) & GENMASK(15, 8)) >> 8)
0253
0254 #endif