soc/mscc/ocelot_dev.h

0001 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
0002 /*
0003  * Microsemi Ocelot Switch driver
0004  *
0005  * Copyright (c) 2017 Microsemi Corporation
0006  */
0007
0008 #ifndef _MSCC_OCELOT_DEV_H_
0009 #define _MSCC_OCELOT_DEV_H_
0010
0011 #define DEV_CLOCK_CFG_MAC_TX_RST                          BIT(7)
0012 #define DEV_CLOCK_CFG_MAC_RX_RST                          BIT(6)
0013 #define DEV_CLOCK_CFG_PCS_TX_RST                          BIT(5)
0014 #define DEV_CLOCK_CFG_PCS_RX_RST                          BIT(4)
0015 #define DEV_CLOCK_CFG_PORT_RST                            BIT(3)
0016 #define DEV_CLOCK_CFG_PHY_RST                             BIT(2)
0017 #define DEV_CLOCK_CFG_LINK_SPEED(x)                       ((x) & GENMASK(1, 0))
0018 #define DEV_CLOCK_CFG_LINK_SPEED_M                        GENMASK(1, 0)
0019
0020 #define DEV_PORT_MISC_FWD_ERROR_ENA                       BIT(4)
0021 #define DEV_PORT_MISC_FWD_PAUSE_ENA                       BIT(3)
0022 #define DEV_PORT_MISC_FWD_CTRL_ENA                        BIT(2)
0023 #define DEV_PORT_MISC_DEV_LOOP_ENA                        BIT(1)
0024 #define DEV_PORT_MISC_HDX_FAST_DIS                        BIT(0)
0025
0026 #define DEV_EEE_CFG_EEE_ENA                               BIT(22)
0027 #define DEV_EEE_CFG_EEE_TIMER_AGE(x)                      (((x) << 15) & GENMASK(21, 15))
0028 #define DEV_EEE_CFG_EEE_TIMER_AGE_M                       GENMASK(21, 15)
0029 #define DEV_EEE_CFG_EEE_TIMER_AGE_X(x)                    (((x) & GENMASK(21, 15)) >> 15)
0030 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP(x)                   (((x) << 8) & GENMASK(14, 8))
0031 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_M                    GENMASK(14, 8)
0032 #define DEV_EEE_CFG_EEE_TIMER_WAKEUP_X(x)                 (((x) & GENMASK(14, 8)) >> 8)
0033 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF(x)                  (((x) << 1) & GENMASK(7, 1))
0034 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_M                   GENMASK(7, 1)
0035 #define DEV_EEE_CFG_EEE_TIMER_HOLDOFF_X(x)                (((x) & GENMASK(7, 1)) >> 1)
0036 #define DEV_EEE_CFG_PORT_LPI                              BIT(0)
0037
0038 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG(x)        (((x) << 4) & GENMASK(11, 4))
0039 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_M         GENMASK(11, 4)
0040 #define DEV_PTP_PREDICT_CFG_PTP_PHY_PREDICT_CFG_X(x)      (((x) & GENMASK(11, 4)) >> 4)
0041 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG(x)      ((x) & GENMASK(3, 0))
0042 #define DEV_PTP_PREDICT_CFG_PTP_PHASE_PREDICT_CFG_M       GENMASK(3, 0)
0043
0044 #define DEV_MAC_ENA_CFG_RX_ENA                            BIT(4)
0045 #define DEV_MAC_ENA_CFG_TX_ENA                            BIT(0)
0046
0047 #define DEV_MAC_MODE_CFG_FC_WORD_SYNC_ENA                 BIT(8)
0048 #define DEV_MAC_MODE_CFG_GIGA_MODE_ENA                    BIT(4)
0049 #define DEV_MAC_MODE_CFG_FDX_ENA                          BIT(0)
0050
0051 #define DEV_MAC_TAGS_CFG_TAG_ID(x)                        (((x) << 16) & GENMASK(31, 16))
0052 #define DEV_MAC_TAGS_CFG_TAG_ID_M                         GENMASK(31, 16)
0053 #define DEV_MAC_TAGS_CFG_TAG_ID_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
0054 #define DEV_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA                 BIT(2)
0055 #define DEV_MAC_TAGS_CFG_VLAN_DBL_AWR_ENA                 BIT(1)
0056 #define DEV_MAC_TAGS_CFG_VLAN_AWR_ENA                     BIT(0)
0057
0058 #define DEV_MAC_ADV_CHK_CFG_LEN_DROP_ENA                  BIT(0)
0059
0060 #define DEV_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK             BIT(17)
0061 #define DEV_MAC_IFG_CFG_REDUCED_TX_IFG                    BIT(16)
0062 #define DEV_MAC_IFG_CFG_TX_IFG(x)                         (((x) << 8) & GENMASK(12, 8))
0063 #define DEV_MAC_IFG_CFG_TX_IFG_M                          GENMASK(12, 8)
0064 #define DEV_MAC_IFG_CFG_TX_IFG_X(x)                       (((x) & GENMASK(12, 8)) >> 8)
0065 #define DEV_MAC_IFG_CFG_RX_IFG2(x)                        (((x) << 4) & GENMASK(7, 4))
0066 #define DEV_MAC_IFG_CFG_RX_IFG2_M                         GENMASK(7, 4)
0067 #define DEV_MAC_IFG_CFG_RX_IFG2_X(x)                      (((x) & GENMASK(7, 4)) >> 4)
0068 #define DEV_MAC_IFG_CFG_RX_IFG1(x)                        ((x) & GENMASK(3, 0))
0069 #define DEV_MAC_IFG_CFG_RX_IFG1_M                         GENMASK(3, 0)
0070
0071 #define DEV_MAC_HDX_CFG_BYPASS_COL_SYNC                   BIT(26)
0072 #define DEV_MAC_HDX_CFG_OB_ENA                            BIT(25)
0073 #define DEV_MAC_HDX_CFG_WEXC_DIS                          BIT(24)
0074 #define DEV_MAC_HDX_CFG_SEED(x)                           (((x) << 16) & GENMASK(23, 16))
0075 #define DEV_MAC_HDX_CFG_SEED_M                            GENMASK(23, 16)
0076 #define DEV_MAC_HDX_CFG_SEED_X(x)                         (((x) & GENMASK(23, 16)) >> 16)
0077 #define DEV_MAC_HDX_CFG_SEED_LOAD                         BIT(12)
0078 #define DEV_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA           BIT(8)
0079 #define DEV_MAC_HDX_CFG_LATE_COL_POS(x)                   ((x) & GENMASK(6, 0))
0080 #define DEV_MAC_HDX_CFG_LATE_COL_POS_M                    GENMASK(6, 0)
0081
0082 #define DEV_MAC_DBG_CFG_TBI_MODE                          BIT(4)
0083 #define DEV_MAC_DBG_CFG_IFG_CRS_EXT_CHK_ENA               BIT(0)
0084
0085 #define DEV_MAC_STICKY_RX_IPG_SHRINK_STICKY               BIT(9)
0086 #define DEV_MAC_STICKY_RX_PREAM_SHRINK_STICKY             BIT(8)
0087 #define DEV_MAC_STICKY_RX_CARRIER_EXT_STICKY              BIT(7)
0088 #define DEV_MAC_STICKY_RX_CARRIER_EXT_ERR_STICKY          BIT(6)
0089 #define DEV_MAC_STICKY_RX_JUNK_STICKY                     BIT(5)
0090 #define DEV_MAC_STICKY_TX_RETRANSMIT_STICKY               BIT(4)
0091 #define DEV_MAC_STICKY_TX_JAM_STICKY                      BIT(3)
0092 #define DEV_MAC_STICKY_TX_FIFO_OFLW_STICKY                BIT(2)
0093 #define DEV_MAC_STICKY_TX_FRM_LEN_OVR_STICKY              BIT(1)
0094 #define DEV_MAC_STICKY_TX_ABORT_STICKY                    BIT(0)
0095
0096 #define PCS1G_CFG_LINK_STATUS_TYPE                        BIT(4)
0097 #define PCS1G_CFG_AN_LINK_CTRL_ENA                        BIT(1)
0098 #define PCS1G_CFG_PCS_ENA                                 BIT(0)
0099
0100 #define PCS1G_MODE_CFG_UNIDIR_MODE_ENA                    BIT(4)
0101 #define PCS1G_MODE_CFG_SGMII_MODE_ENA                     BIT(0)
0102
0103 #define PCS1G_SD_CFG_SD_SEL                               BIT(8)
0104 #define PCS1G_SD_CFG_SD_POL                               BIT(4)
0105 #define PCS1G_SD_CFG_SD_ENA                               BIT(0)
0106
0107 #define PCS1G_ANEG_CFG_ADV_ABILITY(x)                     (((x) << 16) & GENMASK(31, 16))
0108 #define PCS1G_ANEG_CFG_ADV_ABILITY_M                      GENMASK(31, 16)
0109 #define PCS1G_ANEG_CFG_ADV_ABILITY_X(x)                   (((x) & GENMASK(31, 16)) >> 16)
0110 #define PCS1G_ANEG_CFG_SW_RESOLVE_ENA                     BIT(8)
0111 #define PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT              BIT(1)
0112 #define PCS1G_ANEG_CFG_ANEG_ENA                           BIT(0)
0113
0114 #define PCS1G_ANEG_NP_CFG_NP_TX(x)                        (((x) << 16) & GENMASK(31, 16))
0115 #define PCS1G_ANEG_NP_CFG_NP_TX_M                         GENMASK(31, 16)
0116 #define PCS1G_ANEG_NP_CFG_NP_TX_X(x)                      (((x) & GENMASK(31, 16)) >> 16)
0117 #define PCS1G_ANEG_NP_CFG_NP_LOADED_ONE_SHOT              BIT(0)
0118
0119 #define PCS1G_LB_CFG_RA_ENA                               BIT(4)
0120 #define PCS1G_LB_CFG_GMII_PHY_LB_ENA                      BIT(1)
0121 #define PCS1G_LB_CFG_TBI_HOST_LB_ENA                      BIT(0)
0122
0123 #define PCS1G_DBG_CFG_UDLT                                BIT(0)
0124
0125 #define PCS1G_CDET_CFG_CDET_ENA                           BIT(0)
0126
0127 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY(x)               (((x) << 16) & GENMASK(31, 16))
0128 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_M                GENMASK(31, 16)
0129 #define PCS1G_ANEG_STATUS_LP_ADV_ABILITY_X(x)             (((x) & GENMASK(31, 16)) >> 16)
0130 #define PCS1G_ANEG_STATUS_PR                              BIT(4)
0131 #define PCS1G_ANEG_STATUS_PAGE_RX_STICKY                  BIT(3)
0132 #define PCS1G_ANEG_STATUS_ANEG_COMPLETE                   BIT(0)
0133
0134 #define PCS1G_LINK_STATUS_DELAY_VAR(x)                    (((x) << 12) & GENMASK(15, 12))
0135 #define PCS1G_LINK_STATUS_DELAY_VAR_M                     GENMASK(15, 12)
0136 #define PCS1G_LINK_STATUS_DELAY_VAR_X(x)                  (((x) & GENMASK(15, 12)) >> 12)
0137 #define PCS1G_LINK_STATUS_SIGNAL_DETECT                   BIT(8)
0138 #define PCS1G_LINK_STATUS_LINK_STATUS                     BIT(4)
0139 #define PCS1G_LINK_STATUS_SYNC_STATUS                     BIT(0)
0140
0141 #define PCS1G_STICKY_LINK_DOWN_STICKY                     BIT(4)
0142 #define PCS1G_STICKY_OUT_OF_SYNC_STICKY                   BIT(0)
0143
0144 #define PCS1G_LPI_CFG_QSGMII_MS_SEL                       BIT(20)
0145 #define PCS1G_LPI_CFG_RX_LPI_OUT_DIS                      BIT(17)
0146 #define PCS1G_LPI_CFG_LPI_TESTMODE                        BIT(16)
0147 #define PCS1G_LPI_CFG_LPI_RX_WTIM(x)                      (((x) << 4) & GENMASK(5, 4))
0148 #define PCS1G_LPI_CFG_LPI_RX_WTIM_M                       GENMASK(5, 4)
0149 #define PCS1G_LPI_CFG_LPI_RX_WTIM_X(x)                    (((x) & GENMASK(5, 4)) >> 4)
0150 #define PCS1G_LPI_CFG_TX_ASSERT_LPIDLE                    BIT(0)
0151
0152 #define PCS1G_LPI_STATUS_RX_LPI_FAIL                      BIT(16)
0153 #define PCS1G_LPI_STATUS_RX_LPI_EVENT_STICKY              BIT(12)
0154 #define PCS1G_LPI_STATUS_RX_QUIET                         BIT(9)
0155 #define PCS1G_LPI_STATUS_RX_LPI_MODE                      BIT(8)
0156 #define PCS1G_LPI_STATUS_TX_LPI_EVENT_STICKY              BIT(4)
0157 #define PCS1G_LPI_STATUS_TX_QUIET                         BIT(1)
0158 #define PCS1G_LPI_STATUS_TX_LPI_MODE                      BIT(0)
0159
0160 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT(x)                (((x) << 8) & GENMASK(15, 8))
0161 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_M                 GENMASK(15, 8)
0162 #define PCS1G_TSTPAT_STATUS_JTP_ERR_CNT_X(x)              (((x) & GENMASK(15, 8)) >> 8)
0163 #define PCS1G_TSTPAT_STATUS_JTP_ERR                       BIT(4)
0164 #define PCS1G_TSTPAT_STATUS_JTP_LOCK                      BIT(0)
0165
0166 #define DEV_PCS_FX100_CFG_SD_SEL                          BIT(26)
0167 #define DEV_PCS_FX100_CFG_SD_POL                          BIT(25)
0168 #define DEV_PCS_FX100_CFG_SD_ENA                          BIT(24)
0169 #define DEV_PCS_FX100_CFG_LOOPBACK_ENA                    BIT(20)
0170 #define DEV_PCS_FX100_CFG_SWAP_MII_ENA                    BIT(16)
0171 #define DEV_PCS_FX100_CFG_RXBITSEL(x)                     (((x) << 12) & GENMASK(15, 12))
0172 #define DEV_PCS_FX100_CFG_RXBITSEL_M                      GENMASK(15, 12)
0173 #define DEV_PCS_FX100_CFG_RXBITSEL_X(x)                   (((x) & GENMASK(15, 12)) >> 12)
0174 #define DEV_PCS_FX100_CFG_SIGDET_CFG(x)                   (((x) << 9) & GENMASK(10, 9))
0175 #define DEV_PCS_FX100_CFG_SIGDET_CFG_M                    GENMASK(10, 9)
0176 #define DEV_PCS_FX100_CFG_SIGDET_CFG_X(x)                 (((x) & GENMASK(10, 9)) >> 9)
0177 #define DEV_PCS_FX100_CFG_LINKHYST_TM_ENA                 BIT(8)
0178 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER(x)                (((x) << 4) & GENMASK(7, 4))
0179 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_M                 GENMASK(7, 4)
0180 #define DEV_PCS_FX100_CFG_LINKHYSTTIMER_X(x)              (((x) & GENMASK(7, 4)) >> 4)
0181 #define DEV_PCS_FX100_CFG_UNIDIR_MODE_ENA                 BIT(3)
0182 #define DEV_PCS_FX100_CFG_FEFCHK_ENA                      BIT(2)
0183 #define DEV_PCS_FX100_CFG_FEFGEN_ENA                      BIT(1)
0184 #define DEV_PCS_FX100_CFG_PCS_ENA                         BIT(0)
0185
0186 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP(x)              (((x) << 8) & GENMASK(11, 8))
0187 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_M               GENMASK(11, 8)
0188 #define DEV_PCS_FX100_STATUS_EDGE_POS_PTP_X(x)            (((x) & GENMASK(11, 8)) >> 8)
0189 #define DEV_PCS_FX100_STATUS_PCS_ERROR_STICKY             BIT(7)
0190 #define DEV_PCS_FX100_STATUS_FEF_FOUND_STICKY             BIT(6)
0191 #define DEV_PCS_FX100_STATUS_SSD_ERROR_STICKY             BIT(5)
0192 #define DEV_PCS_FX100_STATUS_SYNC_LOST_STICKY             BIT(4)
0193 #define DEV_PCS_FX100_STATUS_FEF_STATUS                   BIT(2)
0194 #define DEV_PCS_FX100_STATUS_SIGNAL_DETECT                BIT(1)
0195 #define DEV_PCS_FX100_STATUS_SYNC_STATUS                  BIT(0)
0196
0197 #endif